JP2006064488A - Semiconductor tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor tester that does not have the risk of damaging a DUT, since pulse signals within the semiconductor tester are prevented from being sent out to the DUT side, even if only semiconductor relays are used as relays on a route from a pin electronics part to the DUT. <P>SOLUTION: This semiconductor tester having the pin electronics part as an output part is such that: relays on a route leading from the electronics part to a performance board are all semiconductor relays; the common connection point of a driver, a comparator, and an electronic load being parallel-connected at the electronic component, is connected to a pogo pin via a first semiconductor relay; an interrupt signal input terminal for direct-current measurement is connected to a connection point of the first semiconductor relay and the pogo pin via a series circuit of second and third semiconductor relays; and the connection points of the second and third semiconductor relays are connected to a common potential point via a fourth semiconductor relay. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor test apparatus, and more particularly to an improvement of a pin electronics section that constitutes an output section of a semiconductor test apparatus.

  Patent Document 1 discloses a technique related to the semiconductorization of a mechanical relay in a pin electronics unit that constitutes an output unit of a semiconductor test apparatus.

Japanese Patent Laid-Open No. 2001-74816

  FIG. 2 is a conceptual configuration diagram of the semiconductor test apparatus. The test head 10 is connected to the performance board 30 via, for example, a pogo pin 20. The performance board 30 is equipped with a DUT 40 to be inspected.

  A connection part of the test head 10 with the pogo pin 20 is provided with a pin electronics unit that constitutes an output unit of the semiconductor test apparatus for each pin.

  FIG. 3 is a circuit diagram showing an example of a conventional pin electronics unit, and shows an example in which the DUT 40 is a logic circuit. A driver 51, a comparator 52, and an electronic load 53 are connected to the pin electronics unit 50 in parallel. The common connection point of the driver 51, the comparator 52, and the electronic load 53 connected in parallel is connected to the pogo pin through a series circuit of the semiconductor relay SW1 and the mechanical relay SW0. An interrupt signal input terminal for direct current (DC) measurement is connected to a connection point between the semiconductor relay SW1 and the mechanical relay SW0 via the semiconductor relay SW2.

  Here, as described in paragraph 0007 of Patent Document 1, the mechanical relay SW0 is electrically connected so that an electrical signal is not applied to the DUT 40 during calibration / diagnosis of the semiconductor test apparatus itself. It is intended for separation.

  However, although the mechanical relay SW0 has a small on-resistance, it has a mechanical contact structure, and therefore has a relatively short life such as contact wear and low reliability. Therefore, as described in Patent Document 1, replacement with a semiconductor relay is being studied.

  However, paying attention to the electrical characteristics of the semiconductor relay, there is a trade-off relationship between withstand voltage / off-state capacitance / on-resistance. Of these, the capacitance at the time of off is the pulse signal inside the semiconductor testing device via this capacitance even if the semiconductor relay is controlled to be off at the time of calibration / diagnosis of the semiconductor testing device itself as described above. May be sent to the DUT side and the DUT may be damaged.

  By the way, in Patent Document 1, as described in paragraph 0018, all stages in the pin electronics 70 are configured by the semiconductor relay 75, and the pin electronics output unit and the performance board 30 are connected by the ZIF connector 32. . Here, as described in paragraph 0020, the contact 33 of the ZIF connector 32 is based on the mechanical structural principle as in the case of the mechanical relay.

  Focusing on the reliability of the entire device described in Patent Document 1, the ZIF connector having contacts based on the mechanical structure principle similar to that of the mechanical relay is dominant, and has a relatively short life and low reliability. It is considered to be.

  Further, in the apparatus described in Patent Document 1, when focusing on the range electrically controlled by the control means 79, it extends to the pin electronics 70 portion and the ZIF connector 32 portion as shown in FIG. It seems that the control system becomes complicated.

  The present invention solves such a conventional problem, and its object is to eliminate the mechanical relay from the path from the pin electronics section to the DUT, and to use only the semiconductor relay, so that the pulse inside the semiconductor test apparatus can be obtained. It is an object of the present invention to provide a semiconductor test apparatus in which no signal is transmitted to the DUT side and there is no fear of damaging the DUT.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In semiconductor test equipment with pin electronics as an output,
All the relays on the path from the pin electronics section to the DUT are semiconductor relays.

According to a second aspect of the present invention, in the semiconductor test apparatus of the first aspect,
The common connection point of the driver, the comparator, and the electronic load connected in parallel in the pin electronics unit is connected to the pogo pin via the first semiconductor relay,
An interrupt signal input terminal for DC measurement is connected to a connection point between the first semiconductor relay and the pogo pin through a series circuit of the second semiconductor relay and the third semiconductor relay,
A connection point between the second semiconductor relay and the third semiconductor relay is connected to a common potential point via a fourth semiconductor relay.

According to a third aspect of the present invention, in the semiconductor test apparatus of the first aspect,
A test head having a pin electronics unit as an output unit is connected to the DUT through a pogo pin.

  According to the present invention, although all the relays in the path from the pin electronics section to the DUT are semiconductor relays, the semiconductor test apparatus internal pulse signal is not sent to the DUT side, and there is no possibility of damaging the DUT. A test device can be realized.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a specific example of the present invention, and the same reference numerals are given to portions common to FIG. In FIG. 1, the common connection point of the driver 51, the comparator 52, and the electronic load 53 connected in parallel is connected to the pogo pin via the semiconductor relay SW1. An interrupt signal input terminal for direct current (DC) measurement is connected to a connection point between the semiconductor relay SW1 and the pogo pin through a series circuit of the semiconductor relay SW2 and the semiconductor relay SW3. A connection point between the semiconductor relay SW2 and the semiconductor relay SW3 is connected to a common potential point via the semiconductor relay SW4.

  In such a configuration, the semiconductor relays SW1 to SW4 are on / off controlled in accordance with the operation modes (A) to (C) described below.

(A) Function operation SW1 ON SW2 OFF SW3 OFF SW4 ON Since the semiconductor relay SW1 is ON, the common connection point of the driver 51, the comparator 52, and the electronic load 53 connected in parallel is pogo-pin via the semiconductor relay SW1. Connected to. At this time, since the semiconductor relay SW2 and the semiconductor relay SW3 are turned off, the DC measurement interrupt signal is not applied to the connection point between the semiconductor relay SW1 and the pogo pin. Further, since the semiconductor relay SW4 is turned on, the potential at the connection point between the semiconductor relay SW2 and the semiconductor relay SW3 is held at the common potential point.
As a result, various tests on the DUT are performed using the driver 51, the comparator 52, and the electronic load 53 connected in parallel.

(B) DC system measurement SW1 off SW2 on SW3 on SW4 off Since the semiconductor relay SW1 is off, the common connection point of the driver 51, the comparator 52, and the electronic load 53 connected in parallel is when the semiconductor relay SW1 is off. It is connected to the pogo pin through a capacitance. At this time, since the semiconductor relay SW2 and the semiconductor relay SW3 are turned on, a DC measurement interrupt signal is applied to the connection point between the semiconductor relay SW1 and the pogo pin. Here, since the semiconductor relay SW4 is off, the potential at the connection point between the semiconductor relay SW2 and the semiconductor relay SW3 is not held at the common potential point.
Thereby, the DC test for the DUT is performed based on the interrupt signal for DC measurement.
(C) Calibration / diagnosis of the semiconductor test apparatus itself SW1 off SW2 on SW3 off SW4 on Since the semiconductor relay SW1 is off, the common connection point of the driver 51, the comparator 52, and the electronic load 53 connected in parallel is a semiconductor. The relay SW1 is connected to the pogo pin through the off-time capacitance. At this time, since the semiconductor relay SW2 and the semiconductor relay SW4 are turned on, the semiconductor relay SW1 is also connected to the common potential point through the off-state capacitance of the semiconductor relay SW1. The off-state capacitance of the semiconductor relay SW1 becomes a load of the driver 51. When viewed from the pogo pin (DUT) side, the output of the pin electronics unit is connected to a common potential point, and the pulse output of the pin electronics unit used for calibration / diagnosis of the semiconductor test equipment itself adversely affects the DUT. There is no.

  According to such a configuration, all the relays in the path from the pin electronics unit 50 to the performance board 30 are semiconductor relays, but the pulse signal inside the semiconductor test apparatus is not sent to the DUT 40 side, and the DUT 40 is damaged. A semiconductor test apparatus can be realized with no fear of failure.

  And since all the relays of the path from the pin electronics unit 50 to the performance board 30 are semiconductor relays, the life of the entire semiconductor test apparatus can be extended and the reliability can be improved, and since there is no mechanical relay, these Control of the relay becomes easy.

It is a block diagram which shows the specific example of this invention. 1 is a conceptual configuration diagram of a semiconductor test apparatus. It is a circuit diagram which shows an example of the conventional pin electronics part.

Explanation of symbols

10 Test head 20 Pogo pin 30 Performance board 40 DUT
50-pin electronics section 51 driver 52 comparator 53 electronic loads SW1 to SW4 semiconductor relay

Claims (3)

In semiconductor test equipment with pin electronics as an output,
A semiconductor test apparatus characterized in that all the relays in the path from the pin electronics section to the DUT are semiconductor relays. The common connection point of the driver, the comparator, and the electronic load connected in parallel in the pin electronics unit is connected to the pogo pin via the first semiconductor relay,
An interrupt signal input terminal for DC measurement is connected to a connection point between the first semiconductor relay and the pogo pin through a series circuit of the second semiconductor relay and the third semiconductor relay,
2. The semiconductor test apparatus according to claim 1, wherein a connection point between the second semiconductor relay and the third semiconductor relay is connected to a common potential point via a fourth semiconductor relay.   2. The semiconductor test apparatus according to claim 1, wherein a test head having a pin electronics part as an output part is connected to the DUT through a pogo pin.

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