JP2006059968A - Semiconductor device and its manufacturing method, ferroelectric capacitor structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a stack capacitor structure of lower electrode/ferroelectric film/upper electrode, in which excess capacitor structure is eliminated from a lower electrode and crystal orientation of the lower electrode and the overlying ferroelectric film is enhanced, and to provide its manufacturing method and a ferroelectric capacitor structure. <P>SOLUTION: The semiconductor device comprises a transistor element 12 formed on a semiconductor substrate 11, an insulating film 13 covering the transistor element 12, a conductive plug 14 penetrating the insulating film 13 and being connected with the source S of the transistor element 12, and a ferroelectric capacitor C1 formed on the insulating film 13 and constituted of a lower electrode 15 being connected with the conductive plug 14, a ferroelectric film 16 and an upper electrode 17. At least the lower electrode 15 is arranged with an interlayer film 152 for enhancing ferroelectric characteristics and includes a first multilayer portion L1, consisting of a first electrode member layer 151/the interlayer film 152/a second electrode member layer 153 from the conductive plug 14 side, and a second multilayer portion L2, where the interlayer film 152 is removed and the first electrode member layer 151 is connected with the second electrode member layer 153. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a stacked capacitor structure of lower electrode / ferroelectric film / upper electrode, a manufacturing method thereof, and a ferroelectric capacitor structure.

  A ferroelectric memory is one of nonvolatile memories excellent in high speed, low power consumption, high integration, and rewrite resistance. When the ferroelectric memory has a stacked capacitor structure, a capacitor of lower electrode / ferroelectric film / upper electrode is formed on a contact plug such as W connected to the transistor element. As a matter of course, the lower electrode is made of a conductive material that is electrically connected to the contact plug.

Ferroelectric material of the ferroelectric film is PZT: For _{((PbZr X Ti 1-X} O 3) based lead zirconate titanate-based), Pt used for the lower electrode, the crystalline orientation thereof is important . That is, in the ferroelectric capacitor, by improving the Pt (111) crystal orientation, the (111) crystal orientation of PZT is inherited and good characteristics are obtained.

The crystal orientation of Pt varies depending on the underlying material. In general, Ti and TiO _X are suitably used as a base material for property evaluation relating to a ferroelectric material. For example, the film quality and ferroelectric characteristics of PZT are evaluated using an underlying material such as a SiO ₂ / Ti / Pt laminate or a SiO ₂ / TiO _X / Pt laminate as an electrode. Thereby, the crystal orientation of Pt (Pt (111)) can be expected, and the crystal orientation of PZT is also improved. Therefore, good characteristics can be obtained.

Further, the prior art has disclosed that when forming a ferroelectric film, the lower electrode constitutes a flat surface without underlying irregularities (see, for example, Patent Document 1). Here, a TiO ₂ film is used for the barrier metal of the lower electrode, and Pt is used for the lower electrode. After the patterning of the lower electrode, the surface of the lower electrode is planarized by a CMP (Chemical Mechanical Polishing) method together with the interlayer insulating film. Although this [Patent Document 1] does not disclose the crystal orientation of the ferroelectric film, it is possible to form a ferroelectric film having good film characteristics on a flat lower electrode without underlying irregularities. It is said.
JP 2000-138349 A (page 3, FIG. 1)

The above-described TiO ₂ film or TiO _X film is an insulating film. The lower electrode is connected to the contact plug, but includes a parasitic capacitor formed of a TiO _X film.
Further, as the lower electrode, it is considered to form a base material by the above-described lamination of SiO ₂ / Ti / Pt. It is well known that Pt is a material that allows oxygen to pass through. In addition, PZT requires heat treatment to recover damage due to process deterioration. Here, PZT undergoes a crystallization annealing process in a high-temperature oxygen atmosphere. Therefore, even if Ti is used as the base material, it is oxidized as Ti + O ₂ → TiO _{X in} a high-temperature oxygen atmosphere such as the PZT crystallization annealing, so that an insulating film is formed.

For this reason, the ferroelectric capacitor has a series capacitor of PZT and TiO _X. Considering the characteristics as a ferroelectric memory, the presence of a parasitic capacitor due to TiO _X may have an adverse effect on further miniaturization.

  The present invention has been made in view of the above circumstances, and eliminates an unnecessary capacitor structure in the lower electrode and improves the crystal orientation of the lower electrode and the ferroelectric film thereon. It is an object of the present invention to provide a semiconductor device having a ferroelectric capacitor / upper electrode stack capacitor structure, a method of manufacturing the same, and a ferroelectric capacitor structure.

  A semiconductor device according to the present invention includes a transistor element formed on a semiconductor substrate, an insulating film formed on the semiconductor substrate and covering the transistor element, and penetrating the insulating film and connected to a predetermined portion of the transistor element. A ferroelectric plug comprising: a lower electrode formed on the insulating film and connected to the conductive plug; a ferroelectric film on the lower electrode; and an upper electrode on the ferroelectric film A capacitor, and at least the lower electrode is provided with an interlayer film for improving ferroelectric characteristics, and a first stacked layer comprising a first electrode member layer / an interlayer film / a second electrode member layer from the conductive plug side. There is a portion and a second laminated portion in which the interlayer film is removed and the first electrode member layer and the second electrode member layer are connected.

  According to the semiconductor device of the present invention, even if the interlayer film undergoes an oxidation reaction during the process, and the interlayer film finally becomes an insulating film, the second stacked portion is present, so that the series connection to the ferroelectric capacitor is present. No parasitic capacitor. The interlayer film is a film useful for improving the ferroelectric characteristics, and affects the crystal orientation of the ferroelectric film.

In addition, the semiconductor device according to the present invention contributes to improvement of characteristics as a ferroelectric capacitor by having any of the following features.
The interlayer film is a film that affects at least the crystal orientation of the second electrode member.
The area of the first stacked portion is larger than the area of the second stacked portion.
The second stacked portion is provided immediately above the conductive plug.
The second laminated portion is provided in the vicinity of the periphery of the lower electrode.
The interlayer film is a film containing at least Ti or Al.
The first electrode member layer includes at least a first conductive layer having adhesion and diffusion barrier properties with the conductive plug, and a second conductive layer having at least an anti-oxidation function covering the first conductive layer. Features.
The second electrode member layer includes Pt, and the ferroelectric film includes Pb.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a transistor element on a substrate, a step of forming an insulating film covering the transistor element on the substrate, a through-hole of the insulating film, and Forming a conductive plug connected to a predetermined portion; and forming a first electrode member layer having at least diffusion / reaction barrier properties as a part of the lower electrode on the insulating film including the conductive plug. A step of forming an interlayer film for enhancing the crystal orientation of the upper layer on the first electrode member layer, a step of forming a removal region of the interlayer film exposing the first electrode member layer, and the first Forming a second electrode member layer which is a part of a lower electrode on the interlayer film including the electrode member layer; forming a ferroelectric film on the second electrode member layer; and At least before on the body membrane Forming an upper electrode member including the same electrode member layer as the second electrode member layer; patterning all member layers of the upper electrode member, the ferroelectric film, and the lower electrode into a predetermined capacitor shape; ,including.

  According to the method for manufacturing a semiconductor device according to the present invention, the lower electrode is formed by forming the first electrode member layer and the second electrode member layer, and an interlayer film between the upper electrode, that is, the second electrode member layer, for improving the crystal orientation of the upper electrode. It becomes. Even if the interlayer film undergoes an oxidation reaction during the process, and the interlayer film eventually becomes an insulating film, a removal region of the interlayer film is formed in advance, so that the first electrode member layer and the second electrode member layer are securely With a connection area. Therefore, a capacitor in series with the ferroelectric capacitor is not formed. Inheriting the crystal orientation of the second electrode member layer, the ferroelectric film also has a high crystal orientation.

In addition, the method for manufacturing a semiconductor device according to the present invention contributes to improvement of characteristics as a ferroelectric capacitor by having any of the following characteristics.
The step of forming the interlayer film is characterized in that a film containing Ti or Al is formed through the use of at least a sputtering method, a solution method, or a CVD method.
The interlayer film removal region is formed in a region in the vicinity of the peripheral portion of the capacitor shape other than a region including immediately above the conductive plug or a region immediately above the conductive plug.
The step of forming the ferroelectric film is characterized by crystallizing a ferroelectric material having a desired film thickness by a sol-gel method by heat treatment.

  Further, the present invention provides a ferroelectric capacitor structure having a ferroelectric film as a capacitor insulating film, and is connected to a lower electrode and an upper electrode sandwiching the ferroelectric film, and a region at or near the center of the lower electrode. The lower electrode is provided with an interlayer film for improving crystal orientation of at least the upper layer in a predetermined region, and the first electrode member layer / interlayer film / second electrode member layer from the conductive member side. And a second laminated portion in which the first electrode member layer and the second electrode member layer are connected in a region smaller than the first laminated portion.

  According to the ferroelectric capacitor structure of the present invention, the lower electrode is provided with the interlayer film for improving the crystal orientation of at least the upper layer. Even if the interlayer film undergoes an oxidation reaction during the process and eventually the interlayer film becomes an insulating film, the second stacked portion is present, so that no capacitor in series with the ferroelectric capacitor is parasitic.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a cross-sectional view showing a main part of a semiconductor device according to the first embodiment of the present invention. The structure of a ferroelectric memory cell is shown. One memory cell is composed of one selection transistor and one ferroelectric capacitor.
On the conductor substrate 11, a selection transistor 12 made of a MOS field effect transistor element is formed. The drain D of the selection transistor 12 is connected to a selection line (bit line) (not shown). The gate G of the selection transistor 12 functions as a control line (word line). The source S of the selection transistor 12 is connected to the ferroelectric capacitor C1 through the conductive plug 14. The ferroelectric capacitor C1 includes a lower electrode 15, a ferroelectric film 16 on the lower electrode 15, and an upper electrode 17 on the ferroelectric film 16.

  The conductive plug 14 penetrates through the insulating film 13 between the layers, the bottom is connected to the source S of the selection transistor 12, and the upper end is connected to the lower electrode 15 of the ferroelectric capacitor C1. The conductive plug 14 is, for example, a W (tungsten) plug. When the conductive plug 14 is a W plug, a barrier metal (not shown) is interposed in the contact portion between the insulating film 13 inner wall and the source S.

  The lower electrode 15 of the ferroelectric capacitor C1 has a region of about 1 μm square, for example, with the conductive plug 14 being substantially at the center. The lower electrode 15 includes the first electrode member layer 151 / the first laminated portion L1 formed of the first electrode member layer 151 / the interlayer film 152 / the second electrode member layer 153 from the conductive plug 14 side, and the first electrode member layer 151 from which the interlayer film 152 is removed. There is a second laminated portion L2 to which the second electrode member layer 153 is connected.

The first electrode member layer 151 includes a first conductive layer 151a and a second conductive layer 151b. The first conductive layer 151a uses TiN or TiAlN as an adhesion to the conductive plug 14 and a diffusion / reaction barrier. Also in the second conductive layer 151b, Ir or Ir / IrO _X laminated layer or IrO _X having diffusion / reaction barrier properties and rich in anti-oxidation function of the lower layer is used. As described above, the first electrode member layer 151 is a diffusion / reaction barrier with the conductive plug 14 (for example, W) as a whole, and a layer that particularly plays a role of preventing oxidation.
Since the second electrode member layer 153 is in contact with the ferroelectric film 16, a noble metal having excellent heat and chemical stability is used. Here, Pt is used as the second electrode member layer 153.

The interlayer film 152 is a Ti, TiO _X, or AlO _X film. The crystal orientation (Pt (111)) of the second electrode member layer 153 formed on these films, that is, Pt is increased. Further, when the ferroelectric film 16 is PZT, by improving the Pt (111) crystal orientation, the (111) crystal orientation of the PZT is inherited, and good characteristics can be obtained.

  Such an interlayer film 152 is a thin film of about 30 nm or a thin film of 30 nm or less. As a result, the level difference between the first stacked portion L1 and the second stacked portion L2 is reduced to minimize crystal disturbance. The region of the first stacked portion L1 is larger than the region of the second stacked portion L2. Thereby, the region where the Pt (111) crystal orientation of the second electrode member layer 153 is good is increased, and the film quality and ferroelectric properties of the ferroelectric film 16 are improved. In this embodiment, the region of the second stacked portion L2 is provided immediately above the conductive plug 14. The region of the second stacked portion L2 is preferably smaller than the diameter of the conductive plug 14.

In the upper electrode 17, Pt is in contact with the ferroelectric film 16 as in the second electrode member layer 153. The upper electrode 17 may have a laminated structure containing Pt. The upper electrode 17 is preferably provided with an Ir / IrO _X stack or IrO _X on the Pt film in the same manner as the second conductive layer 151b. In this case, the Pt film has a thickness of about 0 to 100 nm, and the Pt film may not be provided. The upper electrode 17 may be configured to be supplied with a reference potential (plate potential or the like) by connecting another wiring (not shown).

2 to 5 are cross-sectional views illustrating an example of a method of manufacturing a semiconductor device having the configuration as shown in FIG. 1 in the order of steps according to the second embodiment of the present invention. The same parts as those in FIG. 1 will be described with the same reference numerals.
As shown in FIG. 2, a MOS field effect transistor 12 is formed on a semiconductor substrate 11. That is, in the element region having a predetermined impurity concentration of the semiconductor substrate 11, the gate oxide film 21 and the polysilicon layer 22 are sequentially formed on the channel region, and the gate electrode G is patterned. Next, source / drain regions S / D are formed. Here, a source / drain region S / D having an LDD (Lightly Doped Drain) structure, that is, a so-called extension region may be formed. In that case, first, the low concentration region 23 is formed by impurity ion implantation using the region of the gate electrode G as a mask. Next, after depositing an insulating film so as to cover the gate electrode G by a CVD (Chemical Vapor Deposition) method, a spacer 24 is formed by anisotropic dry etching. Next, using the regions of the gate electrode G and the spacer 24 as a mask, the source / drain high concentration region 25 is formed by impurity ion implantation to form the source / drain region S / D. Although not shown, the polysilicon layer 22 of the gate G may be silicided. Further, the source S and the drain D may be structured using a silicided salicide process. In this way, the selection transistor 12 made of a MOS field effect transistor element is formed.

  Next, an interlayer insulating film 13 covering the selection transistor 12 is formed. During this time, a selection line (bit line) connected to the drain D may be formed according to a necessary process (not shown). The insulating film 13 is planarized using an etch back method or a CMP (Chemical Mechanical Polishing) technique, and an opening 26 reaching the source S is formed using a lithography technique. After coating the inner wall of the opening 26 with a barrier film 27 such as TiN or TaN, W is formed using a CVD method, and is embedded through a CMP technique. Thereby, the conductive plug 14 is formed. The conductive plug 14 is not limited to such a W plug. For example, a polysilicon plug may be used as the conductive plug 14.

Next, a TiAlN film is formed on the insulating film 13 including the conductive plug 14 as a first electrode member layer 151 which is a part of the lower electrode 15 by a sputtering method to a thickness of about 100 nm (first conductive layer 151a). Next, an Ir film is formed to a thickness of about 100 nm on the TiAlN film by a sputtering method (second conductive layer 151b). On this Ir film, Ti is deposited as an interlayer film 152 by a sputtering method. Then, a TiO _X film having a thickness of about 30 nm is obtained through furnace oxidation. In addition, the TiO _X film may be formed by sputtering in an oxygen atmosphere using Ti as a target or sputtering using TiO _X as a target. Further, a TiO _X film can be formed by a subsequent thermal oxidation using a solution method.

Next, as shown in FIG. 3, the interlayer film 152 (TiO _X film) is patterned through a photolithography process and an etching process. Thus, the first electrode member layer 151 top surface, a coated region of the TiO _X film, a region where Ir film TiO _X film is removed is exposed there. Here, the removal region CNT of the interlayer film 152 is provided directly above the conductive plug 14 and smaller than the diameter of the conductive plug 14.

  Next, as shown in FIG. 4, a second electrode member layer 153 that is a part of the lower electrode 15 is formed on the interlayer film 152 including the first electrode member layer 151. The second electrode member layer 153 is a Pt film and is formed with a thickness of about 100 nm by a sputtering method. Next, the ferroelectric film 16 is formed on the second electrode member layer 153. The ferroelectric film 16 is PZT formed by a sol-gel method. The composition ratio of PZT was Pb: Zr: Ti = 110: 40: 60, and the film thickness was 150 nm. The PZT crystallization conditions are, for example, heat treatment in an oxygen atmosphere, 600 ° C., and about 5 minutes.

Next, an upper electrode member layer 17s, here a Pt film, is formed on the ferroelectric film 16 made of PZT by sputtering to a thickness of about 200 nm. Note that the upper electrode member layer 17s may be provided with an Ir / IrO _X stack or IrO _X on the Pt film, similarly to the second conductive layer 151b. In this case, the Pt film has a thickness of about 0 to 100 nm, and the Pt film may be omitted.

  Next, as shown in FIG. 5, the shape of the ferroelectric capacitor C1 is obtained through a photolithography process and an etching process. That is, the upper electrode member layer 17s, the ferroelectric film 16, the second electrode member layer 153, the interlayer film 152, and the first electrode member layer 151 (151b) in the region not covered with the resist mask (broken line) formed in the predetermined region. 151a) is removed with physical etching, trimming, and the like. Thereafter, the ferroelectric film 16 is stabilized through heat treatment or the like. Thereby, a configuration as shown in FIG. 1 is obtained. Thereafter, although not shown, an interlayer insulating film or protective film is formed. A configuration in which a reference potential (plate potential or the like) is applied by connecting the upper electrode 17 to another wiring may be employed.

According to the configuration and method according to the first and second embodiments, the lower electrode 15 including the first stacked portion L1 where the interlayer film 152 is interposed and the second stacked portion L2 where the interlayer film 152 is not interposed, the ferroelectric layer A structure of the ferroelectric capacitor C1 including the body film 16 and the upper electrode 17 is obtained. The interlayer film 152 is a film containing Ti and has an effect of increasing the Pt crystal orientation (Pt (111)) of the second electrode member layer 153. Furthermore, the crystal orientation (111) of PZT of the ferroelectric film 16 is enhanced, and good ferroelectric properties can be obtained. Even if the interlayer film 152 becomes a TiO _x film and becomes an insulating film during the process, the second stacked portion L2 exists, and therefore no extra capacitor in series with the ferroelectric capacitor C1 is parasitic. As a result, a highly reliable ferroelectric memory that does not deteriorate the capacitor characteristics can be configured.

  6 to 8 are cross-sectional views showing a semiconductor device including a pattern modification example of the interlayer film 152 in the first and second embodiments and a method for manufacturing the same according to the third embodiment of the present invention. FIG. 6 corresponds to FIG. 3, and the interlayer film 152 has a different pattern. The removal region CNT of the interlayer film 152 is formed in the vicinity of the peripheral portion of the capacitor shape other than the region immediately above the conductive plug 14. The interlayer film 152 is provided directly above the conductive plug 14 and larger than the diameter of the conductive plug 14. The subsequent steps leading to the configuration shown in FIGS. 7 and 8 are in accordance with the second embodiment (FIGS. 4 and 5). Thus, the ferroelectric capacitor C2 including the lower electrode 15, the ferroelectric film 16, and the upper electrode 17 including the first stacked portion L1 with the interlayer film 152 interposed therebetween and the second stacked portion L2 without the interlayer film 152 interposed therebetween. The following structure is obtained.

The same effects as those of the first and second embodiments can also be obtained by the configuration and method according to the third embodiment. That is, the interlayer film 152 is made of a film containing Ti, and has an effect of increasing the Pt crystal orientation (Pt (111)) of the second electrode member layer 153. Furthermore, the crystal orientation (111) of PZT of the ferroelectric film 16 is enhanced, and good ferroelectric properties can be obtained. Even if the interlayer film 152 becomes a TiO _x film and becomes an insulating film during the process, the second stacked portion L2 exists, and therefore no extra capacitor in series with the ferroelectric capacitor C1 is parasitic. As a result, a highly reliable ferroelectric memory that does not deteriorate the capacitor characteristics can be configured.

In the second and third embodiments, the first electrode member layer 151 uses a TiAlN film as the first conductive layer 151a. However, a TiN film may be used instead of the TiAlN film. Further, although an Ir film is formed as the second conductive layer 151b, an Ir / IrO _X stacked layer or an IrO _X film is obtained through a process. Further, although the TiO _X film is formed as the interlayer film 152, Ti may be formed at first, and the TiO _X film may be formed as the process proceeds. In addition, it is conceivable that an AlO _X film is used as the interlayer film 152. The AlO _X film also has chemical stability, and can be employed from the viewpoint of increasing the crystal orientation (Pt (111)) of the upper layer, thereby increasing the (111) crystal orientation of PZT.

  As described above, according to the present invention, the lower electrode of the ferroelectric capacitor is in contact with the ferroelectric film and the first electrode member layer serving as a diffusion / reaction barrier such as adhesion to the conductive plug and prevention of oxidation. A predetermined region is formed between the second electrode member layers and an upper layer, that is, an interlayer film for improving the crystal orientation of the second electrode member layers. Even if the interlayer film undergoes an oxidation reaction during the process, and the interlayer film eventually becomes an insulating film, the removal region of the interlayer film is formed, so the first electrode member layer and the second electrode member layer are securely It has a configuration with a connection area. Therefore, no capacitor in series with the ferroelectric capacitor is formed. Inheriting the crystal orientation of the second electrode member layer, the ferroelectric film also has a high crystal orientation. As a result, a highly reliable ferroelectric memory that does not deteriorate the capacitor characteristics can be configured. As a result, a semiconductor having a stack capacitor structure of a lower electrode / ferroelectric film / upper electrode that eliminates an extra capacitor structure in the lower electrode and improves the crystal orientation of the lower electrode and the ferroelectric film thereon. An apparatus, a manufacturing method thereof, and a ferroelectric capacitor structure can be provided.

Sectional drawing which shows the principal part of the semiconductor device which concerns on 1st Embodiment. The 1st sectional view showing the manufacturing method of the semiconductor device concerning a 2nd embodiment in order of a process. The 2nd sectional view following Drawing 2. FIG. 4 is a third sectional view following FIG. 3. FIG. 5 is a fourth cross-sectional view following FIG. 4. The 1st sectional view showing the semiconductor device concerning a 3rd embodiment, and a manufacturing method in order of a process. The 2nd sectional view following Drawing 6. FIG. 8 is a third cross-sectional view following FIG. 7.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate, 12 ... Selection transistor (MOS type field effect transistor element), 13 ... Insulating film, 14 ... Conductive plug, 15 ... Lower electrode, 151 ... 1st electrode member layer, 151a ... 1st conductive layer, 151b ... second conductive layer, 152 ... interlayer film, 153 ... second electrode member layer, 16 ... ferroelectric film, 17 ... upper electrode, 17s ... upper electrode member layer, 21 ... gate oxide film, 22 ... polysilicon layer, 23 ... Low concentration region of source / drain, 24 ... Spacer, 25 ... High concentration region of source / drain, 26 ... Opening portion, 27 ... Barrier film, L1 ... First laminated portion, L2 ... Second laminated portion, C1 , C2 ... Ferroelectric capacitor, S ... Source, D ... Drain, G ... Gate (control line, word line), CNT ... Removal region of interlayer film.

Claims (13)

A transistor element formed on a semiconductor substrate;
An insulating film formed on the semiconductor substrate and covering the transistor element;
A conductive plug passing through the insulating film and connected to a predetermined portion of the transistor element;
A lower electrode formed on the insulating film and connected to the conductive plug; a ferroelectric film on the lower electrode; a ferroelectric capacitor including an upper electrode on the ferroelectric film;
At least the lower electrode is provided with an interlayer film for improving ferroelectric characteristics, and a first laminated portion composed of a first electrode member layer / interlayer film / second electrode member layer from the conductive plug side, and the interlayer A semiconductor device having a second stacked portion in which a film is removed and the first electrode member layer and the second electrode member layer are connected. The semiconductor device according to claim 1, wherein the interlayer film is a film that acts on crystal orientation of at least the second electrode member. The semiconductor device according to claim 1, wherein an area of the first stacked portion is larger than an area of the second stacked portion. The semiconductor device according to claim 1, wherein the second stacked portion is provided immediately above the conductive plug. The semiconductor device according to claim 1, wherein the second stacked portion is provided near a periphery of the lower electrode. The semiconductor device according to claim 1, wherein the interlayer film is a film containing at least Ti or Al. The first electrode member layer includes at least a first conductive layer having adhesion and diffusion barrier properties with the conductive plug, and a second conductive layer having at least an anti-oxidation function covering the first conductive layer. The semiconductor device according to any one of 1 to 6. The semiconductor device according to claim 1, wherein the second electrode member layer includes Pt, and the ferroelectric film includes Pb. Forming a transistor element on the substrate;
Forming an insulating film covering the transistor element on the substrate;
Forming a conductive plug penetrating the insulating film and connected to a predetermined portion of the transistor element;
Forming a first electrode member layer having at least diffusion / reaction barrier properties, which is a part of the lower electrode, on the insulating film including the conductive plug;
Forming an interlayer film for enhancing the crystal orientation of the upper layer on the first electrode member layer;
Forming a removal region of the interlayer film exposing the first electrode member layer;
Forming a second electrode member layer that is a part of a lower electrode on the interlayer film including the first electrode member layer;
Forming a ferroelectric film on the second electrode member layer;
Forming an upper electrode member on the ferroelectric film;
Patterning all member layers of the upper electrode member, the ferroelectric film, and the lower electrode into a predetermined capacitor shape;
A method of manufacturing a semiconductor device including: 10. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the interlayer film forms a film containing Ti or Al through at least a sputtering method, a solution method, or a CVD method. 11. The removal region of the interlayer film is formed in a region in the vicinity of the peripheral portion of the capacitor shape other than a region including immediately above the conductive plug or a region directly above the conductive plug. Semiconductor device manufacturing method. 12. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the ferroelectric film crystallizes by heat-treating a ferroelectric material having a desired film thickness by a sol-gel method. Method. In the ferroelectric capacitor structure in which the ferroelectric film is a capacitor insulating film,
A lower electrode and an upper electrode sandwiching the ferroelectric film;
A conductive member connected to the center of the lower electrode or a region in the vicinity thereof,
The lower electrode is provided with an interlayer film for enhancing crystal orientation of at least an upper layer in a predetermined region, and a first laminated portion composed of a first electrode member layer / interlayer film / second electrode member layer from the conductive member side; A ferroelectric capacitor structure in which a second multilayer portion in which the first electrode member layer and the second electrode member layer are connected is present in a region smaller than the first multilayer portion.

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