JP2006059871A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006059871A
JP2006059871A JP2004237540A JP2004237540A JP2006059871A JP 2006059871 A JP2006059871 A JP 2006059871A JP 2004237540 A JP2004237540 A JP 2004237540A JP 2004237540 A JP2004237540 A JP 2004237540A JP 2006059871 A JP2006059871 A JP 2006059871A
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semiconductor
semiconductor device
semiconductor elements
substrate
heat
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JP4237116B2 (en
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Katsuyoshi Matsumoto
克良 松本
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To improve heat dissipation performance in a laminated multichip semiconductor device having a plurality of semiconductor elements, and also to reduce mutual electrical interference among the semiconductor elements. <P>SOLUTION: A heatsink 3 partly exposing over on the upper surface of the semiconductor device is arranged between two facing semiconductor elements 1A and 1B. In addition, the heatsink 3 is connected with a connection pattern formed on a substrate 2 by using a wire, and it is electrically connected at a constant potential. Thus, when the semiconductor element generates heat, the heat is conducted to the outside through the heatsink. As a result, the heat dissipation performance of the laminated multichip semiconductor device having a plurality of semiconductor elements is improved so as to reduce electrical mutual interference among the semiconductor elements. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、配線基板上に積層して搭載された複数の半導体素子を有する積層型マルチチップ半導体装置の放熱性能を高め、半導体素子間の電気的な相互干渉を緩和することができる半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device capable of enhancing the heat dissipation performance of a multilayer multichip semiconductor device having a plurality of semiconductor elements stacked and mounted on a wiring board, and mitigating electrical mutual interference between the semiconductor elements, and It relates to the manufacturing method.

近年、半導体装置の単位面積あたりの半導体素子の高密度化が求め続けられているが、チップ中の回路素子の高密度化と平行して、半導体素子を１つの半導体装置内に複数積層するマルチチップ構造の半導体装置が製造されている。   In recent years, high density of semiconductor elements per unit area of a semiconductor device has been continuously demanded. In parallel with high density of circuit elements in a chip, a multi-layer in which a plurality of semiconductor elements are stacked in one semiconductor device. A semiconductor device having a chip structure is manufactured.

以下従来例としてワイヤボンディングタイプの半導体装置であるＰＢＧＡを例に、図５によって説明する。   Hereinafter, a PBGA which is a wire bonding type semiconductor device will be described as an example of the prior art with reference to FIG.

図５（ａ）は半導体装置の断面図、図５（ｂ）は半導体装置の上面から見た透過図である。概略でいうと、この半導体装置は半導体素子１Ａ，１Ｂ、半導体基板２、熱伝導性接着剤４Ａ，４Ｂ、ボンディングワイヤ５Ａ，５Ｂ、封止樹脂６、外部電極７を有している。   5A is a cross-sectional view of the semiconductor device, and FIG. 5B is a transparent view seen from the top surface of the semiconductor device. Generally speaking, this semiconductor device includes semiconductor elements 1A and 1B, a semiconductor substrate 2, thermally conductive adhesives 4A and 4B, bonding wires 5A and 5B, a sealing resin 6 and an external electrode 7.

次にこの製造工程を図６によって説明する。概略でいうと、まず図６（ａ）のように半導体基板２の１主面に熱伝導性接着剤４Ａを塗布し、半導体素子１Ａの裏面を搭載する。次に図６（ｂ）のように半導体素子１Ａの表面に熱伝導性接着剤４Ｂを塗布し、半導体素子１Ｂの裏面を搭載する。引き続き図６（ｃ）のように半導体基板２の１主面に形成された接続パターン（図示せず）と半導体素子１Ａまたは１Ｂの表面に形成された接続パターン（図示せず）の間をボンディングワイヤ５Ａまたは５Ｂによって電気的に接続する。続いて図６（ｄ）のように金型８を使用し、封止樹脂６によって半導体基板２上を封止する。最後に図６（ｅ）のように外部電極７を半導体基板２の下面に形成された接続パターンに搭載する。   Next, this manufacturing process will be described with reference to FIG. In summary, first, as shown in FIG. 6A, a heat conductive adhesive 4A is applied to one main surface of the semiconductor substrate 2, and the back surface of the semiconductor element 1A is mounted. Next, as shown in FIG. 6B, the heat conductive adhesive 4B is applied to the surface of the semiconductor element 1A, and the back surface of the semiconductor element 1B is mounted. Subsequently, as shown in FIG. 6C, bonding is performed between a connection pattern (not shown) formed on one main surface of the semiconductor substrate 2 and a connection pattern (not shown) formed on the surface of the semiconductor element 1A or 1B. They are electrically connected by wires 5A or 5B. Subsequently, as shown in FIG. 6D, the mold 8 is used and the semiconductor substrate 2 is sealed with the sealing resin 6. Finally, as shown in FIG. 6E, the external electrode 7 is mounted on the connection pattern formed on the lower surface of the semiconductor substrate 2.

半導体素子１Ａ，１Ｂの素材には主にシリコンが用いられる。半導体基板２はガラスエポキシ製のものなどが用いられる。熱伝導性接着剤４Ａ，４Ｂの材料としてはエポキシ樹脂などが用いられる。ワイヤボンディング５Ａ，５Ｂとしては金線が用いられることが多い。封止樹脂６としては例えばエポキシ樹脂などが用いられ、外部電極７としては半田バンプなどの形態が取られ、半田バンプの材料としては低弾性である共晶半田が用いられることが多い。   Silicon is mainly used as a material for the semiconductor elements 1A and 1B. The semiconductor substrate 2 is made of glass epoxy. An epoxy resin or the like is used as a material for the heat conductive adhesives 4A and 4B. Gold wires are often used as the wire bonding 5A and 5B. For example, epoxy resin or the like is used as the sealing resin 6, a form such as a solder bump is used as the external electrode 7, and eutectic solder having low elasticity is often used as the material of the solder bump.

従来技術としては、半導体素子上に放熱体を配置し、この放熱体の一部が半導体基板上に接続される構造にすることによって、半導体素子の発熱を半導体基板側に伝導させるというものがあった（例えば特許文献１参照）。
特開２０００−７７５７５公報 As a conventional technique, a heat dissipating body is disposed on a semiconductor element, and a part of the heat dissipating body is connected to the semiconductor substrate to conduct heat generated by the semiconductor element to the semiconductor substrate side. (See, for example, Patent Document 1).
JP 2000-77575 A

しかしながら、１つの半導体装置内に複数の半導体素子を有する積層型マルチチップ半導体装置においては、発熱体である半導体素子が複数になるために、従来よりも高い放熱性能が必要になる。   However, in a multi-chip semiconductor device having a plurality of semiconductor elements in one semiconductor device, since there are a plurality of semiconductor elements that are heating elements, higher heat dissipation performance than before is required.

また異なる機能を持つ半導体素子が隣接して配置されることになる積層型マルチチップ半導体装置においては、半導体素子間の電気的な相互干渉が無視できなくなる。このため半導体素子間の電気的な相互干渉を緩和するための対策が必要になる。   In a stacked multichip semiconductor device in which semiconductor elements having different functions are arranged adjacent to each other, electrical mutual interference between the semiconductor elements cannot be ignored. For this reason, it is necessary to take measures to alleviate electrical mutual interference between semiconductor elements.

したがって、この発明の目的は、前記に鑑み、複数の半導体素子を有する積層型マルチチップ半導体装置において、放熱性能を高め、半導体素子間の電気的な相互干渉を緩和することができる半導体装置およびその製造方法を提供することである。   Therefore, in view of the above, an object of the present invention is to provide a semiconductor device capable of improving heat dissipation performance and alleviating electrical mutual interference between semiconductor elements in a multilayer multichip semiconductor device having a plurality of semiconductor elements. It is to provide a manufacturing method.

前記の目的を達成するためにこの発明の請求項１記載の半導体装置は、外部回路と接続するための外部電極を有する基板と、前記外部電極と反対側の前記基板上に積層して搭載された複数の半導体素子とを備えた積層型マルチチップ半導体装置であって、対向する２つの半導体素子の間に一部が半導体装置の上面に露出する放熱体を配置した。   In order to achieve the above object, a semiconductor device according to claim 1 of the present invention is mounted on a substrate having an external electrode for connection to an external circuit, and stacked on the substrate opposite to the external electrode. In addition, a multi-chip semiconductor device including a plurality of semiconductor elements, and a heat dissipating body, a part of which is exposed on the upper surface of the semiconductor device, is disposed between two facing semiconductor elements.

請求項２記載の半導体装置は、請求項１記載の半導体装置において、前記放熱体と基板上に形成された接続パターンとをワイヤを用いて接続し、前記放熱体が電気的に定電位に接続される。   The semiconductor device according to claim 2 is the semiconductor device according to claim 1, wherein the radiator and the connection pattern formed on the substrate are connected using a wire, and the radiator is electrically connected to a constant potential. Is done.

請求項３記載の半導体装置の製造方法は、複数の半導体素子を熱伝導性接着剤を使用して基板上に積層する積層型マルチチップ半導体装置の製造方法であって、前記複数の半導体素子を積層する際に前記複数の半導体素子の中の２つの半導体素子間に放熱体を熱伝導性接着剤を使用して接続する工程と、前記基板の上面に配置された接続パターンと前記半導体素子の上面に配置された接続パターンをワイヤで接続する工程と、前記基板の上面に配置された接続パターンと前記放熱体の一部をワイヤで接続する工程と、前記基板上面に前記半導体素子と前記ワイヤを覆って封止樹脂を配置する工程と、前記封止樹脂を硬化する工程と、前記基板に外部回路と接続するための外部電極を配置する工程とを含む。   A method for manufacturing a semiconductor device according to claim 3 is a method for manufacturing a stacked multi-chip semiconductor device in which a plurality of semiconductor elements are stacked on a substrate using a thermally conductive adhesive. A step of connecting a heat sink using a thermally conductive adhesive between two semiconductor elements of the plurality of semiconductor elements when stacking, a connection pattern disposed on an upper surface of the substrate, and the semiconductor element Connecting the connection pattern disposed on the upper surface with a wire; connecting the connection pattern disposed on the upper surface of the substrate with a part of the heat dissipating member; and connecting the semiconductor element and the wire to the upper surface of the substrate. A step of disposing a sealing resin over the substrate, a step of curing the sealing resin, and a step of disposing an external electrode for connecting to an external circuit on the substrate.

この発明の請求項１記載の半導体装置によれば、対向する２つの半導体素子の間に一部が半導体装置の上面に露出する放熱体を配置したので、半導体素子に発熱があった際に、放熱体を伝導して外部に伝わることによって、複数の半導体素子を有する積層型マルチチップ半導体装置の放熱性能を高めることができる。   According to the semiconductor device of the first aspect of the present invention, since the heat dissipating body partly exposed on the upper surface of the semiconductor device is disposed between the two facing semiconductor elements, when the semiconductor element generates heat, By conducting the heat radiating body and transmitting it to the outside, the heat radiation performance of the multilayer multichip semiconductor device having a plurality of semiconductor elements can be improved.

請求項２では、放熱体と基板上に形成された接続パターンとをワイヤを用いて接続し、放熱体が電気的に定電位に接続されるので、定電位に接続された放熱体によって、放熱体の両側の半導体素子間の電気的な相互干渉を緩和することができる。   According to the second aspect of the present invention, the radiator and the connection pattern formed on the substrate are connected using wires, and the radiator is electrically connected to a constant potential. It is possible to reduce electrical mutual interference between semiconductor elements on both sides of the body.

この発明の請求項３記載の半導体装置の製造方法によれば、複数の半導体素子を積層する際に複数の半導体素子の中の２つの半導体素子間に放熱体を熱伝導性接着剤を使用して接続する工程と、基板の上面に配置された接続パターンと放熱体の一部をワイヤで接続する工程とを含むので、複数の半導体素子を有する積層型マルチチップ半導体装置の放熱性能を高め、半導体素子間の電気的な相互干渉を緩和することができる。   According to the method of manufacturing a semiconductor device according to claim 3 of the present invention, when laminating a plurality of semiconductor elements, a heat-dissipating body is used between two semiconductor elements of the plurality of semiconductor elements by using a heat conductive adhesive. And connecting the connection pattern disposed on the upper surface of the substrate and a step of connecting a part of the heat dissipating member with a wire, so that the heat dissipation performance of the multilayer multichip semiconductor device having a plurality of semiconductor elements is improved, Electrical mutual interference between semiconductor elements can be reduced.

この発明の第１の実施の形態を図１および図２に基づいて説明する。図１（ａ）は本発明の第１の実施形態の半導体装置の断面図、（ｂ）はその半導体装置の上面から見た透過図である。   A first embodiment of the present invention will be described with reference to FIGS. FIG. 1A is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, and FIG.

図１（ａ）に示すように、外部回路と接続するための外部電極７を有する基板２と、外部電極７と反対側の基板２上に積層して搭載された複数の半導体素子とを備えた従来の構造に加えて、対向する２つの半導体素子１Ａ，１Ｂの間に一部が半導体装置の上面に露出する放熱体３を配置している。この場合、放熱体３と熱伝導性接着剤４Ｂが半導体素子１Ａと１Ｂ間に配置される。更にこの放熱体３は封止樹脂６の外部に露出する面を持った構造となっているが、図１（ｂ）に示すように、半導体素子間の部分と外部へ露出する部分の間の連結部は、ボンディングワイヤ５Ａ，５Ｂ領域を避けるようになっており、ワイヤボンディングを妨げることのない構造になっている。具体的には、放熱体３の半導体素子間の部分は、上方の半導体素子１Ｂより面積が大きい平板状で、その４角部から対角線方向に連結部を立ち上げている。外部へ露出する部分は、連結部と一体に封止樹脂６の上面と面一となるように形成されている。   As shown in FIG. 1A, a substrate 2 having an external electrode 7 for connection to an external circuit and a plurality of semiconductor elements stacked and mounted on the substrate 2 on the opposite side of the external electrode 7 are provided. In addition to the conventional structure described above, the heat dissipating body 3 that is partially exposed on the upper surface of the semiconductor device is disposed between the two facing semiconductor elements 1A and 1B. In this case, the heat radiator 3 and the heat conductive adhesive 4B are disposed between the semiconductor elements 1A and 1B. Further, the heat radiating body 3 has a structure having a surface exposed to the outside of the sealing resin 6, but, as shown in FIG. 1B, between the portion between the semiconductor elements and the portion exposed to the outside. The connecting portion avoids the bonding wires 5A and 5B regions, and has a structure that does not hinder wire bonding. Specifically, the portion between the semiconductor elements of the heat radiating body 3 is a flat plate having a larger area than the upper semiconductor element 1B, and the connecting portion is raised from the four corners in the diagonal direction. The portion exposed to the outside is formed so as to be flush with the upper surface of the sealing resin 6 integrally with the connecting portion.

第１の実施形態によると、半導体素子１Ａ，１Ｂに発熱があった際に、放熱体３を伝導して半導体装置の外部に伝わることによって、半導体素子の放熱性能を向上させることが可能になる。   According to the first embodiment, when heat is generated in the semiconductor elements 1A and 1B, the heat dissipation performance of the semiconductor element can be improved by conducting the heat radiating body 3 and transmitting it to the outside of the semiconductor device. .

次に上記半導体装置の製造方法について説明する。図２は本発明の第１の実施形態の半導体装置の製造方法を示す工程断面図である。   Next, a method for manufacturing the semiconductor device will be described. FIG. 2 is a process sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

まず図２（ａ）に示すように、半導体素子１Ａを半導体基板２に熱伝導性接着剤４Ａで接続する。熱伝導性接着剤４Ａは例えばエポキシ樹脂などを用いる。   First, as shown in FIG. 2A, the semiconductor element 1A is connected to the semiconductor substrate 2 with a heat conductive adhesive 4A. For example, an epoxy resin is used as the heat conductive adhesive 4A.

図２（ｂ）に示すように、前記図２（ａ）の状態のものの上に放熱体３を熱伝導性接着剤４Ｂで接続する。この放熱体３は図２（ｄ）で示すボンディングワイヤ５Ａ，５Ｂ，５Ｃの領域を避けるようになっており、上記のようにワイヤボンディングを妨げることのない構造になっている。   As shown in FIG.2 (b), the heat radiator 3 is connected with the heat conductive adhesive 4B on the thing of the said state of Fig.2 (a). The heat dissipating body 3 avoids the bonding wires 5A, 5B, and 5C shown in FIG. 2D, and has a structure that does not hinder wire bonding as described above.

図２（ｃ）に示すように、前記図２（ｂ）の状態のものの上に半導体素子１Ｂを熱伝導性接着剤４Ｃで接続する。   As shown in FIG. 2 (c), the semiconductor element 1B is connected to the state shown in FIG. 2 (b) with a heat conductive adhesive 4C.

図２（ｄ）に示すように、前記図２（ｃ）の状態のものの半導体素子１Ａ，１Ｂの図示しない接続パターンと半導体基板２の図示しない接続パターンをボンディングワイヤ５Ａ，５Ｂで接続する。ボンディングワイヤ５Ａ，５Ｂは例えば金線を用いる。   As shown in FIG. 2D, the connection pattern (not shown) of the semiconductor elements 1A and 1B in the state of FIG. 2C and the connection pattern (not shown) of the semiconductor substrate 2 are connected by bonding wires 5A and 5B. For example, gold wires are used as the bonding wires 5A and 5B.

図２（ｅ）に示すように、前記図２（ｄ）の状態のものを金型８の中に配置する。この際、放熱体３が樹脂封止後も上部が露出するように金型８は製造されている。配置後に封止樹脂６を封止して図２（ｅ）に至る。封止樹脂６は例えば熱硬化性樹脂である。   As shown in FIG. 2 (e), the one in the state of FIG. 2 (d) is placed in the mold 8. At this time, the mold 8 is manufactured so that the upper portion of the radiator 3 is exposed even after resin sealing. After the placement, the sealing resin 6 is sealed to reach FIG. The sealing resin 6 is, for example, a thermosetting resin.

最後に図２（ｆ）に示すように、前記図２（ｅ）の状態の半導体基板２の下面の図示しない接続パターンに外部電極７を搭載する。   Finally, as shown in FIG. 2F, the external electrode 7 is mounted on a connection pattern (not shown) on the lower surface of the semiconductor substrate 2 in the state shown in FIG.

半導体素子１Ａ，１Ｂの素材には主にシリコンが用いられる。半導体基板２はガラスエポキシ製のものなどが用いられる。放熱体３は例えば銅や鉄系の金属が用いられる。熱伝導性接着剤４Ａ，４Ｂ，４Ｃとしては例えばエポキシ樹脂、アクリル系樹脂、フェノール系樹脂、尿素系樹脂、イミド系樹脂、アミド系樹脂などが用いられる。ボンディングワイヤ５Ａ，５Ｂとしては金線が用いられることが多い。封止樹脂６としては例えばエポキシ樹脂、アクリル系樹脂、フェノール系樹脂、尿素系樹脂、イミド系樹脂、アミド系樹脂などが用いられる。外部電極７としては半田バンプなどの形態が取られ、半田バンプの材料としては低弾性である共晶半田が用いられることが多い。   Silicon is mainly used as a material for the semiconductor elements 1A and 1B. The semiconductor substrate 2 is made of glass epoxy. For example, copper or iron-based metal is used for the radiator 3. As the heat conductive adhesives 4A, 4B, 4C, for example, epoxy resins, acrylic resins, phenol resins, urea resins, imide resins, amide resins, and the like are used. Gold wires are often used as the bonding wires 5A and 5B. As the sealing resin 6, for example, an epoxy resin, an acrylic resin, a phenol resin, a urea resin, an imide resin, an amide resin, or the like is used. The external electrode 7 takes a form such as a solder bump, and eutectic solder having low elasticity is often used as the material of the solder bump.

この発明の第２の実施の形態を図３および図４に基づいて説明する。図３（ａ）は本発明の第２の実施形態の半導体装置の断面図、（ｂ）はその半導体装置の上面から見た透過図である。   A second embodiment of the present invention will be described with reference to FIGS. FIG. 3A is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention, and FIG. 3B is a transparent view seen from the top surface of the semiconductor device.

図３（ａ）に示すように、第１の実施形態と同様に放熱体３と熱伝導性接着剤４Ｂが半導体素子１Ａと１Ｂ間に配置される。また、この放熱体３はボンディングワイヤ５Ｃによって半導体基板２上の接続パターンに接続され、この接続パターンは半導体基板内の配線を介して定電位に接続される。更にこの放熱体３は封止樹脂６の外部に露出する面を持った構造となっているが、図３（ｂ）に示すように、半導体素子間の部分と外部へ露出する部分の間の連結部は、ボンディングワイヤ５Ａ，５Ｂ，５Ｃ領域を避けるようになっており、ワイヤボンディングを妨げることのない構造になっている。   As shown in FIG. 3A, the radiator 3 and the thermally conductive adhesive 4B are disposed between the semiconductor elements 1A and 1B, as in the first embodiment. The radiator 3 is connected to a connection pattern on the semiconductor substrate 2 by a bonding wire 5C, and the connection pattern is connected to a constant potential via a wiring in the semiconductor substrate. Further, the heat radiating body 3 has a structure having a surface exposed to the outside of the sealing resin 6, but as shown in FIG. 3B, between the portion between the semiconductor elements and the portion exposed to the outside. The connecting portion avoids the bonding wires 5A, 5B, and 5C regions, and has a structure that does not hinder wire bonding.

第２の実施形態によると、半導体素子１Ａ，１Ｂに発熱があった際に、放熱体３を伝導して半導体装置の外部に伝わることによって、半導体素子の放熱性能を向上させることが可能になる。また定電位に接続された放熱体３によって、放熱体３の両側の半導体素子１Ａ，１Ｂ間の電気的な相互干渉を緩和することが可能になる。   According to the second embodiment, when heat is generated in the semiconductor elements 1A and 1B, the heat dissipation performance of the semiconductor element can be improved by conducting the heat radiating body 3 and transmitting it to the outside of the semiconductor device. . Further, the heat radiating body 3 connected to a constant potential can alleviate electrical mutual interference between the semiconductor elements 1A and 1B on both sides of the heat radiating body 3.

次に上記半導体装置の製造方法について説明する。図４は本発明の第２の実施形態の半導体装置の製造方法を示す工程断面図である。   Next, a method for manufacturing the semiconductor device will be described. FIG. 4 is a process sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

まず図４（ａ）に示すように、半導体素子１Ａを半導体基板２に熱伝導性接着剤４Ａで接続する。熱伝導性接着剤４Ａは例えばエポキシ樹脂などを用いる。   First, as shown in FIG. 4A, the semiconductor element 1A is connected to the semiconductor substrate 2 with a heat conductive adhesive 4A. For example, an epoxy resin is used as the heat conductive adhesive 4A.

図４（ｂ）に示すように、前記図４（ａ）の状態のものの上に放熱体３を熱伝導性接着剤４Ｂで接続する。この放熱体３は図４（ｄ）で示すボンディングワイヤ５Ａ，５Ｂ，５Ｃの領域を避けるようになっており、上記のようにワイヤボンディングを妨げることのない構造になっている。   As shown in FIG.4 (b), the heat radiator 3 is connected on the thing of the state of Fig.4 (a) with the heat conductive adhesive 4B. The heat dissipating body 3 avoids the regions of the bonding wires 5A, 5B, and 5C shown in FIG. 4D, and has a structure that does not hinder wire bonding as described above.

図４（ｃ）に示すように、前記図４（ｂ）の状態のものの上に半導体素子１Ｂを熱伝導性接着剤４Ｂで接続する。   As shown in FIG. 4 (c), the semiconductor element 1B is connected to the state shown in FIG. 4 (b) with a heat conductive adhesive 4B.

図４（ｄ）に示すように、前記図４（ｃ）の状態のものの半導体素子１Ａ，１Ｂの図示しない接続パターンと半導体基板２の図示しない接続パターンをボンディングワイヤ５Ａ，５Ｂで接続し、更に放熱体３上の一部分と半導体基板２の図示しない接続パターンをボンディングワイヤ５Ｃで接続する。この際ボンディングワイヤ５Ｃが接続される半導体基板２上の接続パターンは半導体基板２内部の配線と下面の外部電極７を通して定電位に接続されるように設計されることとする。ボンディングワイヤ５Ａ，５Ｂ，５Ｃは例えば金線を用いる。   As shown in FIG. 4D, the connection pattern (not shown) of the semiconductor elements 1A and 1B in the state of FIG. 4C and the connection pattern (not shown) of the semiconductor substrate 2 are connected by bonding wires 5A and 5B. A part of the radiator 3 and a connection pattern (not shown) of the semiconductor substrate 2 are connected by a bonding wire 5C. At this time, the connection pattern on the semiconductor substrate 2 to which the bonding wire 5C is connected is designed to be connected to a constant potential through the wiring inside the semiconductor substrate 2 and the external electrode 7 on the lower surface. For example, gold wires are used as the bonding wires 5A, 5B, and 5C.

図４（ｅ）に示すように、前記図４（ｄ）の状態のものを金型８の中に配置する。この際、放熱体３が樹脂封止後も上部が露出するように金型８は製造されている。配置後に封止樹脂６を封止して図４（ｅ）に至る。封止樹脂６は例えば熱硬化性樹脂である。   As shown in FIG. 4 (e), the one in the state of FIG. 4 (d) is placed in the mold 8. At this time, the mold 8 is manufactured so that the upper portion of the radiator 3 is exposed even after resin sealing. After the placement, the sealing resin 6 is sealed to reach FIG. The sealing resin 6 is, for example, a thermosetting resin.

最後に図４（ｆ）に示すように、前記図４（ｅ）の状態の半導体基板２の下面の図示しない接続パターンに外部電極７を搭載する。   Finally, as shown in FIG. 4F, the external electrode 7 is mounted on a connection pattern (not shown) on the lower surface of the semiconductor substrate 2 in the state of FIG.

半導体素子１Ａ，１Ｂの素材には主にシリコンが用いられる。半導体基板２はガラスエポキシ製のものなどが用いられる。放熱体３は例えば銅や鉄系の金属が用いられる。熱伝導性接着剤４Ａ，４Ｂ，４Ｃとしては例えばエポキシ樹脂、アクリル系樹脂、フェノール系樹脂、尿素系樹脂、イミド系樹脂、アミド系樹脂などが用いられる。ボンディングワイヤ５Ａ，５Ｂとしては金線が用いられることが多い。封止樹脂６としては例えばエポキシ樹脂、アクリル系樹脂、フェノール系樹脂、尿素系樹脂、イミド系樹脂、アミド系樹脂などが用いられる。外部電極７としては半田バンプなどの形態が取られ、半田バンプの材料としては低弾性である共晶半田が用いられることが多い。   Silicon is mainly used as a material for the semiconductor elements 1A and 1B. The semiconductor substrate 2 is made of glass epoxy. For example, copper or iron-based metal is used for the radiator 3. As the heat conductive adhesives 4A, 4B, 4C, for example, epoxy resins, acrylic resins, phenol resins, urea resins, imide resins, amide resins, and the like are used. Gold wires are often used as the bonding wires 5A and 5B. As the sealing resin 6, for example, an epoxy resin, an acrylic resin, a phenol resin, a urea resin, an imide resin, an amide resin, or the like is used. The external electrode 7 takes a form such as a solder bump, and eutectic solder having low elasticity is often used as the material of the solder bump.

本発明にかかる半導体装置およびその製造方法は、配線基板上に積層して搭載された複数の半導体素子を有する積層型マルチチップ半導体装置の放熱性能を高め、半導体素子間の電気的な相互干渉を緩和させる効果を有する。   A semiconductor device and a manufacturing method thereof according to the present invention improve the heat dissipation performance of a stacked multi-chip semiconductor device having a plurality of semiconductor elements stacked and mounted on a wiring board, and prevent electrical mutual interference between semiconductor elements. Has a relaxing effect.

従って、配線基板上に積層して搭載された複数の半導体素子を有する積層型マルチチップ半導体装置であるＰＢＧＡ、ＰＧＡ、ＣＳＰ等を適用するコンピュータやネットワークルータ、ＰＤＰ、デジタルＴＶ、ハイビジョンＴＶ、携帯電話、あるいは、特に非常な負荷の加わる車載用半導体装置などにおいて有用である。   Accordingly, computers, network routers, PDPs, digital TVs, high-definition TVs, mobile phones to which PBGA, PGA, CSP, etc., which are stacked multichip semiconductor devices having a plurality of semiconductor elements stacked and mounted on a wiring board, are applied. Or, it is particularly useful in an in-vehicle semiconductor device to which a very heavy load is applied.

（ａ）は本発明の第１の実施形態の半導体装置の断面図、（ｂ）はその半導体装置の上面から見た透過図である。(A) is sectional drawing of the semiconductor device of the 1st Embodiment of this invention, (b) is the permeation | transmission figure seen from the upper surface of the semiconductor device. 本発明の第１の実施形態の半導体装置の製造方法を示す工程断面図である。It is process sectional drawing which shows the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. （ａ）は本発明の第２の実施形態の半導体装置の断面図、（ｂ）はその半導体装置の上面から見た透過図である。(A) is sectional drawing of the semiconductor device of the 2nd Embodiment of this invention, (b) is the permeation | transmission figure seen from the upper surface of the semiconductor device. 本発明の第２の実施形態の半導体装置の製造方法を示す工程断面図である。It is process sectional drawing which shows the manufacturing method of the semiconductor device of the 2nd Embodiment of this invention. （ａ）は従来例の半導体装置の断面図、（ｂ）はその半導体装置の上面から見た透過図である。(A) is sectional drawing of the semiconductor device of a prior art example, (b) is the permeation | transmission figure seen from the upper surface of the semiconductor device. 従来例の半導体装置の製造方法を示す工程断面図である。It is process sectional drawing which shows the manufacturing method of the semiconductor device of a prior art example.

符号の説明Explanation of symbols

１Ａ,１Ｂ 半導体素子
２ 半導体基板
３ 放熱体
４Ａ,４Ｂ,４Ｃ 熱伝導性接着剤
５Ａ,５Ｂ,５Ｃ ボンディングワイヤ
６ 封止樹脂
７ 外部電極
８ 金型 1A, 1B Semiconductor element 2 Semiconductor substrate 3 Heat dissipating body 4A, 4B, 4C Thermally conductive adhesive 5A, 5B, 5C Bonding wire 6 Sealing resin 7 External electrode 8 Mold

Claims (3)

外部回路と接続するための外部電極を有する基板と、前記外部電極と反対側の前記基板上に積層して搭載された複数の半導体素子とを備えた積層型マルチチップ半導体装置であって、
対向する２つの半導体素子の間に一部が半導体装置の上面に露出する放熱体を配置したことを特徴とする半導体装置。 A multilayer multichip semiconductor device comprising a substrate having an external electrode for connecting to an external circuit, and a plurality of semiconductor elements stacked and mounted on the substrate opposite to the external electrode,
A semiconductor device, wherein a heat radiating body, a part of which is exposed on an upper surface of a semiconductor device, is disposed between two opposing semiconductor elements. 前記放熱体と基板上に形成された接続パターンとをワイヤを用いて接続し、前記放熱体が電気的に定電位に接続される請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the heat radiating body and a connection pattern formed on the substrate are connected using a wire, and the heat radiating body is electrically connected to a constant potential. 複数の半導体素子を熱伝導性接着剤を使用して基板上に積層する積層型マルチチップ半導体装置の製造方法であって、前記複数の半導体素子を積層する際に前記複数の半導体素子の中の２つの半導体素子間に放熱体を熱伝導性接着剤を使用して接続する工程と、前記基板の上面に配置された接続パターンと前記半導体素子の上面に配置された接続パターンをワイヤで接続する工程と、前記基板の上面に配置された接続パターンと前記放熱体の一部をワイヤで接続する工程と、前記基板上面に前記半導体素子と前記ワイヤを覆って封止樹脂を配置する工程と、前記封止樹脂を硬化する工程と、前記基板に外部回路と接続するための外部電極を配置する工程とを含む半導体装置の製造方法。   A method for manufacturing a multi-chip semiconductor device in which a plurality of semiconductor elements are stacked on a substrate using a thermally conductive adhesive, wherein the plurality of semiconductor elements are stacked when the plurality of semiconductor elements are stacked. A step of connecting a heat radiator between two semiconductor elements using a thermally conductive adhesive, and a connection pattern arranged on the upper surface of the substrate and a connection pattern arranged on the upper surface of the semiconductor element are connected by wires. A step of connecting a connection pattern disposed on the upper surface of the substrate and a part of the radiator with a wire, a step of covering the semiconductor element and the wire on the substrate upper surface and disposing a sealing resin; A method for manufacturing a semiconductor device, comprising: a step of curing the sealing resin; and a step of disposing an external electrode for connecting to an external circuit on the substrate.
JP2004237540A 2004-08-17 2004-08-17 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4237116B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4768012B2 (en) * 2005-04-18 2011-09-07 フリースケール セミコンダクター インコーポレイテッド Layered structure of integrated circuits on other integrated circuits
WO2014106879A1 (en) * 2013-01-07 2014-07-10 パナソニック株式会社 Semiconductor device provided with radiator member
US9177942B2 (en) 2013-09-11 2015-11-03 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
CN106713151A (en) * 2016-11-25 2017-05-24 东莞大联社电子散热材料有限公司 Novel router heat dissipation module

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4768012B2 (en) * 2005-04-18 2011-09-07 フリースケール セミコンダクター インコーポレイテッド Layered structure of integrated circuits on other integrated circuits
WO2014106879A1 (en) * 2013-01-07 2014-07-10 パナソニック株式会社 Semiconductor device provided with radiator member
US9437517B2 (en) 2013-01-07 2016-09-06 Panasonic Corporation Semiconductor apparatus including a heat dissipating member
JPWO2014106879A1 (en) * 2013-01-07 2017-01-19 パナソニック株式会社 Semiconductor device provided with heat dissipation member
US9177942B2 (en) 2013-09-11 2015-11-03 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
CN106713151A (en) * 2016-11-25 2017-05-24 东莞大联社电子散热材料有限公司 Novel router heat dissipation module
CN106713151B (en) * 2016-11-25 2019-12-31 东莞大联社电子散热材料有限公司 Novel heat dissipation module of router

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