JP2006059751A - Charging/discharging circuit and charging/discharging method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charging/discharging circuit and a charging/discharging method for charging/discharging a capacitor capable of reducing overshoot. <P>SOLUTION: This charging/discharging circuit is provided with a first capacitor (C1), a second capacitor (C2), a switching means (74) provided between the first capacitor (C1) and the second capacitor (C2) and switching connection between the first capacitor (C1) and the second capacitor (C2), voltage detection means (76, R12, R13) detecting voltage between both ends of the switching means (74), and control means (71, 72, 73, 75, R11, C11) controlling charging/discharging of the first capacitor and controlling switching the switching means (74) according to the detection results of the voltage detection means (76, R12, R13) when charging the first capacitor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a charging / discharging circuit and a charging / discharging method, and more particularly, to a charging / discharging circuit and a charging / discharging method for charging or discharging a charge in a capacitor.

  Conventionally, in order to control delay and timing, a pulse signal or the like is generated by charging / discharging a capacitance and detecting the charging voltage.

  However, when a single capacitor is charged and discharged, there is a problem that a charging voltage overshoot occurs when the capacitor is charged.

  This invention is made | formed in view of said point, and aims at providing the charging / discharging circuit and charging / discharging method which can reduce an overshoot.

  The present invention is provided between the first capacitor (C1), the second capacitor (C2), the first capacitor (C1) and the second capacitor (C2), and the first capacitor (C1). ) And the second capacitor (C2), switching means (74) for switching the connection, voltage detection means (76, R12, R13) for detecting the voltage across the switching means (74), and the first capacitor Control means (71, 72, 73) for switching control of the switching means (74) according to the detection result of the voltage detection means (76, R12, R13) during charging of the first capacitor. , 75, R11, C11).

  The control means (71, 72, 73, 75, R11, C11) switches the switch means (74) according to the detection result of the voltage detection means (76, R12, R13) and the polarity of the voltage across the switch means (74). Switching.

  The control means (71, 72, 73, 75, R11, C11) turns on the switch means (74) to charge both the first capacitor (C1) and the second capacitor (C2) to substantially the same potential. Then, the switch means (74) is turned off, the first capacitor (C1) is discharged, the first capacitor (C1) is discharged, and then the charging of the first capacitor (C1) is started. When the detection result of the detection means (76, R12, R13) shows that the charging potential of the first capacitor (C1) becomes larger than the charging potential of the second capacitor (C2), the switch means (74) is turned on. It is characterized by.

  In addition, the said reference code is a reference to the last, and a claim is not limited by this.

  According to the present invention, after the switch means is turned on and both the first capacitor and the second capacitor are charged to substantially the same potential, the switch means is turned off, and the first capacitor is discharged. After discharging the capacitor, charging of the first capacitor is started, and when the charging potential of the first capacitor becomes higher than the charging potential of the second capacitor, the switch means is turned on, thereby When the capacitor is charged, the second capacitor is connected in parallel near the charging voltage, and the capacitance increases, so that the overshoot can be reduced.

  In this embodiment, an example in which the charge / discharge circuit and the charge / discharge method of the present invention are applied to a cold cathode fluorescent tube lighting system will be described. First, a cold cathode fluorescent tube lighting system will be described.

〔System configuration〕

  FIG. 1 shows a block diagram of an embodiment of the present invention.

  The cold cathode fluorescent tube lighting system 1 of the present embodiment is a system used as a backlight of a liquid crystal monitor, for example, and includes a cold cathode fluorescent tube portion 11, a resonance circuit portion 12, a driving IC (integrated circuit) 13, and a protection IC. (Integrated circuit) 14, a peak hold circuit 15, a reference voltage source 16, and capacitors C1 and C2.

  The cold cathode fluorescent tube section 11 has a configuration in which cold cathode fluorescent tube pairs 21 and 22 are arranged in parallel. The cold cathode fluorescent tube pair 21 has a configuration in which two cold cathode fluorescent tubes 31 and 32 are arranged in parallel, and the cold cathode fluorescent tube pair 22 has a configuration in which two cold cathode fluorescent tubes 41 and 42 are arranged in parallel. Has been.

  The resonance circuit 12 is connected to one end of each cold cathode fluorescent tube 31, 32, 41, 42. The other ends of the cold cathode fluorescent tubes 31 and 32 are grounded via detection resistors Rs1 and Rs2, and the other ends of the cold cathode fluorescent tubes 41 and 42 are grounded via detection resistors Rs3 and Rs4.

  The cold cathode fluorescent tubes 31, 32, 41, and 42 constitute a resonance circuit together with the resonance circuit 12, and when a voltage of a predetermined frequency, for example, 50 kHz is applied to both ends thereof, a drive current flows and is lit. When a voltage of lower or higher frequency, for example, 100 kHz is applied, the light is turned off.

  The resonance circuit 12 is supplied with a drive signal having a predetermined frequency from the drive IC 13. The resonance circuit 12 is composed of a capacitor, a transformer, and the like, and constitutes a resonance circuit by their capacitance, inductance, and the like. The resonance circuit 12 resonates with a drive signal supplied from the drive IC 13 and is driven to the cold cathode fluorescent tube unit 11. Power is being supplied and applied.

  [Drive IC13]

  FIG. 2 is a block diagram of the driving IC 13.

  The drive IC 13 includes a voltage control oscillation circuit 51, a start circuit 52, an error amplifier 53, and a voltage control circuit 54.

  The control circuit Tcnt of the voltage controlled oscillation circuit 51 is connected to the starting circuit 52, the error amplifier 53, the voltage control circuit 54, and the terminal T4. The voltage controlled oscillation circuit 51 outputs an oscillation output having a frequency corresponding to the voltage applied to the control terminal Tcnt from the output terminal Tosc.

  The output terminal Tosc of the voltage controlled oscillation circuit 51 is connected to the output terminal T 1 of the drive IC 13, and the oscillation output of the voltage controlled oscillation circuit 51 is output from the output terminal T 1 toward the resonance circuit 12.

  The starting circuit 52 controls the control voltage of the voltage controlled oscillation circuit 51 so that the cold cathode fluorescent tubes 31, 32, 41, 42 are turned on quickly when the power is turned on.

  The error amplifier 53 has an inverting input terminal connected to the terminal T2, and a non-inverting input terminal connected to the terminal T3. An average value signal is supplied from the protection IC 14 to the terminal T2, and a reference voltage is supplied from the reference voltage source to the terminal T3. The error amplifier 53 outputs a voltage corresponding to the difference between the average value signal and the reference voltage. The output of the error amplifier 53 is supplied to the control terminal Tcnt of the voltage controlled oscillation circuit 51 and is also supplied to the terminal T4.

  The voltage control circuit 54 is connected to a terminal T5. The terminal T5 is connected to the terminal T14 of the protection IC 14, and a stop signal is supplied from the protection IC 14. The voltage control circuit 54 fixes the control terminal Tcnt of the voltage controlled oscillation circuit 51 to a high level by a stop signal from the protection IC 14. At this time, when the output of the voltage control circuit 54 is fixed to the high level, the output is maintained at the high level until the reset is performed due to power-off or the like.

  The terminal T4 is connected to the terminal T15 of the protection IC 14. A capacitor C1 is connected between the connection point between the terminal T4 and the terminal T15 and the ground. In the voltage controlled oscillation circuit 51, the control voltage applied to the control terminal Tcnt is controlled by the charging voltage of the capacitor C1, and the oscillation frequency is controlled.

  [Protection IC 14]

  As shown in FIG. 1, the protection IC 14 includes a PWM (pulse width modulation) control unit 61 and a protection circuit unit 62. The PWM control unit 61 is a circuit for performing PWM control on the oscillation state of the voltage controlled oscillation circuit 51 included in the drive IC 13.

  [PWM controller 61]

  FIG. 3 is a block diagram of the PWM control unit 61.

  The PWM controller 61 includes a triangular wave generation circuit 71, a comparator 72, a gate circuit 73, an analog switch 74, a discharge switch 75, a comparator 76, resistors R11, R12, R13, and a capacitor C11.

  The terminal T17 is supplied with a set luminance signal for determining the luminance from the outside. The set luminance signal supplied to the terminal T17 is supplied to the inverting input terminal of the comparator 72. A triangular wave is supplied from the triangular wave generation circuit 71 to the non-inverting input terminal of the comparator 72. The comparator 72 compares the luminance signal with the triangular wave, and sets the output to a high level when the triangular wave is larger than the luminance signal, and sets the output to a low level when the triangular wave is smaller than the luminance signal. The comparator 72 generates a pulse having a pulse width corresponding to the frequency of the triangular wave and corresponding to the luminance signal.

  The output pulse of the comparator 72 is supplied to the switch 75 and a gate circuit 73 through a delay circuit composed of a resistor R11 and a capacitor C11. The switch 75 is connected between the terminal T15 and the ground, and is switched by a pulse obtained by delaying the output pulse of the comparator 72 by a time determined by the resistor R11 and the capacitor C11. The switch 75 is turned off when the pulse is at a low level to charge the capacitor C1, and is turned on when the pulse is at a high level to discharge the capacitor C1.

  The gate circuit 73 inverts and outputs the output pulse of the comparator 72. Further, the output of the comparator 76 is supplied to the gate circuit 73. The gate circuit 73 outputs an AND logic between the inverted output of the comparator 72 and the output of the comparator 76. The output of the gate circuit 73 is supplied to the analog switch 74.

  The analog switch 74 includes a p-channel MOS field effect transistor M 1, an n-channel MOS field effect transistor M 2, and an inverting circuit 81. The transistor M1 and the transistor M2 constitute a transfer gate having a so-called CMOS (complementary MOS) structure. The output of the AND gate 73 is directly supplied to the gate of the transistor M2, and the output of the AND gate 73 is supplied to the gate of the transistor M1 through the inverting circuit 81.

  The analog switch 74 is connected between the terminals T15 and T16, and is switched according to the output of the gate circuit 73. The analog switch 74 is turned on when the output of the gate circuit 73 is at a high level, short-circuits the terminal T15 and the terminal T16, is turned off when the output of the gate circuit 73 is at a low level, and connects the terminal T15 and the terminal T16. Open.

  A terminal T16 is connected to the inverting input terminal of the comparator 76, and a connection point between the resistor R12 and the resistor R13 is connected to the non-inverting input terminal. The resistor R12 has one end connected to the non-inverting input terminal of the comparator 76 and the other end connected to the terminal T15. One end of the resistor R13 is connected to a connection point between the non-inverting input terminal of the comparator 76 and one end of the resistor R12, and the power supply voltage Vdd is applied to the other end.

  The comparator 76 compares the potential at the connection point between the resistor R12 and the resistor R13 with the potential at the terminal T16. If the potential at the connection point between the resistor R12 and the resistor R13 is greater than the potential at the terminal T16, the output is set to the high level. If the potential at the connection point between the resistors R12 and R13 is smaller than the potential at the terminal T16, the output is set to low level.

[Operation of PWM control unit 61]
First, when the output pulse of the comparator 72 becomes high level, the switch 74 is turned off and the terminals T15 and T16 are opened. As a result, the capacitor C1 and the capacitor C2 are disconnected.

  Next, the switch 75 is delayed by the resistor R11 and the capacitor C11 and becomes high level. As a result, the switch 75 is turned on after a slight delay after the output of the comparator 72 becomes high level. When the switch 75 is turned on, the capacitor C1 connected to the terminal T15 is discharged.

  When the capacitor C1 is discharged, the potential at the terminal T15 decreases. Next, when the triangular wave output from the triangular wave generating circuit 71 decreases and the output of the comparator 72 becomes low level, the switch 75 is turned off with a slight delay by the resistors R11 and C11. When the switch 75 is turned off, the capacitor C1 is charged by the potential of the terminal T4 of the drive IC 13.

  When the capacitor C1 is charged, the potential at the terminal T15 rises. As the potential at the terminal T15 increases, the potential at the non-inverting input terminal of the comparator 76 increases.

  When the potential of the non-inverting input terminal of the comparator 76 rises and rises above the potential of the terminal T16, that is, the charging voltage of the capacitor C2, the output of the comparator 76 becomes high level. When the output of the comparator 76 becomes high level, the output of the gate circuit 73 becomes high level and the analog switch 74 is turned on. When the analog switch 74 is turned on, the capacitor C1 and the capacitor C2 are connected.

  When the charging voltage of the capacitor C1 reaches a desired voltage V with respect to the charging voltage of the capacitor C2, the capacitor C1 and the capacitor C2 are connected, and overshooting during charging of the capacitor C1 can be prevented.

  FIG. 4 is a diagram illustrating a change in the charging voltage of the capacitor C1.

  When the capacitor C1 is charged, at time t1, the analog switch 74 is turned on in accordance with the voltage across the analog switch 74 and connected to the capacitors C1 and C2, so that the charging voltage waveform is in the vicinity of the charging voltage as shown in FIG. It becomes possible to relax. For this reason, it can suppress that overshoot generate | occur | produces in the electric potential of terminal T4. Therefore, the oscillation output of the voltage controlled oscillation circuit 51 whose oscillation frequency is controlled by the potential of the terminal T4 can be stabilized. Further, in this embodiment, the potential at both ends of the analog switch 74 is directly compared by the comparator 76, so that the timing for turning on the analog switch 74 can be set according to the charging potential of the capacitors C1 and C2.

  The PWM controller 61 of this embodiment directly compares the voltages at both ends of the analog switch 74 by the comparator 76, but compares the voltages at both ends of the analog switch 74 by the comparators, and outputs the logical operation of the outputs of the comparators. Thus, the analog switch 74 may be controlled.

  FIG. 5 shows a block configuration diagram of a modified example of the PWM control unit 61. In the figure, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

  The PWM control unit 161 of this modification is different from the configuration of the detection unit 176 in FIG. The detection unit 176 according to the present modification includes comparators 181 and 182, reference voltage sources 183 and 184, and an AND gate 185. In the comparator 181, the terminal T15 is connected to the non-inverting input terminal, and the reference voltage generated by the reference voltage source 183 is applied to the inverting input. The comparator 181 sets the output to a high level if the potential at the terminal T15 is higher than the reference voltage generated by the reference voltage source 183, and outputs the output if the potential at the terminal T15 is lower than the reference voltage generated by the reference voltage source 183. Set to low level. The output of the comparator 181 is supplied to an AND gate 185.

  In the comparator 182, the output of the terminal T16 is supplied to the non-inverting input terminal, and the reference voltage generated by the reference voltage source 184 is supplied to the inverting input. The comparator 182 sets the output to a high level if the potential at the terminal T16 is greater than the reference voltage generated by the reference voltage source 184, and outputs the output if the potential at the terminal T16 is less than the reference voltage generated by the reference voltage source 184. Set to low level. The output of the comparator 182 is supplied to an AND gate 185.

  The AND gate 185 outputs an AND logic between the output of the comparator 181 and the output of the comparator 182. The output of the AND gate 185 is supplied to the AND gate 73.

  According to this modification, when both the potential of the terminal T15 and the potential of the terminal T16, that is, the potentials at both ends of the analog switch 74 are larger than the predetermined potential, the output of the AND gate 73 becomes high level and the analog switch 74 is turned on. It becomes possible.

  Next, when the triangular wave of the triangular wave generation circuit 71 becomes larger than the set luminance signal and the output of the comparator 72 becomes high level, the output of the gate circuit 73 becomes low level and the analog switch 74 is turned off. When the analog switch 74 is turned off, the potential of the terminal T4 of the driving IC 13 is held in the capacitor C2. Note that after a short time has elapsed after the analog switch 74 is turned off, the switch 75 is turned on and the capacitor C1 is discharged. At this time, since the analog switch 74 is turned off, the potential of the terminal T4 is held in the capacitor C2.

  As described above, the potential of the terminal T4 of the driving IC 13 can be controlled in a pulse shape in accordance with the output pulse of the comparator 72.

  The drive IC 13 can intermittently change the oscillation frequency of the voltage-controlled oscillation circuit 51 between about 50 kHz and about 100 kHz by driving the potential of the terminal T4 in a pulse shape. When the output oscillation frequency of the voltage controlled oscillation circuit 51 reaches 50 kHz, the resonance circuit 12 resonates and the cold cathode fluorescent tubes 31, 32, 41, and 42 are lit. When the output oscillation frequency of the voltage controlled oscillation circuit 51 reaches 100 kHz, the supply of power from the resonance circuit 12 to the cold cathode fluorescent tubes 31, 32, 41, 42 is stopped, and the cold cathode fluorescent tubes 31, 32, 41, 42, 42 is turned off.

  As described above, power is intermittently supplied to the cold cathode fluorescent tubes 31, 32, 41, and 42, and the luminance is kept constant.

  Here, the comparator 76 used in the PWM control unit 61 will be described.

[Comparator 76]
The comparator 76 compares the potential at the connection point between the resistor R12 and the resistor R13 with the potential at the terminal T16. If the potential at the connection point between the resistor R12 and the resistor R13 is greater than the potential at the terminal T16, the output is set to the high level. If the potential at the connection point between the resistors R12 and R13 is smaller than the potential at the terminal T16, the output is set to low level. The comparator 76 is provided with hysteresis and offset, and the comparator of the present invention is applied as the comparator 76.

  Here, the comparator 76 will be described in detail.

  FIG. 6 shows a circuit configuration diagram of the comparator 76.

  The comparator 76 compares the first current corresponding to the first input signal with the second current corresponding to the second input signal, and sets the output signal to a high level or a low level according to the magnitude relationship. When the output signal of the comparison circuit unit 121 and the comparison circuit unit 121 is at one level, the first current corresponding to the first input signal is controlled, and when the output signal of the comparison circuit 121 is at the other level The input control circuit 122 controls the second current according to the second input signal and gives hysteresis characteristics to the input / output signal, and the bias power sources 123 and 124.

[Comparison circuit unit 121]
The comparison circuit unit 121 includes a comparison circuit including p-channel MOS field effect transistors M31 and M32 and n-channel MOS field effect transistors M33 to M36, a p-channel MOS field effect transistor M37, and an n-channel MOS field effect transistor M38. And an output circuit composed of

  The transistors M31 and M32 constitute a current mirror circuit, and a current corresponding to the current flowing through the transistor M31 flows through the transistor M32.

  A bias voltage Vbias2 is applied from the bias power supply 124 to the gate of the transistor M33. The transistor M33 draws a current corresponding to the bias voltage Vbias2 from the drain of the transistor M31. A bias voltage Vbias2 is applied from the bias power supply 124 to the gate of the transistor M34. The transistor M34 draws a current corresponding to the bias voltage Vbias2 from the drain of the transistor M32.

  A bias voltage Vbias1 is applied from the bias power supply 123 to the gate of the transistor M35. The transistor M35 draws a current corresponding to the bias voltage Vbias1 from the source of the transistor M33 and releases it to the ground. A bias voltage Vbias1 is applied from the bias power supply 123 to the gate of the transistor M36. The transistor M36 draws a current corresponding to the bias voltage Vbias1 from the source of the transistor M34 and releases it to the ground.

  A first current is supplied from the input control circuit 122 to a connection point between the transistors M33 and M35, and a second current is supplied from the input control circuit 122 to a connection point between the transistors M34 and M36. .

  When the first current is larger than the second current, the comparison circuit unit 121 reduces the current draw from the drain and gate of the transistor M31 and the gate of the transistor M32 and draws the current from the drain of the transistor M34. Increases, the gate voltage of the transistor M37 decreases. As a result, the transistor M37 is turned on and the output becomes a high level.

  In addition, when the second current is larger than the first current, the comparison circuit unit 121 increases the amount of current drawn from the drain and gate of the transistor M31 and the gate of the transistor M32, and the current from the drain of the transistor M34. Is reduced, the gate voltage of the transistor M37 increases. As a result, the transistor M37 is turned off and the output becomes a low level.

[Input control circuit 122]
The input control circuit 122 includes a current source 131, a first input control circuit 132, a second input control circuit 133, a first input transistor M41, and a second input transistor M42.

  A power supply voltage Vdd is applied to the current source 131, and a drive current is generated from the power supply voltage Vdd and output. The current generated by the current source 131 is supplied to the source of the first input transistor M41 and the source of the second input transistor M42.

  The first input transistor M41 is composed of a p-channel MOS field effect transistor, and its gate is connected to the terminal T16. The signal supplied to the terminal T16 is supplied to the gate of the first input transistor M41 as the first input signal.

  The second input transistor M42 is composed of a p-channel MOS field effect transistor, and has a gate connected to a connection point between the resistor R12 and the resistor R13. The potential at the connection point between the resistor R12 and the resistor R13 is supplied to the gate of the second input transistor M42 as the second input signal.

  The first input transistor M41 draws a current corresponding to the first input signal from the current source 131 and outputs it from the drain. The current output from the drain of the first input transistor M41 is supplied to the comparison circuit unit 121 as the first current. The second input transistor M42 draws a current corresponding to the second input signal from the current source 131 and outputs it from the drain. The current output from the drain of the second input transistor M42 is supplied to the comparison circuit unit 121 as a second current.

[First input control circuit 132]
The first input control circuit 132 includes n-channel MOS field effect transistors M51 and M52 and an inverting circuit 141. When the output of the comparison circuit unit 121 is at a low level, the first input control circuit 132 starts from the first input transistor M41. Control is performed so that the first current supplied to the comparison circuit unit 121 is reduced.

  The transistor M51 has a drain connected to the connection point between the drain of the first input transistor M41 and the comparison circuit unit 121, a source connected to the drain of the transistor M52, and a gate connected to the comparison circuit unit via the inverting circuit 141. The output terminal 121 is connected to the connection point between the drain of the transistor M37 and the drain of the transistor M38. The drain of the transistor M52 is connected to the source of the transistor M51, the source is grounded, and the bias voltage Vbias1 is applied to the gate from the bias power supply 123.

  When the potential at the connection point between the drain of the transistor M37 and the drain of the transistor M38, which is the output terminal of the comparison circuit unit 121, becomes low level, the output of the inverting circuit 141 becomes high level. When the output of the inverting circuit 141 becomes high level, the transistor M51 is turned on. When the transistor M51 is turned on, the transistor M52 draws a current from the connection point between the drain of the first input transistor M41 and the comparison circuit unit 121 by a constant current set by the bias voltage Vbias1. As a result, the first current corresponding to the first input signal decreases.

  When the potential at the connection point between the drain of the transistor M37 and the drain of the transistor M38, which is the output terminal of the comparison circuit unit 121, is high, the output of the inverting circuit 141 is low. When the output of the inverting circuit 141 is at a low level, the transistor M51 is off, and the first current corresponding to the first input signal is supplied to the comparison circuit unit 121 as it is.

[Second input control circuit 133]
The second input control circuit 133 is composed of n-channel MOS field effect transistors M61 and M62, and is supplied from the second input transistor M42 to the comparison circuit unit 121 when the output of the comparison circuit unit 121 is at a high level. The second current is controlled to be reduced.

  The transistor M61 has a drain connected to a connection point between the drain of the second input transistor M42 and the comparison circuit unit 121, a source connected to the drain of the transistor M62, and a gate serving as an output terminal of the comparison circuit unit 121. The transistor M37 is connected to the connection point between the drain of the transistor M38 and the drain of the transistor M38. The transistor M62 has a drain connected to the source of the transistor M61, a source grounded, and a bias voltage Vbias1 applied from the bias power supply 123 to the gate.

  When the potential at the connection point between the drain of the transistor M37 serving as the output terminal of the comparison circuit unit 121 and the drain of the transistor M38 becomes high, the transistor M61 is turned on. When the transistor M61 is turned on, the transistor M62 draws current from the connection point between the drain of the second input transistor M42 and the comparison circuit unit 121 by a constant current set by the bias voltage Vbias1. As a result, the second current corresponding to the second input signal is reduced.

  When the potential at the connection point between the drain of the transistor M37 and the drain of the transistor M38, which is the output terminal of the comparison circuit unit 121, is low, the transistor M61 is off and the comparison circuit unit 121 has a second input. The second current corresponding to the signal is supplied as it is.

[Operation]
FIG. 7 is a diagram for explaining the operation of the comparator 76. 7A shows the first input and the second input, FIG. 7B shows the first current and the second current, FIG. 7C shows the operation waveform of the output signal, and FIG. The state of the first input control circuit 132, FIG. 7E shows the state of the second input control circuit 133.

  In a state where the first input signal is larger than the second input signal at time t0, the first current becomes smaller than the second current, and the output of the comparison circuit unit 121 becomes a low level.

  When the output of the comparison circuit unit 121 is at a low level, the transistor M51 of the first input control circuit 132 is turned on, and the first current is drawn into the first input control circuit 132 and reduced. When the output of the comparison circuit unit 121 is at a low level, the transistor M61 of the second input control circuit 133 is turned off, and the second current is supplied to the comparison circuit unit 121 as it is. In this state, the output is not inverted unless the first input signal is larger than the second input signal by a certain level.

  Next, when the first input signal becomes larger than the second input signal by a certain level or more at time t1, the first current becomes larger than the second current, and the output of the comparison circuit unit 121 becomes the high level. When the output of the comparison circuit unit 121 becomes a high level, the transistor M51 of the first input control circuit 132 is turned off, and the first current is supplied to the comparison circuit unit 121 as it is. Further, the transistor M61 of the second input control circuit 133 is turned on, and a part of the second current is drawn into the second input control circuit 133 to be reduced. In this state, the output is not inverted unless the first input signal is lower than the second input signal by a certain level or more.

  Next, when the first input signal becomes smaller than the second input signal by a certain level or more at time t2, the first current becomes smaller than the second current, and the output of the comparison circuit unit 121 becomes the low level. When the output of the comparison circuit unit 121 becomes high level, the transistor M51 of the first input control circuit 132 is turned on, and a part of the first current is drawn into the first input control circuit 132 to be reduced. In addition, the transistor M61 of the second input control circuit 133 is turned off, and the second current is supplied to the comparison circuit unit 121 as it is. In this state, the output is not inverted unless the first input signal is larger than the second input signal by a certain level or more.

  As described above, hysteresis can be given to the input / output characteristics.

  At this time, in this embodiment, since the first input and the second input are supplied to the gates of the input transistors M41 and M42 formed of MOS field effect transistors, the current supply capability is not sufficient on the input side. Hysteresis operation is also possible.

  Further, by making the channel length of the transistor M35 and the channel length of the transistor M36 constituting the comparison circuit unit 121 different, the current supply capabilities of the transistor M35 and the transistor M36 are made different so that the input / output signal has an offset. Can do. Note that by changing the channel width of the transistor M35 and the channel width of the transistor M36, the current supply capabilities of the transistor M35 and the transistor M36 can be made different so that the input / output signal has an offset. Further, by changing both the channel length and the channel width, the current supply capability of the transistor M35 and the transistor M36 can be similarly changed, and the input / output signal can be offset.

  [Protection circuit section 62]

  Next, the protection circuit unit 62 will be described.

  The protection circuit unit 62 is a circuit for detecting the maximum value of the applied voltage and supply current of the cold cathode fluorescent tube unit 11 and detecting an abnormality of the cold cathode fluorescent tube unit 11.

  FIG. 8 is a block diagram of the protection circuit unit 62.

  The protection circuit unit 62 includes a maximum value output circuit 91, a comparator 92, a reference voltage source 93, a coefficient multiplication circuit 94, comparators 95, 96, 97, a reference voltage source 98, an AND gate 99, an output circuit 100, an average value circuit 101, It consists of diodes D1 and D2.

  The maximum value output circuit 91 receives detection voltages from terminals T12 and T13. A diode D1 is connected in the reverse direction between the terminal T12 and the ground. A diode D2 is connected to the terminal T13 in the reverse direction between the terminal T13 and the ground.

  The diodes D1 and D2 act as protection elements for the protection IC 13. The detection voltage is half-wave rectified from the terminals T12 and T13 by the diodes D1 and D2. The signals supplied to the terminals T12 and T13 and half-wave rectified by the diodes D1 and D2 are supplied to the maximum value output circuit 91.

  The maximum value output circuit 91 selectively outputs the larger detection voltage of the detection voltage supplied from the terminal T12 or the detection voltage supplied from the terminal T13.

  The maximum value signal output from the maximum value output circuit 91 is supplied to the non-inverting input terminal of the comparator 92 and the coefficient multiplication circuit 94. A reference voltage is applied from the reference voltage source 93 to the inverting input terminal of the comparator 92. The reference voltage generated by the reference voltage source 93 is set to the lower limit value of the maximum value signal.

  If the maximum value signal from the maximum value output circuit 91 is larger than the reference voltage generated by the reference voltage source 93, the comparator 92 sets the output to the high level, and the maximum value signal from the maximum value output circuit 91 is the reference voltage source 93. If it is smaller than the generated reference voltage, the output is set to low level. The output of the comparator 92 is supplied to the AND gate 99.

  The coefficient multiplication circuit 94 multiplies the maximum value signal output from the maximum value output circuit 91 by 0.8. That is, a signal having 80% of the maximum value is output. The signal multiplied by 0.8 by the coefficient multiplication circuit 94 is supplied to the inverting input terminals of the comparators 95 and 96.

  The detection signal V12 supplied to the terminal T12 is supplied to the non-inverting input terminal of the comparator 95. The comparator 95 sets the output to a high level if the detection signal V12 is larger than the signal of 80% of the maximum value from the coefficient multiplication circuit 94, and if the detection signal V12 is smaller than the signal of 80% of the maximum value from the coefficient multiplication circuit 94. The output is set to low level.

  The detection signal V13 supplied to the terminal T13 is supplied to the non-inverting input terminal of the comparator 96. The comparator 96 sets the output to a high level if the detection signal V13 is larger than the signal of 80% of the maximum value from the coefficient multiplication circuit 94, and if the detection signal V13 is smaller than the signal of 80% of the maximum value from the coefficient multiplication circuit 94. The output is set to low level. Outputs of the comparators 95 and 96 are supplied to an AND gate 99.

  The inverting input terminal of the comparator 97 is supplied with the output of the hold circuit 15 from the terminal T11. The hold circuit 15 holds the voltage at the connection point between the detection resistor Rs1 and the detection resistor Rs2 and the maximum voltage at the connection point between the detection resistor Rs3 and the detection resistor Rs4. A reference voltage is applied from the reference voltage source 98 to the inverting input terminal of the comparator 97. The reference voltage generated by the reference voltage source 98 is set to a voltage corresponding to the maximum drive voltage.

  The comparator 97 sets the output to a low level if the output voltage of the hold circuit 15 is higher than the reference voltage from the reference voltage 98, and sets the output to a high level if the output voltage of the hold circuit 15 is lower than the reference voltage from the reference voltage 98. To do. The output of the comparator 97 is supplied to the AND gate 99.

  The outputs of the comparators 92, 95, 96, and 97 are supplied to the AND gate 99. The AND gate 99 outputs an AND logic of outputs from the comparators 92, 95, 96, and 97. The AND gate 99 outputs a high level when all the outputs of the comparators 92, 95, 96, and 97 are at a high level, and outputs when any one of the outputs of the comparators 92, 95, 96, and 97 is at a low level. Becomes low level. The output of the AND gate 99 is supplied to the output circuit 100.

  The output circuit 100 includes a current source 111, a comparator 112, a reference voltage source 113, a capacitor C21, and transistors M11 and M12.

  The output of the AND gate 99 is supplied to the gate of the transistor M11. The transistor M11 is composed of an n-channel MOS field effect transistor, and has a source grounded and a capacitor C21 connected in parallel with the drain-source. A charging current is supplied from the current source 111 to a connection point between the drain of the transistor M11 and the capacitor C21.

  The transistor M11 is turned on when the output of the AND gate 99 is at a high level, and turned off when the output of the AND gate 99 is at a low level. A charging current is supplied from the current source 111 to the capacitor C21 while the transistor M11 is off, and the capacitor C21 is charged. When the transistor M12 is turned on, the charge charged in the capacitor C21 is discharged to the ground through the transistor M11. Thus, the capacitor C21 is charged / discharged according to the on / off of the transistor M11.

  The charging voltage of the capacitor C21 is applied to the inverting input terminal of the comparator 112. A reference voltage is supplied from the reference voltage source 113 to the non-inverting input terminal of the comparator 112. The comparator 112 outputs a low level if the charging voltage of the capacitor C21 is larger than the reference voltage from the reference voltage source 113, and outputs a high level if the charging voltage of the capacitor C21 is smaller than the reference voltage from the reference voltage source 113. And The output of the comparator 112 is supplied to the gate of the transistor M12.

  The transistor M12 is composed of an n-channel MOS field effect transistor, the source is grounded, and the drain is connected to the output terminal T14. The transistor M12 is turned on when the output of the comparator 112 is at a high level and turned off when it is at a low level.

  [Operation of Protection Circuit Unit 62]

  In the normal operation state, the outputs of the comparators 92, 95, 96 and 97 are all at a high level, and the output of the AND gate 99 is at a high level. When the output of the AND gate 99 is at a high level, the transistor M11 is turned on. When the transistor M11 is turned on, the capacitor C21 is discharged, and the charging voltage of the capacitor C21 becomes low level. When the charging voltage of the capacitor becomes low level, the output of the comparator 112 becomes high level. When the output of the comparator 112 becomes high level, the transistor M12 is turned on and the terminal T14 becomes low level.

  Further, when the connection state and the lighting state of the cold cathode fluorescent tube unit 11 are abnormal, and the output of the maximum output circuit 91 becomes smaller than the reference voltage, that is, the lower limit value of the maximum value signal, the output of the comparator 92 becomes low level. .

  When the output of the comparator 92 becomes low level, the output of the AND gate 99 becomes low level. When the output of the AND gate 99 is at a low level, the transistor M11 is turned off. By turning off the transistor M11, the capacitor C21 is charged by the current source 111. When the capacitor C21 is charged and the charging voltage becomes higher than the reference voltage 113, the output of the comparator 112 becomes low level. When the output of the comparator 112 becomes low level, the transistor M12 is turned off and the terminal T14 becomes high level. The abnormal state of the cold cathode fluorescent tube section 11 can be detected by the terminal T14 being at a high level.

  Further, when the voltage at the terminal T12 or the terminal T13 becomes smaller than 80% of the output of the coefficient multiplication circuit 94 or the maximum value signal due to an abnormality such as connection state of the cold cathode fluorescent tube portion 11 or extinction, the output of the comparator 95 or 96 is Become low level.

  When the output of the comparator 92 becomes low level, the output of the AND gate 99 becomes low level. When the output of the AND gate 99 is at a low level, the transistor M11 is turned off. By turning off the transistor M11, the capacitor C21 is charged by the current source 111. When the capacitor C21 is charged and the charging voltage becomes higher than the reference voltage 113, the output of the comparator 112 becomes low level. When the output of the comparator 112 becomes low level, the transistor M12 is turned off and the terminal T14 becomes high level. The abnormal state of the cold cathode fluorescent tube section 11 can be detected by the terminal T14 being at a high level.

  When the cold cathode fluorescent tube unit 11 is in an overvoltage state and the voltage at the terminal T11 becomes higher than the reference voltage generated by the reference voltage source 98, the output of the comparator 97 becomes low level. When the output of the comparator 97 becomes low level, the output of the AND gate 99 becomes low level. When the output of the AND gate 99 is at a low level, the transistor M11 is turned off. By turning off the transistor M11, the capacitor C21 is charged by the current source 111. When the capacitor C21 is charged and the charging voltage becomes higher than the reference voltage 113, the output of the comparator 112 becomes low level. When the output of the comparator 112 becomes low level, the transistor M12 is turned off and the terminal T14 becomes high level. The abnormal state of the cold cathode fluorescent tube section 11 can be detected by the terminal T14 being at a high level. The terminal T14 is connected to the terminal T5 of the drive IC 13.

  The average value circuit 101 is supplied with detection signals V12 and V13 from terminals T12 and T13. The average value circuit 101 generates a signal corresponding to the average value of the detection signals V12 and V13 and outputs it from the terminal T18. The terminal T18 is connected to the terminal T2 of the driving IC 13.

It is a block block diagram of one Example of this invention. 3 is a block configuration diagram of a drive IC 13. FIG. 3 is a block configuration diagram of a PWM control unit 61. FIG. It is a figure which shows the change of the charging voltage of the capacitor C1. It is a block block diagram of the modification of the PWM control part. 3 is a circuit configuration diagram of a comparator 76. FIG. 6 is an operation explanatory diagram of a comparator 76. FIG. 3 is a block configuration diagram of a protection circuit unit 62. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Cold cathode fluorescent tube lighting system 11 Cold cathode fluorescent tube part, 12 Resonance circuit, 13 Drive IC, 14 Protection IC
15 Hold circuit, 16 Reference voltage source 21, 22 Cold cathode fluorescent tube pair, 31, 32, 41, 42 Cold cathode fluorescent tube 61 PWM control unit, 62 Protection circuit unit C1, C2 Capacitor 91 Maximum value output circuit, 92, 95 97, 112 Comparator 94 Coefficient multiplication circuit, 98 Reference voltage source, 99 AND gate, 100 Output circuit 101 Average value circuit, D1, D2 Diodes 121, 221 Current source

Claims (6)

A first capacitor;
A second capacitor;
Switch means provided between the first capacitor and the second capacitor, for switching a connection between the first capacitor and the second capacitor;
Voltage detection means for detecting the voltage across the switch means;
The charging / discharging control of the first capacitor is performed, and control means for controlling the switching of the switching means according to a detection result of the voltage detection means when charging the first capacitor is provided. Charge / discharge circuit. 2. The charge / discharge circuit according to claim 1, wherein the control means switches the switch means in accordance with a detection result of the voltage detection means and a polarity of a voltage across the switch means. The control means turns on the switch means to charge both the first capacitor and the second capacitor to substantially the same potential, and then turns off the switch means to discharge the first capacitor. After the first capacitor is discharged, charging of the first capacitor is started, and as a result of detection by the voltage detection means, the charging potential of the first capacitor is larger than the charging potential of the second capacitor. 3. The charging / discharging circuit according to claim 1, wherein the switch means is turned on when it becomes. A first capacitor;
A second capacitor;
Switch means provided between the first capacitor and the second capacitor, for switching a connection between the first capacitor and the second capacitor;
Detecting the voltage across the switch means;
A charging / discharging method, wherein the switching unit is subjected to switching control according to a detection result of the voltage detection unit. 5. The charge / discharge method according to claim 4, wherein the switch means is switched according to the polarity of the voltage across the switch means. After the switch means is turned on and both the first capacitor and the second capacitor are charged to substantially the same potential, the switch means is turned off, the first capacitor is discharged, and the first capacitor is discharged. After discharging the capacitor, the charging of the first capacitor is started, and when the charging potential of the first capacitor becomes larger than the charging potential of the second capacitor, the switch means is turned on. The charging / discharging method according to claim 4 or 5, characterized in that:

Images