JP2006049823A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an improved thin film transistor which makes the entire channel region substantially partially depleted, irrespective of the size of the taper angle at the channel region end, thus suppressing the characteristic variation. <P>SOLUTION: The semiconductor device comprises a semiconductor layer provided on one surface of a substrate, a first conductivity type channel region provided in the semiconductor layer, second conductivity type high-concentration diffused regions adjacent and opposite to both sides of the channel region with leaving a space from the semiconductor layer, a first conductivity type body terminal connected to the channel region for fixing the potential of the channel region, an insulation film laid on the channel region, a gate electrode covering the channel region on the insulation film, and a channel end region doped with a first conductivity type impurity provided in the end of the semiconductor layer at the end of the channel region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a thin film transistor used for a liquid crystal display device and a manufacturing method thereof.

  A so-called thin film transistor (TFT) in which a field effect transistor is formed in a semiconductor layer provided above a substrate is used as, for example, a switching element for driving a liquid crystal display device.

An example of a conventional thin film transistor 1 is shown in FIG. 12A is a perspective view, and FIG. 12B is a cross-sectional view in the channel width direction along the cutting line 12B-12B shown in FIG. 12A. A semiconductor layer 14 is formed on a substrate 10, for example, a glass substrate, via a base insulating film 12, for example, a silicon oxide film (SiO ₂ ). The semiconductor layer 14 is, for example, a polycrystalline silicon layer having large crystal grains. A thin film transistor having, for example, a channel region 18, source and drain regions 28 and 30, a gate insulating film 34 formed above the channel region 18, and a gate electrode 36 formed above the gate insulating film 34 on the semiconductor layer 14. Is formed. Thus, the thin film transistor 1 in which the gate electrode 36 is formed above the semiconductor layer 14 is called a top-gate thin film transistor. Here, a substrate having a semiconductor layer 14 having a thickness (body film thickness) of 200 nm is used.

In this thin film transistor 1, the channel width direction cross section of the channel region 18 has a tapered side wall surface at its end as shown in FIG. 12B (for example, Patent Document 1 and Patent Document 2). The channel region 18 includes a channel flat portion 19 and a taper portion 20. In the thin film transistor disclosed in Patent Document 1, a gate oxide film thicker than the flat portion is formed on the intentionally formed tapered portion, thereby reducing the electric field concentration in the tapered portion.
JP-A-8-172198 US Pat. No. 6,184,556 US Pat. No. 6,753,549 US Patent Application Publication No. 2001/0036710

  However, it is preferable that the end of the channel region 18 of the thin film transistor 1 is a right angle also in miniaturization. However, in reality, the end of the channel region 18 inevitably has a tapered portion 20 in the manufacturing process, and the taper angle cannot be controlled to a constant value within the surface of the substrate 10 or between the substrates 10. is there. That is, the taper angle at the end has variations in the manufacturing process, and it has been clarified that such variations in the taper angle affect the characteristics of the thin film transistor 1, for example, the threshold value and the subthreshold characteristics. . In particular, it has been clarified that the influence is remarkable when the thin film transistor 1 is used in a partially depleted type. In the partially depleted transistor, the entire thickness (body thickness) of the semiconductor layer in the channel region 18 is not made a depletion layer during operation, but a depletion layer is formed only in a part thereof. Since the partially depleted transistor can improve the punch-through breakdown voltage as compared with the fully depleted transistor, it is advantageous for a high breakdown voltage transistor or miniaturization.

  FIG. 13 is an example of drain current-gate voltage (IV) characteristics of a partially depleted n-channel thin film transistor 1 according to the prior art. The horizontal axis represents the gate voltage, and the vertical axis represents the drain current. As the gate voltage increases from about −1V, the drain current increases, but a “kump” in which the curve is distorted before saturation is observed, as shown by the circled portion in the figure. This hump is caused by the presence of the tapered portion 20. That is, as the gate voltage increases in the positive direction, a depletion layer is formed in the channel region 18 and a drain current begins to flow. When the gate voltage is further increased, the depletion layer width increases in the channel flat portion 19 and the drain current increases. However, in the tapered portion 20, the thickness of the semiconductor layer 14 changes from 0 to the body thickness, so that the entire thickness becomes a depletion layer at a low gate voltage in a portion where the thickness of the semiconductor layer 14 is thin. That is, the depletion layer is completely depleted, and the depletion layer no longer spreads. As a result, as shown in FIG. 13, a bump occurs in the IV characteristic.

When the body region is thicker than the thickness of the depletion layer, such as when the impurity concentration of the channel region 18 is high or the gate voltage is low, a partial depletion type is achieved. FIG. 14 is a diagram showing the relationship between the impurity concentration of the channel region 18 and the maximum depletion layer width. In other words, it is a diagram showing a boundary between a fully depleted type and a partially depleted type. In FIG. 14, the lower side of the curve is a full depletion type (FD), and the upper side is a partial depletion type (PD). For example, when the impurity concentration of the channel region 18 is 1 × 10 ¹⁷ atoms / cm ³ , the maximum depletion layer width is about 110 nm. In this case, if the body film thickness is 200 nm, the channel flat portion 19 becomes a partial depletion type. However, when the thickness of the semiconductor layer of the taper portion 20 is 100 nm or less, the taper portion 20 becomes a fully depleted type. As described above, in a thin film transistor, when a full depletion type and a partial depletion type are mixed in a region having a body film thickness of 100 nm or less and a region having a thickness greater than 100 nm, variations in threshold values, subthreshold characteristics, and the like are caused. It became clear that

  As described above, in the thin film transistor, it is important to control the end portion of the channel region 18, that is, the tapered portion 20 in order to stabilize the element characteristics and improve the reliability. Patent Document 2 discloses a semiconductor device that improves the breakdown voltage between the source and the drain and achieves both high reliability and high electric field mobility even when the substrate potential is floating. This semiconductor device has a pinning region that prevents a depletion layer that forms a channel from extending to an end portion of the channel region. The pinning region is doped with an impurity giving a conductivity type opposite to that of the source / drain. Further, in Patent Document 3, in order to suppress variation in characteristics of the thin film transistor, the angle of the taper portion is set to 60 ° or more, the taper portion is insulative, or the taper portion has conductivity opposite to that of the source / drain. Techniques for doping with impurities that provide molds are disclosed. Further, Patent Document 4 discloses a technique for controlling the angle of the tapered portion by LOCOS (local oxidation of silicon). However, these patents do not mention control of the substrate potential.

  In order to address the above-described problems, the present invention can make the entire channel region substantially partially depleted regardless of the taper angle at the end of the channel region. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same in which variation in characteristics of a thin film transistor caused by mixing types is reduced.

  The above-described problems are solved by the following semiconductor device and manufacturing method thereof according to the present invention.

  A semiconductor device according to one embodiment of the present invention includes a semiconductor layer provided on one side of a substrate, a first conductivity type channel region provided in the semiconductor layer, and adjacent to the channel region. A high-concentration diffusion region of the second conductivity type provided opposite to both sides and spaced from the semiconductor layer, and a body terminal of the first conductivity type connected to the channel region and fixing the potential of the channel region An insulating film provided on the channel region; a gate electrode provided on the insulating film so as to cover the channel region; and an end portion of the channel region, provided on an end portion of the semiconductor layer And a channel end region to which an impurity of the first conductivity type is added.

  A semiconductor device according to another aspect includes a semiconductor layer provided on one surface side of a substrate, a channel region of a first conductivity type provided in the semiconductor layer, adjacent to the channel region, and both sides of the channel region. A low concentration diffusion region of a second conductivity type provided opposite to the semiconductor layer and spaced apart from the semiconductor layer, and a high concentration of a second conductivity type provided in the semiconductor layer outside each of the low concentration diffusion regions A diffusion region; a first conductivity type body terminal connected to the channel region and fixing the potential of the channel region; an insulating film provided on the channel region; and the channel region on the insulating film. A gate electrode provided in an overlying manner; and an end portion of the channel region, and a channel end region to which an impurity of the first conductivity type is added provided at an end portion of the semiconductor layer. To do.

  A semiconductor device according to still another aspect is a semiconductor device including a semiconductor layer provided on one surface side of a substrate and first and second semiconductor elements provided in the semiconductor layer, wherein the first semiconductor The element is adjacent to the first channel region of the first conductivity type provided in the semiconductor layer and the first channel region, and is separated from the semiconductor layer so as to face both sides of the first channel region. The first conductivity type first high-concentration diffusion region provided in the first channel region and the first channel region connected to the first channel region and fixing the potential of the first channel region. A body terminal; a first insulating film provided on the first channel region; a first gate electrode provided on the first insulating film so as to cover the first channel region; At the end of the first channel region and at the end of the semiconductor layer; And a first channel end region doped with an impurity of the first conductivity type, and the second semiconductor element is a second channel region of the second conductivity type provided in the semiconductor layer. A second high-concentration diffusion region of the first conductivity type adjacent to the second channel region and opposed to both sides of the second channel region and spaced apart from the semiconductor layer; A second body terminal of a second conductivity type provided in the semiconductor layer connected to the second channel region and fixing the potential of the second channel region; and provided on the second channel region. A second insulating film; a second gate electrode provided on the second insulating film so as to cover the second channel region; and an end of the second channel region, wherein the semiconductor A second channel doped with an impurity of a second conductivity type provided at an end of the layer; Characterized by comprising a Le end region.

  A semiconductor device according to still another aspect is a semiconductor device including a semiconductor layer provided on one surface side of a substrate and first and second semiconductor elements provided in the semiconductor layer, wherein the first semiconductor The element is adjacent to the first channel region of the first conductivity type provided in the semiconductor layer and the first channel region, and is separated from the semiconductor layer so as to face both sides of the first channel region. A first low-concentration diffusion region of the second conductivity type provided in the first and second high-concentration diffusion regions of the second conductivity type provided in the semiconductor layer outside the first low-concentration diffusion region. A first body terminal of a first conductivity type provided in the semiconductor layer connected to the first channel region and fixing the potential of the first channel region; and the first channel region A first insulating film provided on the first insulating film; and A first gate electrode provided to cover the first channel region and a first conductivity type provided at an end of the first channel region and at an end of the semiconductor layer And a second channel region of the second conductivity type provided in the semiconductor layer, and the second channel region. A second low-concentration diffusion region of the first conductivity type provided opposite to both sides of the second channel region and spaced apart from the semiconductor layer, and the second low-concentration diffusion region Provided in the semiconductor layer which is connected to the second high concentration diffusion region of the first conductivity type provided in the outer semiconductor layer and the second channel region and fixes the potential of the second channel region. Second body terminal of the second conductivity type formed, and the second channel A second insulating film provided on the region, a second gate electrode provided on the second insulating film so as to cover the second channel region, and an end of the second channel region And a second channel end region to which an impurity of the second conductivity type is added provided at an end portion of the semiconductor layer.

  According to still another aspect, a semiconductor device includes a semiconductor layer provided on one side of a substrate, a channel region of a first conductivity type provided in the semiconductor layer, and adjacent to the channel region. A high-concentration diffusion region of a second conductivity type provided opposite to both sides and spaced apart from the semiconductor layer, and a second conductivity type connected to the channel region and provided in the semiconductor layer for fixing the potential of the channel region A body terminal of one conductivity type, an insulating film provided on the channel region, a gate electrode provided on the insulating film so as to cover the channel region, and an end of the channel region, And a substantially insulating channel end region provided at an end of the semiconductor layer.

  According to still another aspect, a semiconductor device includes a semiconductor layer provided on one side of a substrate, a channel region of a first conductivity type provided in the semiconductor layer, and adjacent to the channel region. A low-concentration diffusion region of a second conductivity type provided opposite to both sides and separated from the semiconductor layer, and a high-concentration of a second conductivity type provided in the semiconductor layer outside the low-concentration diffusion region A diffusion region; a body terminal of a first conductivity type provided in the semiconductor layer connected to the channel region and fixing a potential of the channel region; an insulating film provided on the channel region; and the insulation A gate electrode provided on the film so as to cover the channel region; and a substantially insulating channel end region provided at an end of the channel region and at an end of the semiconductor layer. It is characterized by.

  According to another aspect of the present invention, a method of manufacturing a semiconductor device includes a step of patterning a semiconductor film formed on one side of a substrate to form an element region of a first conductivity type, and forming a gate insulating film on the element region A step of forming a gate electrode on the gate insulating film so as to cover a part of the element region; and a second conductive type high concentration diffusion region in the element region adjacent to the outside of the gate electrode. A step of forming, a step of forming a body terminal of a first conductivity type in a region different from the high-concentration diffusion region, the device region outside the gate electrode, and the device covered with the gate electrode A step of adding an impurity having a first conductivity type to an end portion of the region excluding the high concentration diffusion region and a portion in contact with the body terminal.

  According to the present invention, an improved thin film transistor can be achieved by suppressing variation in characteristics of the thin film transistor.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the figure, corresponding parts are indicated by corresponding reference numerals.

(First embodiment)
An example of the top-gate thin film transistor 3 according to the first embodiment of the present invention is shown in FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view in the channel width direction along the cutting line 1B-1B shown in FIG. 1A.

  A semiconductor layer 14 is formed on a support substrate 10, for example, a glass substrate, via a base insulating film 12, for example, a silicon oxide film. The semiconductor layer 14 is etched into a region for forming a device. A thin film transistor 3 having a body terminal structure is formed on the semiconductor layer 14. The thin film transistor 3 having a body terminal structure includes, for example, a channel region 18 formed in the semiconductor layer 14, sources and drains 28 and 30, a body terminal 32, a gate insulating film 34 formed above the channel region 18, The gate electrode 36 is formed above the gate insulating film 34. The body terminal 32 is used to fix the potential of the channel region 18 and stabilizes the characteristics of the thin film transistor 3.

  FIG. 1B shows a cross section in the channel width direction of the thin film transistor 3 indicated by a cutting line 1B-1B in FIG. The channel region 18 formed in the semiconductor layer 14 includes a channel end region 22 having a taper and a flat channel flat portion 19. Impurities having a conductivity type different from that of the source / drains 28 and 30 are added to the channel end region 22 to control the impurity concentration to a predetermined value. Further, the channel end region indicated by 22b in FIG. 1A, that is, the tapered portion of the portion of the semiconductor region 14 where the body terminal 32 is drawn from the channel region 18 and covered with the gate electrode 36, Similar to the channel end region 22, it is preferable to control the impurity concentration. By controlling the impurity concentration of the channel end regions 22 and 22b in this way, the manufacturing variation of the thin film transistor 3 can be reduced, the yield can be improved, and the characteristics of the thin film transistor 3 can be stabilized.

  Next, a manufacturing process of the thin film transistor 3 will be described with reference to FIGS. 2 to 7 by taking an n-channel transistor as an example. 2 to 7, each figure (a) is a cross-sectional view in the channel length direction perpendicular to FIG. 1 (b) and indicated by the section line 2A-2A in FIG. 1 (a). ) Is a cross-sectional view in the channel width direction indicated by section line 1B-1B in FIG.

  (1) First, a semiconductor substrate 100 that is a starting material for a thin film transistor is formed. As shown in FIGS. 2A and 2B, a base insulating film 12, such as a silicon oxide film, is formed on a support substrate 10, such as a glass substrate, by a plasma CVD method. A semiconductor layer 14, for example, an amorphous silicon film is formed on the base insulating film 12 by a plasma CVD method. A cap insulating film 16, for example, a silicon oxide film is formed on the surface of the semiconductor layer 14 by plasma CVD. Next, the semiconductor layer 14 is crystallized into a semiconductor film having large crystal grains by irradiating the semiconductor layer 14 with laser light having a desired light intensity distribution from the cap insulating film 16 side by a crystallization apparatus (not shown). The laser light is, for example, energy light in which excimer laser light is homogenized to make the light intensity uniform and phase modulated by a phase shifter to form a light intensity distribution. In this way, the semiconductor substrate 100 is formed.

As the support substrate 10, for example, a glass substrate, a quartz substrate, a semiconductor substrate such as silicon, a plastic substrate, or a ceramic substrate can be used. The base insulating film 12 is a film that prevents impurities from the base substrate 10 from diffusing into the semiconductor layer 14 and has a heat storage function in the crystallization process. For example, a silicon oxide film (SiO ₂ film), a silicon nitride film (SiN film) can be used.

The semiconductor layer 14 is a film on which a thin film transistor device is formed. For example, an amorphous silicon film or a polycrystalline silicon film is deposited and crystallized into a polycrystalline film having large crystal grains by an arbitrary crystallization method. A silicon film can be used. During the crystallization, an impurity (dopant), for example, boron can be added to adjust the threshold value of the thin film transistor 3. The semiconductor layer 14 is a crystallized silicon layer, and the impurity concentration thereof is, for example, 2 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁸ atoms / cm ³ . The semiconductor layer 14 used in this embodiment has a thickness of 200 nm and an impurity concentration of 1 × 10 ¹⁷ atoms / cm ³ .

As the cap insulating film, for example, a SiO ₂ film or a SiN film can be used. The cap insulating film 16 is a film having a function of storing heat heated by laser light in the crystallization process, and is, for example, a silicon oxide film or a silicon nitride film.

  (2) Next, in order to form a device, a separation process of the semiconductor layer 14 is performed. The semiconductor layer 14 is processed by lithography and etching techniques to form device regions as shown in FIGS. Although the side wall at the end of the device region is preferably vertical, the tapered portion 20 is actually formed as described above.

(3) Next, after removing the cap insulating film 16 on the semiconductor layer 14, a gate insulating film 34 is deposited on the entire surface. As the gate insulating film 34, for example, a SiO ₂ film, a SiN film, or a silicon oxynitride film (SiON film) can be used. Further, a conductive film that is a material for the gate electrode is deposited above the gate insulating film 34. As a gate electrode material, for example, n + polycrystalline silicon or tungsten (W), tantalum (Ta), titanium (Ti) or the like doped with phosphorus (P) or arsenic (As) at a high concentration is used as a main component. Sex materials can be used. The gate electrode material is patterned by lithography and etching techniques to form the gate electrode 36. (Fig. 4 (a), (b))
(4) Next, in order to improve the breakdown voltage characteristics of the thin film transistor, an LDD or an extension (hereinafter referred to as LDD) having an impurity concentration lower than that of the source / drain is formed. That is, n-type impurities such as As are ion-implanted into the semiconductor layer 14 with low energy using the gate electrode 36 as a mask, and doping 25 for forming LDD is performed. (Fig. 4 (a))
(5) Then, an insulating film 38, for example, a SiN film is deposited on the entire surface, and a side wall insulating film 38 is formed on the side wall portion of the gate electrode 36 by anisotropic dry etching. By using the gate electrode 36 and the sidewall insulating film 38 as a mask, n-type impurities having a higher concentration than LDD, for example, As, are ion-implanted into the semiconductor layer 14 with high energy, and dopings 27 and 29 are performed to form the source / drain. . (Fig. 5 (a))
(6) Next, portions other than the taper portion 20 and the body terminal 32 (see FIG. 1A) of the channel region covered with the gate electrode 36 are covered with a mask 40, and the conductivity is different from the conductivity type of the source / drain. A p-type impurity such as boron (B) is ion-implanted 21 into the tapered portion 20 and the body terminal 32 of the channel. (Fig. 6 (a), (b))
(7) After removing the mask 40, annealing is performed in order to electrically activate the ion-implanted impurity, thereby forming the LDD 26, the source / drain 28, 30, the channel end regions 22, 22b, and the body terminal 32. . (Fig. 7 (a), (b))
Thereafter, wiring and the like are formed, and the thin film transistor 3 having a body terminal structure is completed.

  If said process (6) is before process (7) after process (3), the order of the process can be changed arbitrarily.

FIG. 8 shows an example of drain current-gate voltage (IV) characteristics of the thin film transistor 3 formed as described above. In the figure, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. The channel length of the thin film transistor 3 is 2 μm, and the impurity (boron) concentration of the channel region 18 is 1 × 10 ¹⁷ atoms / cm ³ . The impurity in the channel end region 22 is boron, and the impurity concentration is 1 × 10 ¹⁹ atoms / cm ³ higher than the impurity concentration in the channel region 18. As is apparent from FIG. 8, the “hump” of the IV characteristic seen in FIG. 13 is not seen, indicating that the thin film transistor 3 having good characteristics could be formed. Even if a depletion layer is formed in the channel flat portion 19 even when a voltage is applied to the gate electrode 36 by making the impurity concentration of the channel end regions 22 and 22b higher than that of the channel flat portion 19, This is because no depletion layer is formed on 22 and 22b and the substrate potential is stabilized by the body terminal 32. That is, the partially depleted thin film transistor 3 can be formed entirely without depending on the taper angle of the channel end regions 22 and 22b.

Further, the effect of forming the body terminal 32 is noticeable in improving the source-drain breakdown voltage. Table 1 summarizes the influence of the body terminal on the source-drain breakdown voltage of the partially depleted transistor and the fully depleted transistor. In the n-channel transistor used here, the semiconductor layer 14 has a thickness of 200 nm for the partially depleted type and 50 nm for the fully depleted type, the transistor has a channel length of 2 μm, a channel width of 1 μm, and an impurity in the channel region 18. The concentration is 1 × 10 ¹⁷ atoms / cm ³ , and the impurity concentration of the channel end regions 22 and 22b is 1 × 10 ¹⁹ atoms / cm ³ . By adopting the body terminal structure, the source-drain breakdown voltage is remarkably improved in both the partial depletion type and the complete depletion type. Particularly in the case of the partial depletion type, the effect is remarkable. When there is no body terminal, the source-drain breakdown voltage is 0.8 V lower than that of the complete depletion type. The voltage is improved from 1.4 V to 6.2 V, and the breakdown voltage is higher than that of the fully depleted type.

  As described above, according to this embodiment, the substrate potential can be controlled, and the entire channel region 18 can be made substantially partially depleted regardless of the taper angle of the channel region end 20. Thus, there can be obtained a thin film transistor having improved characteristics such as a variation in characteristics of a thin film transistor and a withstand voltage, which are generated by mixing a fully depleted type and a partially depleted type.

(Modification of the first embodiment)
A modification of the first embodiment is shown in FIG. 9A is a plan view, FIG. 9B is a cross-sectional view in the channel width direction indicated by the section line 9B-9B in FIG. 9A, and FIG. 9C is FIG. It is sectional drawing of the channel length direction shown by the cutting line 9C-9C to a). This modification is a thin film transistor 5 in which an LDD or an extension (hereinafter abbreviated as LDD) is not formed at the ends of the source / drain 28 and 30 of the gate electrode 36. Also in this modification, the thin film transistor 5 has the body terminal 32, and the channel end regions 22 and 22b are doped with impurities of a conductivity type different from that of the source / drain 28 and 30.

  This thin film transistor 5 omits the process for forming the LDD from the first embodiment. This thin film transistor 5 can be formed by omitting the process for forming the LDD from the first embodiment. That is, the ion implantation step for forming the LDD shown in the step (4) and the step of forming the sidewall insulating film 38 shown in the step (5) are omitted.

Next, FIG. 10 shows drain current gate voltage characteristics of the thin film transistor 5 in which the LDD is not formed. In the figure, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. The impurity (boron) concentration in the channel flat portion 19 of the thin film transistor 5 is 5 × 10 ¹⁶ atoms / cm ³ , and the impurity (boron) concentration in the channel end regions 22 and 22 b is higher than the impurity concentration in the channel flat portion 19. 1 × 10 ¹⁹ atoms / cm ³ . As is apparent from FIG. 10, the “kump” of the IV characteristic is not seen as in FIG. 8, indicating that the thin film transistor 5 having good characteristics could be formed. That is, the thin film transistor 5 in which the channel region 18 is substantially entirely depleted can be formed without depending on the taper angle of the channel end regions 22 and 22b.

  Although the manufacturing process of the first embodiment has been described by taking the case of forming an n-channel transistor as an example, the p-channel transistor can be formed only by reversing the conductivity type of the impurity to be doped.

  Furthermore, in the case of a CMOS device including both an n-channel transistor and a p-channel transistor, the channel end region can be doped as follows without increasing the number of processes. That is, the doping of the channel end region of the n-channel transistor is performed simultaneously with the doping of the LDD or source / drain of the p-channel transistor. Similarly, the doping of the channel end region of the p-channel transistor is performed simultaneously with the doping of the LDD or source / drain of the n-channel transistor. In this way, a CMOS thin film transistor can be formed without increasing the number of steps.

(Second Embodiment)
The second embodiment is, for example, an n-channel thin film transistor 7 in which a channel end insulating region 24 in which this region is electrically inactive is formed by significantly increasing the resistivity of the tapered portion 20. An example of this embodiment is shown in FIG. 11A is a plan view, and FIG. 11B is a cross-sectional view in the channel width direction indicated by a cutting line 11B-11B in FIG. 11A. Also in this embodiment, the thin film transistor 7 has a body terminal 32 for controlling the substrate potential.

  The thin film transistor 7 of this embodiment can be formed by changing the impurity doping to the tapered portion 20 described in the step (6) as follows in the first embodiment. The doping to the body terminal 32 is performed separately from the processing to the tapered portion 20.

  (6-1) Cover the region of the channel region 18 other than the tapered portion 20 with a mask, and introduce impurities that significantly increase the resistivity of the tapered portion 20. For example, an impurity such as oxygen or nitrogen is introduced to form the channel end insulating region 24. Alternatively, in order to compensate for the carrier in the channel end region 24 and increase the resistance, for example, phosphorus (P) which is an impurity of a different conductivity type from the p-type channel region 18, for example, n-type impurity, is used. Ion implantation is performed in an amount that generates carriers of approximately the same number as the concentration.

  (6-2) Next, a region other than the body terminal 32 is covered with a mask, and a conductivity type different from the conductivity type of the source / drain 28 and 30, for example, boron (B) which is a p-type impurity is applied to the body terminal 32. Ions are implanted into the part.

  Also in this embodiment, as in the first embodiment, the doping of the source / drains 28 and 30 described in the step (5) in the first embodiment and the channel end insulation described in (6-1). Any order of introduction of impurities into the region 24 and doping of the body terminal 32 described in (6-2) may be performed first.

  The characteristics of the thin film transistor 7 formed according to the present embodiment can control the substrate potential as in the first embodiment, eliminate the “kump” of the gate voltage-drain current characteristic, and improve the source-drain breakdown voltage. Confirmed to do.

  The present invention can also be achieved by the following semiconductor device manufacturing method.

  A method of manufacturing a semiconductor device according to a first aspect includes a step of patterning a semiconductor film formed on one surface side of a substrate to form an element region of a first conductivity type, and forming a gate insulating film on the element region A step of forming a gate electrode on the gate insulating film so as to cover a part of the element region, and a low-concentration diffusion region of a second conductivity type in the element region adjacent to the outside of the gate electrode. Forming a high-concentration diffusion region of a second conductivity type in the element region adjacent to the outside of the low-concentration diffusion region; and the element region outside the gate electrode, Forming a first conductivity type body terminal in a region different from the concentration diffusion region and the high concentration diffusion region; and an end portion of the element region covered with the gate electrode, the low concentration diffusion region and the body Part that contacts the terminal Characterized by comprising the step of adding an impurity of the first conductivity type in a region excluding.

  A method of manufacturing a semiconductor device according to a second aspect includes a step of patterning a semiconductor film formed on one surface side of a substrate to form a first element region of a first conductivity type, and a step on the first element region. Forming a first gate insulating film on the first gate insulating film; forming a first gate electrode on the first gate insulating film so as to cover a part of the first element region; and Forming a first high-concentration diffusion region of a second conductivity type in the first element region adjacent to the outside of the electrode; and the first element region outside the first gate electrode, A step of forming a first body terminal of a first conductivity type in a region different from the first high-concentration diffusion region, and an end of the first element region covered with the first gate electrode The first high-concentration diffusion region and the region excluding the portion in contact with the body terminal are first Adding a conductivity type impurity to form a first semiconductor element; patterning the semiconductor film to form a second conductivity type second element region; and the second element region. Forming a second gate insulating film thereon; forming a second gate electrode on the second gate insulating film so as to cover a part of the second element region; and Forming a second high-concentration diffusion region of the first conductivity type in the second element region adjacent to the outside of the gate electrode; and the second element region outside of the second gate electrode. Forming a second body terminal of a second conductivity type in a region different from the second high-concentration diffusion region, and an end of the second element region covered with the second gate electrode A region excluding the second high-concentration diffusion region and a portion in contact with the body terminal. Characterized by comprising the step of forming the second semiconductor element by adding an impurity having a second conductivity type.

  A method of manufacturing a semiconductor device according to a third aspect includes a step of patterning a semiconductor film formed on one surface side of a substrate to form a first element region of a first conductivity type, and a step on the first element region. Forming a first gate insulating film on the first gate insulating film; forming a first gate electrode on the first gate insulating film so as to cover a part of the first element region; and Forming a first low-concentration diffusion region of a second conductivity type in the first element region adjacent to the outside of the electrode; and in the first element region outside the first low-concentration diffusion region Forming a first high-concentration diffusion region of a second conductivity type, and the first element region outside the first gate electrode, the first low-concentration diffusion region and the high-concentration diffusion Forming a first body terminal of a first conductivity type in a region different from the region; An impurity having a first conductivity type is added to the end portion of the first element region covered with the gate electrode, except for the first low-concentration diffusion region and the region in contact with the body terminal. Forming a first semiconductor element, patterning the semiconductor film to form a second element region of a second conductivity type, and forming a second gate insulating film on the second element region A step of forming a second gate electrode on the second gate insulating film so as to cover a part of the second element region, and the second adjacent to the outside of the second gate electrode. Forming a second low-concentration diffusion region of the first conductivity type in the element region of the second conductive region, and forming a second second region of the first conductivity type in the second element region outside the second low-concentration diffusion region. A step of forming a high concentration diffusion region; and the second element outside the second gate electrode. Forming a second body terminal of a second conductivity type in a region different from the second low-concentration diffusion region and the high-concentration diffusion region, and the step of covering the second gate electrode A second semiconductor element is formed by adding an impurity having the second conductivity type to an end portion of the second element region, excluding the second low concentration diffusion region and a region in contact with the body terminal. And a process.

  In the method of manufacturing a semiconductor device according to the third aspect, the impurity concentration of the channel end region of the first semiconductor element is substantially equal to the impurity concentration of the low-concentration diffusion region of the second semiconductor element. The impurity concentration of the channel end region of the semiconductor element may be substantially equal to the impurity concentration of the low concentration diffusion region of the first semiconductor element.

  In the method of manufacturing a semiconductor device according to the second and third aspects, the impurity concentration of the channel end region of the first semiconductor element is substantially equal to the impurity concentration of the high concentration diffusion region of the second semiconductor element. The impurity concentration of the channel end region of the second semiconductor element may be substantially equal to the impurity concentration of the high concentration diffusion region of the first semiconductor element.

  As described above, according to various embodiments of the present invention, the substrate potential of a thin film transistor can be controlled, and the entire channel region is substantially partially depleted regardless of the size of the taper angle at the end of the channel region. Thus, a thin film transistor having improved characteristics such as a variation in characteristics caused by mixing a fully depleted type and a partially depleted type, and a breakdown voltage can be obtained.

  The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily realized by those skilled in the art. The general principles defined herein may then be applied to other embodiments without departing from the spirit or scope of the present invention. As such, the present invention is not intended to be limited to the embodiments shown herein, but is to be applied in a wide range consistent with the principles and outstanding features disclosed herein. .

  The present invention can be used for a semiconductor device using a thin film transistor used in a liquid crystal display device, an organic electroluminescence display device, or the like, and also uses, for example, an SOI (silicon on insulator) substrate in which a semiconductor layer is formed above an insulating substrate. It can also be used for conventional semiconductor devices.

It is a figure for demonstrating an example of the thin-film transistor of the 1st Embodiment of this invention. 1A is a plan view, and FIG. 1B is a cross-sectional view in the channel width direction indicated by a cutting line 1B-1B in FIG. FIG. 2 is a process cross-sectional view for explaining an example of the manufacturing method of the thin film transistor of the first embodiment. 2A is a cross-sectional view in the channel length direction indicated by the section line 2A-2A in FIG. 1A, and FIG. 2B is illustrated by the section line 1B-1B in FIG. It is sectional drawing of the channel width direction. FIG. 3 is a process cross-sectional view for explaining the thin film transistor manufacturing method according to the first embodiment following FIG. 2. 3A is a cross-sectional view in the channel length direction indicated by the cutting line 2A-2A in FIG. 1A, and FIG. 3B is illustrated by the cutting line 1B-1B in FIG. It is sectional drawing of the channel width direction. FIG. 4 is a process cross-sectional view for explaining the manufacturing method of the thin film transistor according to the first embodiment following FIG. 3. 4A is a cross-sectional view in the channel length direction indicated by the section line 2A-2A in FIG. 1A, and FIG. 4B is illustrated by the section line 1B-1B in FIG. It is sectional drawing of the channel width direction. FIG. 5 is a process cross-sectional view for explaining the thin film transistor manufacturing method according to the first embodiment following FIG. 4. FIG. 5A is a cross-sectional view in the channel length direction indicated by the section line 2A-2A in FIG. 1A, and FIG. 5B is illustrated by the section line 1B-1B in FIG. It is sectional drawing of the channel width direction. FIG. 6 is a process cross-sectional view for explaining the thin film transistor manufacturing method according to the first embodiment following FIG. 5. 6A is a cross-sectional view in the channel length direction indicated by the section line 2A-2A in FIG. 1A, and FIG. 6B is illustrated by the section line 1B-1B in FIG. It is sectional drawing of the channel width direction. FIG. 7 is a process cross-sectional view for explaining the manufacturing method of the thin film transistor of the first embodiment following FIG. FIG. 7A is a cross-sectional view in the channel length direction indicated by the section line 2A-2A in FIG. 1A, and FIG. 7B is illustrated by the section line 1B-1B in FIG. It is sectional drawing of the channel width direction. It is a figure which shows an example of the drain current-gate voltage characteristic of the thin-film transistor of 1st Embodiment. FIG. 9 is a diagram for explaining an example of a thin film transistor according to a modification of the first embodiment. FIG. 9A is a plan view, FIG. 9B is a cross-sectional view in the channel width direction indicated by the section line 9B-9B in FIG. 9A, and FIG. It is sectional drawing of the channel length direction shown by the cutting line 9C-9C in 9 (a). It is a figure which shows an example of the drain current-gate voltage characteristic of the thin-film transistor of the modification of 1st Embodiment. FIG. 11 is a diagram for explaining an example of the thin film transistor of the second embodiment. 11A is a plan view, and FIG. 11B is a cross-sectional view in the channel width direction indicated by a cutting line 11B-11B in FIG. 11A. It is a figure for demonstrating the conventional thin-film transistor. 12A is a perspective view, and FIG. 12B is a cross-sectional view in the channel width direction indicated by the section line 12B-12B in FIG. 12A. It is a figure which shows an example of the drain current-gate voltage characteristic of the conventional thin-film transistor. It is a figure which shows the relationship between the body impurity concentration in a thin-film transistor, and the maximum depletion layer width.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor substrate, 10 ... Support substrate, 12 ... Base insulating film, 14 ... Semiconductor layer, 16 ... Cap insulating film, 18 ... Channel region, 20 ... Tapered part, 22 ... Channel end region, 24 ... Channel end insulating region, 26 ... LDD, 28 ... source, 30 ... drain, 32 ... body terminal, 34 ... gate insulating film, 36 ... gate electrode, 38 ... side wall insulating film, 40 ... mask.

Claims (11)

A semiconductor layer provided on one side of the substrate;
A channel region of a first conductivity type provided in the semiconductor layer;
A high-concentration diffusion region of a second conductivity type adjacent to the channel region and facing the both sides of the channel region and spaced apart from the semiconductor layer;
A body terminal of a first conductivity type connected to the channel region and fixing the potential of the channel region;
An insulating film provided on the channel region;
A gate electrode provided on the insulating film so as to cover the channel region;
A semiconductor device comprising: an end portion of the channel region, and a channel end region to which an impurity of a first conductivity type is provided provided at an end portion of the semiconductor layer. A semiconductor layer provided on one side of the substrate;
A channel region of a first conductivity type provided in the semiconductor layer;
A low-concentration diffusion region of a second conductivity type adjacent to the channel region and facing the both sides of the channel region and spaced apart from the semiconductor layer;
A high-concentration diffusion region of a second conductivity type provided in the semiconductor layer outside each of the low-concentration diffusion regions;
A body terminal of a first conductivity type connected to the channel region and fixing the potential of the channel region;
An insulating film provided on the channel region;
A gate electrode provided on the insulating film so as to cover the channel region;
A semiconductor device comprising: an end portion of the channel region, and a channel end region to which an impurity of a first conductivity type is provided provided at an end portion of the semiconductor layer.   The semiconductor device according to claim 1, wherein an impurity concentration of the channel end region is 10 times or more of an impurity concentration of the channel region. A semiconductor layer provided on one side of the substrate;
A semiconductor device including first and second semiconductor elements provided in the semiconductor layer,
The first semiconductor element is:
A first channel region of a first conductivity type provided in the semiconductor layer;
A first high-concentration diffusion region of a second conductivity type adjacent to the first channel region and facing the both sides of the first channel region and spaced apart from the semiconductor layer;
A first body terminal of a first conductivity type connected to the first channel region and fixing a potential of the first channel region;
A first insulating film provided on the first channel region;
A first gate electrode provided on the first insulating film so as to cover the first channel region;
An end portion of the first channel region, and a first channel end region doped with an impurity of a first conductivity type provided at an end portion of the semiconductor layer,
The second semiconductor element is:
A second channel region of a second conductivity type provided in the semiconductor layer;
A second high-concentration diffusion region of a first conductivity type adjacent to the second channel region and facing the both sides of the second channel region and spaced apart from the semiconductor layer;
A second body terminal of a second conductivity type provided in the semiconductor layer connected to the second channel region and fixing the potential of the second channel region;
A second insulating film provided on the second channel region;
A second gate electrode provided on the second insulating film so as to cover the second channel region;
A semiconductor device comprising: an end portion of the second channel region, and a second channel end region to which an impurity of a second conductivity type is provided provided at an end portion of the semiconductor layer. . A semiconductor layer provided on one side of the substrate;
A semiconductor device including first and second semiconductor elements provided in the semiconductor layer,
The first semiconductor element is:
A first channel region of a first conductivity type provided in the semiconductor layer;
A first low-concentration diffusion region of a second conductivity type adjacent to the first channel region and facing the both sides of the first channel region and spaced apart from the semiconductor layer;
A first high concentration diffusion region of a second conductivity type provided in the semiconductor layer outside the first low concentration diffusion region;
A first body terminal of a first conductivity type provided in the semiconductor layer connected to the first channel region and fixing the potential of the first channel region;
A first insulating film provided on the first channel region;
A first gate electrode provided on the first insulating film and covering the first channel region;
An end portion of the first channel region, and a first channel end region doped with an impurity of a first conductivity type provided at an end portion of the semiconductor layer,
The second semiconductor element is:
A second channel region of a second conductivity type provided in the semiconductor layer;
A second low-concentration diffusion region of the first conductivity type provided adjacent to the second channel region and facing the both sides of the second channel region and spaced apart from the semiconductor layer;
A second high concentration diffusion region of a first conductivity type provided in the semiconductor layer outside the second low concentration diffusion region;
A second body terminal of a second conductivity type provided in the semiconductor layer connected to the second channel region and fixing the potential of the second channel region;
A second insulating film provided on the second channel region;
A second gate electrode provided on the second insulating film so as to cover the second channel region;
A semiconductor device comprising: an end portion of the second channel region, and a second channel end region to which an impurity of the second conductivity type is provided provided at an end portion of the semiconductor layer. . The impurity concentration of the channel end region of the first semiconductor element is substantially equal to the impurity concentration of the low concentration diffusion region of the second semiconductor element,
6. The semiconductor device according to claim 5, wherein the impurity concentration of the channel end region of the second semiconductor element is substantially equal to the impurity concentration of the low concentration diffusion region of the first semiconductor element. The impurity concentration of the channel end region of the first semiconductor element is substantially equal to the impurity concentration of the high concentration diffusion region of the second semiconductor element,
6. The semiconductor device according to claim 4, wherein an impurity concentration of a channel end region of the second semiconductor element is substantially equal to an impurity concentration of a high concentration diffusion region of the first semiconductor element. A semiconductor layer provided on one side of the substrate;
A channel region of a first conductivity type provided in the semiconductor layer;
A high-concentration diffusion region of a second conductivity type adjacent to the channel region and facing the both sides of the channel region and spaced apart from the semiconductor layer;
A body terminal of a first conductivity type provided in the semiconductor layer connected to the channel region and fixing the potential of the channel region;
An insulating film provided on the channel region;
A gate electrode provided on the insulating film so as to cover the channel region;
A semiconductor device comprising: an end portion of the channel region, and a substantially insulating channel end region provided at an end portion of the semiconductor layer. A semiconductor layer provided on one side of the substrate;
A channel region of a first conductivity type provided in the semiconductor layer;
A low-concentration diffusion region of a second conductivity type adjacent to the channel region and facing the both sides of the channel region and spaced apart from the semiconductor layer;
A high-concentration diffusion region of a second conductivity type provided in the semiconductor layer outside the low-concentration diffusion region;
A body terminal of a first conductivity type provided in the semiconductor layer connected to the channel region and fixing the potential of the channel region;
An insulating film provided on the channel region;
A gate electrode provided on the insulating film so as to cover the channel region;
A semiconductor device comprising: an end portion of the channel region, and a substantially insulating channel end region provided at an end portion of the semiconductor layer.   10. The semiconductor device according to claim 1, wherein the semiconductor device is a partially depleted semiconductor device. Patterning a semiconductor film formed on one side of the substrate to form a first conductivity type element region;
Forming a gate insulating film on the element region;
Forming a gate electrode on the gate insulating film so as to cover a part of the element region;
Forming a high-concentration diffusion region of a second conductivity type in the element region adjacent to the outside of the gate electrode;
Forming a body terminal of a first conductivity type in a region different from the high concentration diffusion region in the element region outside the gate electrode;
Adding an impurity having a first conductivity type to an end portion of the element region covered with the gate electrode and excluding a portion in contact with the high concentration diffusion region and the body terminal. A method of manufacturing a semiconductor device.

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