JP2006048467A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having an internal circuit for which the supply of clock signals is stopped during operation in a power-saving mode, the semiconductor integrated circuit eliminating the need to take additional measures against power ripples when incorporated into an information processor. <P>SOLUTION: The semiconductor integrated circuit, having the internal circuit for which the supply of clock signals is stopped during operation in the power-saving mode, has the internal circuit divided into a plurality of blocks, and is equipped with an operational mode control module that, when the semiconductor integrated circuit is instructed to operate for recovery from the power-saving mode to the normal mode, starts the supply of clock signals (CLOCK-A, -B, -C) to the blocks forming the internal circuit, thereby implementing a recovery process for creating a state in which the clock signals are supplied to all of the plurality of blocks. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit having an internal circuit in which supply of a clock signal is stopped during operation in a power saving mode.

  Among existing information processing apparatuses, there are an apparatus in which the CPU operates even in the power saving mode, and an apparatus in which the CPU itself operates in the power saving mode in the power saving mode (see, for example, Patent Document 1). Yes. In the CPU used in the latter type of information processing apparatus, the supply of the clock signal to the internal circuit (the circuit that performs the actual processing) is stopped during the operation in the power saving mode. .

  Specifically, a CPU (hereinafter referred to as a CPU capable of stopping clock supply) used in the latter type of information processing apparatus has a configuration as schematically shown in FIG. That is, the CPU capable of stopping the clock supply includes a clock supply buffer 50 capable of turning on / off the supply of the clock signal (CLOCK) to the internal circuit 52, and a clock enable signal (/ CLKEN) to the clock supply buffer 50. ) To be output when a WAIT instruction (command for instructing start of operation in the power saving mode) / interrupt signal (signal for instructing start of operation in the normal mode) is input. The circuit includes an operation mode control module 51 that changes the level of the enable signal.

  By using this CPU capable of stopping the clock supply, it is possible to realize (manufacture) an information processing apparatus with extremely low power consumption in the power saving mode. However, the CPU capable of stopping the clock supply requires an additional countermeasure against power supply ripple as compared with the CPU not stopping the clock when the information processing apparatus using the CPU is operated. As an additional power supply ripple countermeasure, it is necessary to provide a circuit element (such as a low ESR capacitor) for power supply ripple on the power supply line of the CPU capable of stopping the clock supply. The manufacturing cost of the information processing device has risen by the amount of additional power supply ripple countermeasures.

Note that it is necessary to take additional power supply ripple countermeasures when operating an information processing device using a CPU that can stop clock supply, compared to the usual power supply ripple countermeasures (such as decaps) for CPUs that have not stopped clocks. Since the CPU that can supply clocks to a large number of circuit elements (such as latches) constituting the internal circuit is started at the same time when shifting from the power-saving mode to the normal mode, In an information processing apparatus that is simply used (without taking measures against power supply ripple), a large fluctuation occurs in the voltage of the power supply line of the CPU capable of stopping clock supply when shifting from the power saving mode to the normal mode. As a result, an information processing device that may not normally shift from the power saving mode to the normal mode is obtained. It is.
JP 2000-326590 A

  Therefore, an object of the present invention is a semiconductor integrated circuit having an internal circuit in which the supply of a clock signal is stopped when operating in a power saving mode, and an additional power supply ripple countermeasure is taken when incorporated in an information processing device The object is to provide a semiconductor integrated circuit which is not necessary.

  In order to solve the above problems, in the present invention, a semiconductor integrated circuit having an internal circuit in which the supply of a clock signal is stopped when operating in a power saving mode, the internal circuit is divided into a plurality of blocks, When a return operation from the power saving mode to the normal mode is instructed, the clock signal is supplied to all of the plurality of blocks by sequentially starting the supply of the clock signal to each block constituting the internal circuit. An operation mode control module that performs a return process for forming a state is provided.

  That is, the semiconductor integrated circuit of the present invention has a circuit configuration in which clock supply to a large number of circuit elements constituting the internal circuit is not started simultaneously. Therefore, this semiconductor integrated circuit is a semiconductor integrated circuit that does not cause a large fluctuation in the voltage of the power supply line when shifting from the power saving mode to the normal mode. It functions as a semiconductor integrated circuit that does not need to be performed.

  When the semiconductor integrated circuit of the present invention is realized, the return process performed by the operation mode control module may be a process that ends within a time shorter than one clock cycle, and each block is shifted by one clock. Alternatively, the process of starting the supply of the clock signal may be performed. Further, after one clock is supplied to each block, a process of forming a state in which clocks are supplied to all of the plurality of blocks may be performed.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

<First Embodiment>
As schematically shown in FIG. 1, the semiconductor integrated circuit according to the first embodiment of the present invention includes a clock supply buffer 10 to which a clock signal (CLOCK) supplied to the semiconductor integrated circuit is input, The operation mode control module 11 supplying the clock enable signal (/ CLKEN) to the clock supply buffer 10, the delay buffer 12B to which the output of the clock supply buffer 10 is input, and the output of the delay buffer 12B are input. The delay buffer 12C, the clock supply buffer 10, the delay buffer 12B, and the output of the delay buffer 12C are respectively sent to the blocks A, B, and C as clock signals (CLOCK-A, -B, -C). It is a circuit (ASIC) provided with the input internal circuit 15.

  Each of the two delay buffers 12B and 12C included in the semiconductor integrated circuit is an element that delays an input signal by a predetermined time (several tens to hundreds of one clock cycle; details will be described later) and outputs the delayed signal. is there. The clock supply buffer 10 and the operation control module 11 are the same as the clock supply buffer 50 and the operation mode control module 51 provided in the existing CPU (see FIG. 7), respectively. The blocks A to C are blocks (a set of circuit elements) obtained by dividing (dividing) the circuit element group constituting the internal circuit 15.

  That is, in the semiconductor integrated circuit according to the present embodiment, when an interrupt signal is input (when shifting from the power saving mode to the normal mode), as schematically shown in FIG. In the order of block C, the supply of the clock signal is started.

  Since this semiconductor integrated circuit is such a circuit that operates, when the power saving mode is shifted to the normal mode, a clock signal begins to be supplied to all the elements constituting the internal circuit 15 simultaneously. It functions as a circuit that does not cause such a phenomenon (a phenomenon that causes fluctuations in the power supply voltage). Therefore, if this semiconductor integrated circuit is used, the information processing apparatus can be designed and manufactured without the need for additional power supply ripple countermeasures. As a result, if this semiconductor integrated circuit is used, the information processing apparatus can be manufactured at low cost.

  If the phase shift of CLOCK-A to CLOCK-C becomes excessively large, the internal circuit 15 does not operate normally. Therefore, the semiconductor integrated circuit according to the present embodiment has internal delay buffers 12B and 12C as internal delay buffers 12B and 12C. The circuit 15 employs a circuit that operates normally.

Second Embodiment
FIG. 3 shows a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. As shown in the figure, the semiconductor integrated circuit according to the second embodiment of the present invention is also divided into three blocks A to C as in the semiconductor integrated circuit according to the first embodiment (see FIG. 1). This is a circuit (ASIC) having an internal circuit 25. The semiconductor integrated circuit according to the second embodiment includes an operation mode control module 21 having the same function as the operation mode control module 11.

  However, the semiconductor integrated circuit according to the second embodiment is a circuit in which a clock supply buffer 20X (X = A, B, C) is provided for each block constituting the internal circuit 25. In the semiconductor integrated circuit according to the second embodiment, / CLKEN-A and / CLKEN which are the same signals as / CLKEN output from the operation mode control module 21 are signals delayed by one clock cycle. , / CLKEN is also provided with a shift register 22 for supplying / CLKEN-C, which is a signal delayed by two clock cycles, to the clock supply buffers 20A, 20B, and 20C, respectively.

  That is, in the semiconductor integrated circuit according to the second embodiment, when an interrupt signal is input (when shifting from the power saving mode to the normal mode), as shown schematically in FIG. The clock signal supply is started in the order of B and block C, and the clock signal supply timing to each block is shifted by one clock cycle.

  For this reason, this semiconductor integrated circuit also functions as a circuit that does not cause a phenomenon that a clock signal starts to be supplied to all the elements constituting the internal circuit 25 simultaneously (a phenomenon that causes fluctuations in the power supply voltage). . Therefore, even if the semiconductor integrated circuit according to the second embodiment is used, the information processing apparatus can be designed and manufactured without the need for additional power supply ripple countermeasures during the return operation. As a result, the information processing apparatus can be manufactured at low cost.

<Third Embodiment>
FIG. 5 shows a configuration of a semiconductor integrated circuit according to the third embodiment of the present invention. As apparent from a comparison between FIG. 5 and FIG. 3, the semiconductor integrated circuit according to the third embodiment of the present invention includes the operation mode control module 21, the shift register 22, and the semiconductor integrated circuit according to the second embodiment. Is replaced with the operation mode control module 31.

  The operation mode control module 31 used in the semiconductor integrated circuit according to the third embodiment outputs signals that change as shown in FIG. 6 as / CLKEN-A, / CLKEN-B, and / CLKEN-C. Circuit. That is, when the interrupt signal is input, the operation mode control module 31 supplies the clock signals to all the blocks A to C after being supplied to the blocks A to C one clock at a time. This is a circuit that performs processing for controlling the buffers 20A to 20C.

  For this reason, this semiconductor integrated circuit also functions as a circuit in which the phenomenon that the clock signal starts to be supplied simultaneously to all the elements constituting the internal circuit 25 does not occur. Therefore, even when the semiconductor integrated circuit according to the third embodiment is used, the information processing apparatus can be designed and manufactured without the need for additional power supply ripple countermeasures. The device can be manufactured at low cost.

<Deformation>
The semiconductor integrated circuit according to each of the above embodiments can be variously modified. For example, the semiconductor integrated circuit according to each embodiment can be modified into one in which the internal circuits 15 and 25 are divided into two blocks or four or more blocks. Further, by adding a circuit for masking the outputs of the clock supply buffers 20A to 20C for a certain period of time to the semiconductor integrated circuit according to the second embodiment (FIG. 3), it is the same as the semiconductor integrated circuit according to the third embodiment. A semiconductor integrated circuit that operates may be realized.

1 is a schematic configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. The figure for demonstrating the operation | movement content at the time of mode transition of the semiconductor integrated circuit which concerns on 1st Embodiment. The schematic block diagram of the semiconductor integrated circuit which concerns on 2nd Embodiment of this invention. The figure for demonstrating the operation | movement content at the time of mode transition of the semiconductor integrated circuit which concerns on 2nd Embodiment. The schematic block diagram of the semiconductor integrated circuit which concerns on 3rd Embodiment of this invention. The figure for demonstrating the operation | movement content at the time of mode transition of the semiconductor integrated circuit which concerns on 3rd Embodiment. The schematic block diagram of the existing CPU which has an internal circuit by which supply of a clock signal is stopped at the time of operation | movement in a power saving mode.

Explanation of symbols

10, 20A, 20B, 20C Clock supply buffer 12B, 12C Delay buffer, 11, 21, 31 Operation mode control module 15, 25 Internal circuit, 22 Shift register

Claims (4)

A semiconductor integrated circuit having an internal circuit in which supply of a clock signal is stopped when operating in a power saving mode,
The internal circuit is divided into a plurality of blocks;
When a return operation from the power saving mode to the normal mode is instructed, the clock signal is supplied to all of the plurality of blocks by sequentially starting the supply of the clock signal to each block constituting the internal circuit. A semiconductor integrated circuit, comprising: an operation mode control module that performs a return process for forming a closed state. The semiconductor integrated circuit according to claim 1, wherein the return process performed by the operation mode control module is a process that ends within a time shorter than one clock cycle. The semiconductor integrated circuit according to claim 1, wherein the return process performed by the operation mode control module is a process of starting supply of a clock signal to each block with a shift of one clock. The return process performed by the operation mode control module is a process of forming a state in which a clock is supplied to all of the plurality of blocks after one clock is supplied to each block. The semiconductor integrated circuit as described.