JP4463115B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a regulator, and more particularly to a semiconductor device that avoids a malfunction due to a decrease in operating voltage accompanying an increase in power consumption.

  The semiconductor device performs an operation based on the timing of the operation clock. Therefore, the operation speed and power consumption can be made variable by switching the operation clock frequency. Therefore, semiconductor devices used for various purposes are provided with a function of switching an operation clock frequency so that an operation speed and power consumption corresponding to the situation can be obtained.

  For the same purpose, there is also a semiconductor device having a function of switching operating voltage. In such a semiconductor device, a regulator that converts power supplied from the outside into a predetermined voltage and has a function of switching an operating voltage. For example, Patent Document 1 discloses a regulator that can cope with two modes of a low voltage / low power consumption mode and a high voltage / high speed operation mode.

  Further, in order for the semiconductor device to execute processing normally, the operating voltage must be within a predetermined range. In particular, when the operating voltage decreases, the semiconductor device malfunctions. Therefore, a technique for avoiding malfunction of the semiconductor device due to voltage fluctuation of the external power source has been developed.

  Patent Document 2 discloses a circuit configuration that can prevent an influence on a reference voltage of an internal circuit of a semiconductor device even when a state change occurs in an external circuit connected to the semiconductor device.

  Patent Document 3 discloses a semiconductor device that detects a voltage of an external power supply and reduces a clock frequency to expand a stable operation guarantee range and avoid a malfunction when the voltage falls below a predetermined voltage value.

By the way, the semiconductor device is inspected using a test pattern that describes a predetermined input value for each clock cycle and an output value corresponding to the input value. In this test pattern, test instructions can be freely described.
JP-A-10-150152 Japanese Patent Application Laid-Open No. 07-22584 JP-A-61-138356

  In the semiconductor device having the operation clock frequency switching function as described above, since the frequency switching is often realized by changing the frequency division ratio, the frequency is stepwise such as 2, 4 or 8 times. Switching. Therefore, as the operation clock frequency rapidly increases, the power consumption in the semiconductor device increases rapidly.

  On the other hand, the regulator tries to maintain a predetermined operating voltage regardless of fluctuations in power consumption. However, if the increase speed of power consumption is faster than the response speed of the regulator, the power supply temporarily becomes insufficient and the operating voltage decreases. . Therefore, there is a problem that the semiconductor device malfunctions when the operation clock frequency is switched.

  The regulator disclosed in Patent Document 1 switches the operation voltage so as to be compatible with two modes, and cannot cope with a decrease in the operation voltage accompanying a rapid increase in the clock frequency.

  The semiconductor devices disclosed in Patent Documents 2 and 3 are for the purpose of avoiding malfunction due to a voltage drop of a power supply supplied from the outside, and are caused by a voltage drop accompanying an increase in power consumption in the semiconductor device. A malfunction could not be avoided.

  Furthermore, in the inspection of the semiconductor device, when a test pattern in which a test instruction that is not executed in an actual program is used is used, the operating clock frequency increases rapidly, although it is a non-defective product. There was also a problem that it was judged as a defective product.

  Therefore, the present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device capable of avoiding a malfunction due to a decrease in operating voltage accompanying a rapid increase in clock frequency.

  According to the present invention, a CPU unit that operates based on an operation clock received from the outside, a peripheral function circuit that operates in response to a command from the CPU unit, a determination unit that determines the frequency of the operation clock, and power from the outside And a regulator that converts the voltage into a predetermined operating voltage and supplies the converted voltage to the CPU unit and the peripheral function circuit. When the frequency of the operation clock rapidly increases, the determination unit continues to output a warning signal to the CPU unit for a predetermined period during which the regulator stabilizes the supply voltage. When receiving the warning signal, the CPU unit interrupts execution of the program, and when the warning signal ends, resumes execution of the interrupted program.

  According to the present invention, when the determination unit detects a sudden increase in the operation clock, the determination unit predicts a decrease in the operation voltage due to the accompanying rapid increase in power consumption, and causes the CPU unit to interrupt execution of the program. Then, the determination unit causes the CPU unit to resume execution of the program after a lapse of a predetermined period in which the regulator stabilizes the supply voltage. Therefore, even if the operating voltage is lowered, the program is not executed, so that no malfunction occurs. Therefore, it is possible to realize a semiconductor device that avoids malfunction due to a decrease in operating voltage accompanying a rapid increase in clock frequency.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that the same or corresponding parts in the drawings are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a schematic configuration diagram of a semiconductor device 100 according to the first embodiment of the present invention.

  Referring to FIG. 1, a semiconductor device 100 receives a pulse signal having a predetermined frequency from an oscillator 2 composed of a crystal oscillator or a function generator. In addition, the semiconductor device 100 receives power from an external power source. The semiconductor device 100 includes a clock generation unit 4, a CPU unit 6, a peripheral function circuit 8, a determination unit 10, and a regulator 12.

  The clock generation unit 4 converts the pulse signal received from the external oscillator 2 into an operation clock having a predetermined frequency and outputs it to the determination unit 10 and the CPU unit 6. The clock generation unit 4 receives the mode switching command from the CPU unit 6 and changes the frequency of the operation clock. Note that a mode switching command may be given to the oscillator 2 to change the frequency of the pulse signal output to the clock generator 4.

  The determination unit 10 receives the operation clock from the clock generation unit 4 and detects whether the frequency of the operation clock is “high frequency region”, “intermediate frequency region”, or “low frequency region”. The “high frequency region”, “intermediate frequency region”, and “low frequency region” are determined according to the design specifications of the semiconductor device. When the operation clock changes from the “low frequency region” to the “high frequency region”, the determination unit 10 continues to output a warning signal to the CPU unit 6 for a predetermined period thereafter. Note that the detection is not limited to the three regions of “high frequency region”, “intermediate frequency region”, and “low frequency region”, and may be configured to detect the region in more detail.

  Moreover, the determination part 10 is realizable by the structure which accumulate | stores an operation clock in a capacitor and detects the voltage value of a capacitor, for example. That is, if the frequency of the operation clock is low, the amount of discharge is relatively large, so the voltage of the capacitor decreases. If the frequency of the operation clock is high, the amount of charge is relatively large, and the voltage of the capacitor increases. To do. Therefore, the frequency of the operation clock can be detected by comparing the voltage of the capacitor with a predetermined threshold value.

  The CPU unit 6 receives the operation clock from the clock generation unit 4 and executes the program at a speed corresponding to the operation clock. The CPU unit 6 includes a calculation unit 28 and a control unit 30.

  The calculation unit 28 executes a command based on a control command from the control unit 30. The calculation unit 28 includes a program counter register (PC) 32.

  The program counter register 32 stores a program counter for designating an instruction to be executed in the arithmetic unit 28. The program counter is counted up as instructions are executed.

  The control unit 30 gives an instruction command to the arithmetic unit 28 and gives an operation command to the peripheral function circuit 8 according to the program. Further, the control unit 30 gives a mode switching command to the clock generation unit 4 according to the program. The control unit 30 performs processing based on the timing of the operation clock received from the clock generation unit 4.

  Furthermore, the control unit 30 stops the count up of the program counter in the calculation unit 28 during the period when the warning signal is received from the determination unit 10. Then, when the warning signal from the determination unit 10 ends, the control unit 30 restarts the count up of the program counter in the calculation unit 28. Further, the control unit 30 gives a predetermined operation command to the peripheral function circuit 8 during a period in which the warning signal is received from the determination unit 10.

  The peripheral function circuit 8 operates in response to an operation command given from the control unit 30.

  The regulator 12 converts electric power received from the external power source into a predetermined voltage and supplies it to the CPU unit 6 and the peripheral function circuit 8 via the power source line.

  Since the control unit 30 performs processing based on the operation clock, when the frequency of the operation clock is increased, the update cycle of the program counter is shortened, and the number of instructions per unit time executed by the calculation unit 28 is increased. Therefore, the power consumed in the CPU unit 6 increases.

  Further, the cycle in which the control unit 30 gives the operation command to the peripheral function circuit 8 is also shortened. Therefore, the power consumed in the peripheral function circuit 8 also increases.

  On the other hand, the regulator 12 tries to maintain the supply voltage at the operating voltage regardless of the power consumption. That is, the regulator 12 forms a feedback loop that detects a voltage difference between the supply voltage and the operating voltage and adjusts the on-timing of the switching element according to the voltage difference. For this reason, when the power consumption increases rapidly and the supply voltage decreases, the regulator 12 operates to detect the voltage decrease and restore it to a predetermined operating voltage. However, the response time of the feedback loop and the time constant of the circuit Due to the above, an operation delay occurs. In addition, depending on the feedback loop, overshoot or the like may occur. Therefore, when a voltage drop occurs due to a rapid increase in power consumption, it takes time until the voltage stabilizes again. As described above, a period required for the regulator 12 to recover the voltage is referred to as a “recovery period”.

  When the voltage on the power supply line connected to the regulator 12 is lower than the operation guarantee minimum voltage, the control unit 30 and the calculation unit 28 constituting the CPU unit 6 malfunction.

  Therefore, when a voltage drop is expected to occur, the execution of the program in the CPU unit 6 is interrupted, and the malfunction is avoided by waiting until the supply voltage of the regulator 12 is stabilized.

  FIG. 2 is a diagram showing temporal operations in each part of the semiconductor device 100.

  Referring to FIG. 2, when clock generation unit 4 receives a mode switching command or when oscillator 2 receives a command from the outside, the operating clock frequency given from clock generation unit 4 to control unit 30 is It rises rapidly. Note that the rapid increase in the operation clock frequency occurs when shifting from the low speed mode to the high speed mode or when shifting from the sleep mode to the operation mode.

  The determination unit 10 determines which frequency domain of the operation clock is at the edge (rising timing) of the operation clock (current frequency domain). The determination unit 10 stores the frequency region (previous frequency region) determined one cycle before, the previous frequency region is “low frequency region”, and the current frequency region is “high frequency region”. In some cases, a warning signal is output to the CPU unit 6. Further, the determination unit 10 continues outputting the warning signal for a period sufficient for the regulator 12 to stabilize the supply voltage, that is, for a period longer than the recovery period. Note that the frequency region may be divided and detected, and a warning signal may be output when the region changes over two or more. Further, a warning signal may be output when the current frequency region is different from the previous frequency region.

  The control unit 30 receives the warning signal from the determination unit 10 and stops the count up of the program counter in the calculation unit 28. For this reason, since the arithmetic unit 28 does not execute the instruction, power consumption is suppressed. On the other hand, since the control unit 30 gives a predetermined operation command to the peripheral function circuit 8 while receiving the warning signal from the determination unit 10, the power consumption of the peripheral function circuit 8 depends on the frequency of the operation clock. Increase. Therefore, the voltage on the power supply line, that is, the supply voltage of the regulator 12 decreases instantaneously. Then, after the recovery period has elapsed, the regulator 12 recovers the voltage on the voltage line to a predetermined operating voltage.

  The determination unit 10 ends the output of the warning signal after a period sufficient for the regulator 12 to stabilize the supply voltage has elapsed. Then, in response to the end of the warning signal, the control unit 30 restarts the count up of the program counter in the calculation unit 28. Then, since the arithmetic unit 28 resumes execution of the instruction, the power consumption of the arithmetic unit 28 increases.

  However, since only the power consumption of the arithmetic unit 28 increases, the amount of increase is smaller than when the power consumption of the arithmetic unit 28 and the peripheral function circuit 8 increases simultaneously. Therefore, voltage drop on the power supply line can be suppressed as compared with the conventional case. Therefore, when the arithmetic unit 28 resumes execution of instructions, it is possible to avoid malfunction due to voltage drop on the power supply line.

  According to the first embodiment, when the operation clock frequency rapidly increases, the execution of the instruction in the arithmetic unit is interrupted, and the operation of the peripheral function circuit is continued. Therefore, even if the voltage on the power supply line decreases due to an increase in power consumption of the peripheral function circuit, the arithmetic unit does not malfunction. Furthermore, even if the arithmetic unit resumes executing instructions and the power consumption increases, the power consumption of the peripheral function circuit has already increased, so that fluctuations in overall power consumption can be suppressed. Therefore, the amount of voltage drop on the power supply line at the restart timing of the arithmetic unit can be reduced. Therefore, it is possible to realize a semiconductor device that avoids malfunction due to a rapid increase in the operation clock frequency.

  Further, according to the first embodiment, even when a test pattern in which a test instruction that is not executed in an actual program is used is used, malfunction can be avoided. Can be avoided, and the yield can be improved. Furthermore, since there is no restriction on the description content of the test pattern, the labor and time required for creating the test pattern can be reduced.

[Embodiment 2]
In the first embodiment described above, the case has been described in which the count of the program counter in the arithmetic unit is stopped and the execution of the program is interrupted.

  On the other hand, in the second embodiment, a case where a predetermined invalid instruction is executed in the arithmetic unit will be described.

  The configuration of the semiconductor device according to the second embodiment is similar to that of semiconductor device 100 shown in FIG. In the second embodiment, only operations of control unit 30 and arithmetic unit 28 are different from those of semiconductor device 100 according to the first embodiment, and will be described below.

  When the control unit 30 receives the warning signal from the determination unit 10, the control unit 30 gives an invalid mode transition command to the calculation unit 28. Then, when the warning signal from the determination unit 10 ends, the control unit 30 gives a normal mode transition command to the calculation unit 28. Further, the control unit 30 gives a predetermined operation command to the peripheral function circuit 8 during a period in which the warning signal is received from the determination unit 10.

  When the calculation unit 28 receives the invalid mode transition command from the control unit 30, the calculation unit 28 stops counting up the program counter and executes an invalid command without any output. This is a process similar to the no operation for invalidating the output of the instruction decoder. When the arithmetic unit 28 receives a normal mode transition command from the control unit 30, the arithmetic unit 28 resumes counting up the stopped program counter and executes a normal command.

  Since the invalid instruction is executed when the arithmetic unit 28 has shifted to the invalid mode, the power consumption of the arithmetic unit 28 increases according to the frequency of the operation clock. Therefore, the increase in overall power consumption can be further suppressed at the timing when the arithmetic unit 28 resumes the normal instruction.

  According to the second embodiment, when the operation clock frequency rapidly increases, execution of an instruction in the arithmetic unit is interrupted, and an invalid instruction that is not output at all is executed instead. For this reason, since power consumption exists even during a period in which the arithmetic unit suspends execution of the normal instruction, fluctuations in power consumption when the arithmetic unit resumes execution of the normal instruction can be suppressed. Therefore, it is possible to realize a semiconductor device that avoids malfunction due to a rapid increase in the operation clock frequency.

[Embodiment 3]
FIG. 3 is a schematic configuration diagram of a semiconductor device 200 according to the third embodiment.

  Referring to FIG. 3, a semiconductor device 200 is the same as the semiconductor device 100 shown in FIG.

  The power consumption unit 22 is connected to the regulator 12 via a power supply line, receives a warning signal from the determination unit 20, and consumes power supplied from the regulator 12. The power consumption unit 22 receives the operation clock from the clock generation unit 4 and consumes power proportional to the operation clock frequency.

  Moreover, the power consumption part 22 is realizable with the structure which connected the resistance and the capacitor in series, for example. Since the impedance of the capacitor is inversely proportional to the frequency, the overall impedance decreases in proportion to the operation clock frequency, and the power consumption increases.

  When receiving a warning signal from the determination unit 10, the control unit 30 interrupts its own processing. Therefore, when the control unit 30 interrupts the processing, the processing in the arithmetic unit 28 and the peripheral function circuit 8 is also interrupted. Then, when the warning signal from the determination unit 10 ends, the control unit 30 resumes its own processing.

  FIG. 4 is a diagram illustrating temporal operations in the respective units of the semiconductor device 200.

  Referring to FIG. 4, similarly to FIG. 2, when clock generation unit 4 receives a mode switching command or when oscillator 2 receives a command from the outside, clock generation unit 4 transfers to control unit 30. The applied operating clock frequency increases rapidly.

  The determination unit 10 outputs a warning signal to the CPU unit 6 when the previous frequency region is the “low frequency region” and the current frequency region is the “high frequency region”. Then, the determination unit 10 continues outputting the warning signal for a period sufficient for the regulator 12 to stabilize the supply voltage, that is, a period longer than the recovery period.

  The control unit 30 receives the warning signal from the determination unit 10 and stops its own processing. For this reason, the arithmetic unit 28 and the peripheral function circuit 8 do not execute processing, so that power is not consumed.

  On the other hand, the power consumption unit 22 receives a warning signal from the determination unit 10 and consumes power proportional to the operation clock frequency.

  By the way, since the CPU unit 6 and the peripheral function circuit 8 execute processing based on the timing of the operation clock, it can be considered that power proportional to the frequency of the operation clock is consumed. That is, the power consumption unit 22 consumes power corresponding to the power consumption instead of the CPU unit 6 and the peripheral function circuit 8.

  Therefore, the voltage on the power supply line instantaneously decreases as in the case where the power consumption of the CPU unit 6 and the peripheral function circuit 8 increases. Then, after the recovery period has elapsed, the voltage on the voltage line is recovered to the specified voltage.

  When the determination unit 10 finishes outputting the warning signal, the control unit 30 resumes its own processing, and the power consumption unit 22 ends the power consumption. Then, since the control unit 30 resumes its own processing, the arithmetic unit 28 and the peripheral function circuit 8 also resume processing. Therefore, power consumption of the CPU unit 6 and the peripheral function circuit 8 increases.

  However, since the power consumption unit 22 consumes power corresponding to the power consumption in the CPU unit 6 and the peripheral function circuit 8 until just before that, the amount of fluctuation of the overall power consumption is small.

  Therefore, at the timing when the control unit 30 resumes its own processing, a voltage drop on the power supply line does not occur, and a malfunction of the CPU unit 6 can be avoided.

  According to the third embodiment, when the operation clock frequency rapidly increases, the arithmetic unit stops its own processing, and instead, the power consumption unit consumes power corresponding to the power consumption in the CPU unit and the peripheral function circuit. Therefore, even if the voltage on the power supply line decreases, the CPU unit and the peripheral function circuit do not malfunction. Further, when the CPU unit and the peripheral function circuit resume processing and the power consumption increases, the power consumption unit ends the power consumption. Therefore, when the CPU unit and the peripheral function circuit resume processing, the amount of power consumption fluctuation with respect to the regulator can be suppressed, and the voltage drop on the power supply line does not occur. Therefore, it is possible to realize a semiconductor device that avoids malfunction due to an increase in the operating clock frequency.

[Embodiment 4]
FIG. 5 is a schematic configuration diagram of a semiconductor device 300 according to the fourth embodiment.

  Referring to FIG. 5, semiconductor device 300 is the same as semiconductor device 200 shown in FIG. 3, except that power consumption units 22.1, 22.2, 22.3 are provided instead of power consumption unit 22.

  The power consuming units 22.1, 22.2, 22.3 are connected to the regulator 12 through power lines, respectively, and supplied from the regulator 12 after a lapse of different time when receiving a warning signal from the determination unit 20. Consume power. That is, when a warning signal is received from the determination unit 20, power consumption starts in the order of the power consumption units 22.1, 22.2, and 22.3 as time elapses. The power consumption units 22.1, 22.2, and 22.3 each receive an operation clock from the clock generation unit 4 and consume power proportional to the frequency of the operation clock.

  FIG. 6 is a diagram illustrating a temporal operation in each part of the semiconductor device 300.

  Referring to FIG. 6, as in FIG. 2, when clock generation unit 4 receives a mode switching command or when oscillator 2 receives an external command, control unit 30 receives control signal from clock generation unit 4. The operating clock frequency applied to the abruptly increases.

  The determination unit 10 outputs a warning signal to the CPU unit 6 when the previous frequency region is the “low frequency region” and the current frequency region is the “high frequency region”. Then, the determination unit 10 continues outputting the warning signal for a period sufficient for the regulator 12 to stabilize the supply voltage, that is, a period longer than the recovery period.

  The control unit 30 receives the warning signal from the determination unit 10 and stops its own processing. For this reason, the arithmetic unit 28 and the peripheral function circuit 8 do not execute processing, so that power is not consumed.

  On the other hand, the power consumption unit 22.1 receives a warning signal from the determination unit 10 and consumes power proportional to the operation clock frequency. The power consumption unit 22.2 starts consuming power proportional to the operation clock frequency after a delay time Td after receiving the warning signal from the determination unit 10. Furthermore, the power consumption unit 22.3 starts to consume power proportional to the operation clock frequency after a delay time of 2 Td after receiving the warning signal from the determination unit 10.

  As described above, the power consuming units 22.1, 22.2, and 22.3 start consuming power at a constant time interval, and therefore, it is possible to mitigate the rapid increase in power consumption. Therefore, the amount of voltage drop on the power supply line can be suppressed, and the recovery period required for the voltage to recover to the predetermined operating voltage is shortened.

  When the determination unit 10 finishes outputting the warning signal, the control unit 30 resumes its own processing, and the power consumption units 22.1, 22.2, and 22.3 end the power consumption. Then, since the control unit 30 resumes its own processing, the arithmetic unit 28 and the peripheral function circuit 8 also resume processing. Therefore, the power consumption of the CPU unit 6 and the peripheral function circuit 8 increases.

  However, until just before that, the power consumption units 22.1, 22.2, 22.3 consume power corresponding to the power consumption in the CPU unit 6 and the peripheral function circuit 8. The increase is slight.

  Therefore, at the timing when the control unit 30 resumes its own processing, a voltage drop on the power supply line does not occur, and a malfunction of the CPU unit 6 can be avoided.

  In the above-described fourth embodiment, the case where the power consumption unit is composed of three power consumption units has been described. However, the number of power consumption units is not particularly limited, and is not stepwise and continuous. You may use the power consumption part which increases power consumption.

  According to the fourth embodiment, in addition to the effect in the third embodiment, since the rapid fluctuation of the power consumption in the power consumption unit can be alleviated, the voltage drop on the power supply line can be suppressed. Therefore, the recovery period until the voltage on the power supply line is recovered can be shortened. Therefore, the period during which the CPU unit and the peripheral function circuit unit are stopped can be shortened, and the influence of processing delay due to the stop can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic configuration diagram of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the time operation | movement in each part of a semiconductor device. FIG. 10 is a schematic configuration diagram of a semiconductor device according to a third embodiment. It is a figure which shows the time operation in each part of a semiconductor device. FIG. 10 is a schematic configuration diagram of a semiconductor device according to a fourth embodiment. It is a figure which shows the time operation in each part of a semiconductor device.

Explanation of symbols

  2 oscillator, 4 clock generation unit, 6 CPU unit, 8 peripheral function circuit, 10 determination unit, 12 regulator, 20 determination unit, 22 power consumption unit, 28 calculation unit, 30 control unit, 32 program counter register, 100, 200, 300 Semiconductor device, Td delay time.

Claims (5)

A CPU unit that operates based on an operation clock received from the outside;
A peripheral function circuit that operates in response to a command from the CPU;
A determination unit for determining a frequency of the operation clock;
A regulator that receives power from the outside, converts it into a predetermined operating voltage, and supplies it to the CPU unit and peripheral function circuit;
When the frequency of the operation clock increases rapidly, the determination unit continues to output a warning signal to the CPU unit for a predetermined period during which the regulator stabilizes the supply voltage.
The CPU unit suspends execution of a program upon receipt of the warning signal, and resumes execution of the suspended program upon completion of the warning signal.   2. The CPU according to claim 1, wherein the CPU unit executes an invalid instruction instead of the program during a period in which the execution of the program is interrupted, and suppresses fluctuations in power consumption when restarting the execution of the program. Semiconductor device.   A power consuming unit that consumes power instead of the CPU unit during a period in which the CPU unit suspends execution of the program and suppresses fluctuations in power consumption when the CPU unit resumes execution of the program The semiconductor device according to claim 1, further comprising:   The semiconductor device according to claim 3, wherein the power consuming unit consumes power proportional to a frequency of the operation clock.   5. The semiconductor according to claim 3, wherein the power consuming unit limits an increase rate of power consumption within a predetermined range, and suppresses fluctuations in power consumption when the power consuming unit starts consuming power. 6. apparatus.

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