JP2006045036A - Substrate for growing compound semiconductor and method for manufacturing the same - Google Patents

Substrate for growing compound semiconductor and method for manufacturing the same Download PDF

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JP2006045036A
JP2006045036A JP2004232148A JP2004232148A JP2006045036A JP 2006045036 A JP2006045036 A JP 2006045036A JP 2004232148 A JP2004232148 A JP 2004232148A JP 2004232148 A JP2004232148 A JP 2004232148A JP 2006045036 A JP2006045036 A JP 2006045036A
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single crystal
crystal layer
porous
compound semiconductor
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Jun Komiyama
純 小宮山
Yoshihisa Abe
芳久 阿部
Shunichi Suzuki
俊一 鈴木
Hideo Nakanishi
秀夫 中西
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Coorstek KK
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Toshiba Ceramics Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for growing a compound semiconductor, with which the compound semiconductor having a high quality can be obtained. <P>SOLUTION: A porous Si single crystal layer 4 is formed on an Si single crystal substrate 2. The porous Si single crystal layer 4 has holes opened toward the outside and a porosity of 10-90%, and the surface of the porous Si single crystal layer 4 is covered with a 3C-SiC single crystal layer 3 having a surface roughness of 0.1-100 nm and a thickness of 0.1-100 nm. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、化合物半導体、すなわち、短波長半導体発光素子、高周波及び高効率半導体素子等の製造に用いられる3C−SiC(立方晶炭化ケイ素)、GaN(窒化ガリウム)やAlN(窒化アルミニウム)等の単結晶膜の気相成長に使用される基板及びその製造方法に関する。   The present invention relates to 3C-SiC (cubic silicon carbide), GaN (gallium nitride), AlN (aluminum nitride), etc. used for the production of compound semiconductors, that is, short wavelength semiconductor light emitting devices, high frequency and high efficiency semiconductor devices, etc. The present invention relates to a substrate used for vapor phase growth of a single crystal film and a manufacturing method thereof.

従来、この種の化合物半導体成長用基板及びその製造方法としては、多孔質Si(シリコン、ケイ素)単結晶層を有するSi単結晶基板を、非酸化性雰囲気又は真空中で、多孔質Si単結晶層の融点以下の温度で熱処理することにより、多孔質Si単結晶層の表面に、非多孔質のSi単結晶層を形成する半導体基材の作製方法及びその方法により作製された半導体基材が知られている(特許文献1参照)。   Conventionally, as this kind of compound semiconductor growth substrate and its manufacturing method, a Si single crystal substrate having a porous Si (silicon, silicon) single crystal layer is formed by using a porous Si single crystal in a non-oxidizing atmosphere or in a vacuum. A semiconductor substrate manufacturing method for forming a non-porous Si single crystal layer on the surface of a porous Si single crystal layer by heat treatment at a temperature below the melting point of the layer, and a semiconductor substrate manufactured by the method It is known (see Patent Document 1).

ここで、多孔質Si単結晶は、ポーラスSiとも呼ばれ、まるでスポンジの如くSi単結晶に外方へ開孔した微細な多数の穴(直径数nmの孔)が含まれることが知られている。
多孔質Si単結晶層は、Si単結晶基板にその表面から数nm〜数μmの深さ、あるいはSi単結晶基板の厚さ方向全域に形成可能なことが知られており、たとえ厚さ方向全域に多孔質Si単結晶層を形成しても、多孔質Si単結晶層単体で基板として利用可能である。これらは、多孔質Si単結晶基板と呼ばれる。
Here, the porous Si single crystal is also called porous Si, and is known to contain a large number of fine holes (holes with a diameter of several nm) opened outward in the Si single crystal like a sponge. Yes.
It is known that the porous Si single crystal layer can be formed on the Si single crystal substrate at a depth of several nm to several μm from the surface thereof, or in the entire thickness direction of the Si single crystal substrate. Even if a porous Si single crystal layer is formed over the entire area, the porous Si single crystal layer alone can be used as a substrate. These are called porous Si single crystal substrates.

しかし、従来の化合物半導体成長用基板は、気相成長によって積層される半導体がSi単結晶基板と同種のSi単結晶膜の場合には不具合がないものの、Si単結晶基板と異種の化合物半導体単結晶膜の場合には格子不整合あるいは熱膨張係数差による応力に起因すると考えられる転位等の結晶欠陥を高密度で発生させ、実用に耐え得ない不具合がある。
特許第2901031号公報
However, the conventional compound semiconductor growth substrate has no problem when the semiconductor laminated by vapor phase growth is the same type of Si single crystal film as that of the Si single crystal substrate. In the case of a crystal film, crystal defects such as dislocations considered to be caused by lattice mismatch or stress due to a difference in thermal expansion coefficient are generated at a high density, and there is a problem that cannot be put into practical use.
Japanese Patent No. 291031

本発明は、化合物半導体を高品質なものとし得る化合物半導体成長用基板及びその製造方法の提供を課題とする。   It is an object of the present invention to provide a compound semiconductor growth substrate that can make a compound semiconductor of high quality and a method for manufacturing the same.

本発明の第1の化合物半導体成長用基板は、Si単結晶基板上に外方へ開孔し、かつ、多孔度が10〜90%で、表面が表面粗さ0.1〜100nm、厚さ0.1〜100nmの3C−SiC単結晶層によって被覆された多孔質Si単結晶層が形成されていることを特徴とする。   The first compound semiconductor growth substrate of the present invention opens outwardly on a Si single crystal substrate, has a porosity of 10 to 90%, a surface roughness of 0.1 to 100 nm, and a thickness. A porous Si single crystal layer covered with a 3C-SiC single crystal layer of 0.1 to 100 nm is formed.

第2の化合物半導体成長用基板は、Si単結晶基板上に外方へ開孔し、かつ、多孔度が10〜90%、表面粗さ0.1〜100nmの多孔質3C−SiC単結晶層が形成されていることを特徴とする。   The second compound semiconductor growth substrate is a porous 3C-SiC single crystal layer that opens outwardly on a Si single crystal substrate and has a porosity of 10 to 90% and a surface roughness of 0.1 to 100 nm. Is formed.

第3の化合物半導体成長用基板は、Si単結晶基板上に外方へ開孔し、かつ、多孔度が10〜90%の多孔質Si単結晶層、厚さ0.1〜5μmのSi単結晶層及び表面粗さ0.1〜100nm、厚さ0.1〜100nmの3C−SiC単結晶層が順に形成されていることを特徴とする。   The third compound semiconductor growth substrate has a porous Si single crystal layer having a porosity of 10 to 90% and a thickness of 0.1 to 5 μm. A crystal layer and a 3C—SiC single crystal layer having a surface roughness of 0.1 to 100 nm and a thickness of 0.1 to 100 nm are sequentially formed.

一方、第1の化合物半導体成長用基板の製造方法は、Si単結晶基板の上部を多孔質化して外方へ開孔し、かつ、多孔度が10〜90%の多孔質Si単結晶層を形成した後、多孔質Si単結晶層に炭素原料雰囲気において800〜1400℃の温度で熱処理を施して表面を表面粗さ0.1〜100nmに調製しつつ、多孔質Si単結晶層の表層部を表面から0.1〜100nmの深さに及んで炭化することを特徴とする。   On the other hand, in the first method for manufacturing a compound semiconductor growth substrate, the upper part of the Si single crystal substrate is made porous to open outward, and a porous Si single crystal layer having a porosity of 10 to 90% is formed. After the formation, the surface of the porous Si single crystal layer is prepared by subjecting the porous Si single crystal layer to a heat treatment at a temperature of 800 to 1400 ° C. in a carbon raw material atmosphere to adjust the surface to a surface roughness of 0.1 to 100 nm. Is carbonized over a depth of 0.1 to 100 nm from the surface.

第2の化合物半導体成長用基板の製造方法は、Si単結晶基板の上部を多孔質化して外方へ開孔し、かつ、多孔度が10〜90%の多孔質Si単結晶層を形成した後、多孔質Si単結晶層に炭素原料雰囲気において800〜1400℃の温度で熱処理を施して表面を表面粗さ0.1〜100nmに調製しつつ、多孔質Si単結晶層の全部を炭化することを特徴とする。   In the second method for manufacturing a compound semiconductor growth substrate, the upper portion of the Si single crystal substrate is made porous to open outward, and a porous Si single crystal layer having a porosity of 10 to 90% is formed. Thereafter, the porous Si single crystal layer is heat-treated in a carbon raw material atmosphere at a temperature of 800 to 1400 ° C. to adjust the surface to a surface roughness of 0.1 to 100 nm, and the entire porous Si single crystal layer is carbonized. It is characterized by that.

第3の化合物半導体成長用基板の製造方法は、Si単結晶基板の上部を多孔質化して外方へ開孔し、かつ、多孔度が10〜90%の多孔質Si単結晶層を形成した後、多孔質Si単結晶層上に気相成長により厚さ0.1〜5μmのSi単結晶層を積層し、しかる後に、Si単結晶層に炭素原料雰囲気において800〜1400℃の温度で熱処理を施して表面を表面粗さ0.1〜100nmに調製しつつ、Si単結晶層の表層部を表面から0.1〜100nmの深さに及んで炭化することを特徴とする。   In the third method for manufacturing a compound semiconductor growth substrate, the upper portion of the Si single crystal substrate is made porous to open outward, and a porous Si single crystal layer having a porosity of 10 to 90% is formed. Thereafter, a Si single crystal layer having a thickness of 0.1 to 5 μm is stacked on the porous Si single crystal layer by vapor phase growth, and thereafter, heat treatment is performed on the Si single crystal layer at a temperature of 800 to 1400 ° C. in a carbon raw material atmosphere. The surface layer portion of the Si single crystal layer is carbonized to a depth of 0.1 to 100 nm from the surface while the surface is adjusted to have a surface roughness of 0.1 to 100 nm.

本発明の第1の化合物半導体成長用基板及びその製造方法によれば、多孔質Si単結晶層の表面の3C−SiC単結晶層が緩衝層として機能するので、化合物半導体の単結晶膜を積層する際、格子不整合による化合物半導体の欠陥発生を低減することができる。
又、多孔質Si単結晶層が熱膨張係数差に起因した応力による化合物半導体の欠陥発生を低減することができ、加えて、多孔度を制御することで、多孔質層の機械的強度を制御して熱膨張係数差に起因した応力による化合物半導体の欠陥発生を低減することができる。
更に、表面粗さを制御することで、表面粗さに起因した欠陥発生を低減することができ、化合物半導体を高品質なものとすることができる。
According to the first compound semiconductor growth substrate and the method of manufacturing the same of the present invention, the 3C-SiC single crystal layer on the surface of the porous Si single crystal layer functions as a buffer layer. In this case, the generation of defects in the compound semiconductor due to lattice mismatch can be reduced.
In addition, the porous Si single crystal layer can reduce the occurrence of compound semiconductor defects due to stress caused by the difference in thermal expansion coefficient. In addition, the mechanical strength of the porous layer can be controlled by controlling the porosity. Thus, the occurrence of defects in the compound semiconductor due to stress caused by the difference in thermal expansion coefficient can be reduced.
Furthermore, by controlling the surface roughness, it is possible to reduce the occurrence of defects due to the surface roughness, and to improve the quality of the compound semiconductor.

第2の化合物半導体成長用基板及びその製造方法によれば、3C−SiC単結晶層が緩衝層として機能するので、化合物半導体の単結晶膜を積層する際、格子不整合による化合物半導体の欠陥発生を低減することができる。
又、多孔質3C−SiC単結晶層が熱膨張係数差に起因した応力による化合物半導体の欠陥発生を低減することができ、加えて、多孔度を制御することで、多孔質層の機械的強度を制御して熱膨張係数差に起因した応力による化合物半導体の欠陥発生を低減することができる。
更に、表面粗さを制御することで、表面粗さに起因した欠陥発生を低減することができ、化合物半導体を高品質なものとすることができる。
According to the second compound semiconductor growth substrate and the manufacturing method thereof, the 3C-SiC single crystal layer functions as a buffer layer. Therefore, when a single crystal film of the compound semiconductor is stacked, a defect of the compound semiconductor is generated due to lattice mismatch. Can be reduced.
In addition, the porous 3C-SiC single crystal layer can reduce the occurrence of defects in the compound semiconductor due to the stress caused by the difference in thermal expansion coefficient, and in addition, the mechanical strength of the porous layer can be controlled by controlling the porosity. Thus, the generation of defects in the compound semiconductor due to the stress caused by the difference in thermal expansion coefficient can be reduced.
Furthermore, by controlling the surface roughness, it is possible to reduce the occurrence of defects due to the surface roughness, and to improve the quality of the compound semiconductor.

第3の化合物半導体成長用基板及びその製造方法によれば、第1のもの及びその製造方法による作用効果の他、非多孔質であるSi単結晶層が、多孔質Si単結晶層によって発生する段差を埋めることで表面は原子レベルで平坦になるので、化合物半導体の単結晶膜を積層する際、段差による化合物半導体の欠陥発生を低減することができ、化合物半導体を一層高品質なものとすることができる。   According to the third compound semiconductor growth substrate and the manufacturing method thereof, the non-porous Si single crystal layer is generated by the porous Si single crystal layer in addition to the effects of the first and the manufacturing method. Since the surface is flattened at the atomic level by filling the step, the generation of defects in the compound semiconductor due to the step can be reduced when the compound semiconductor single crystal film is stacked, and the compound semiconductor is made of higher quality. be able to.

Si単結晶基板は、(100)面又は(111)面のいずれであってもよい。
又、Si単結晶基板の厚さは、100〜1000μmが好ましく、より好ましくは300〜800μmである。
Si単結晶基板の厚さが、100μm未満であると、機械的強度不足となる。一方、1000μmを超えると、経済的な損失となる。
The Si single crystal substrate may be either the (100) plane or the (111) plane.
Further, the thickness of the Si single crystal substrate is preferably 100 to 1000 μm, more preferably 300 to 800 μm.
When the thickness of the Si single crystal substrate is less than 100 μm, the mechanical strength is insufficient. On the other hand, when it exceeds 1000 μm, an economic loss occurs.

多孔質Si単結晶の多孔度(気孔率)が、10%未満であると、緩衝層としての機能不足となる。一方、90%を超えると、機械的強度不足となる。
多孔質Si単結晶層の多孔度は、20〜80%がより好ましい。
When the porosity (porosity) of the porous Si single crystal is less than 10%, the function as a buffer layer is insufficient. On the other hand, if it exceeds 90%, the mechanical strength is insufficient.
The porosity of the porous Si single crystal layer is more preferably 20 to 80%.

多孔質Si単結晶の表面を被覆する3C−SiC単結晶層の表面粗さが0.1nm未満であるのは、多孔質Si単結晶層の物理的な寸法から困難となる。一方、100nmを超えると、表面粗さに起因した欠陥が発生して品質の低下となる。   It is difficult for the surface roughness of the 3C-SiC single crystal layer covering the surface of the porous Si single crystal to be less than 0.1 nm because of the physical dimensions of the porous Si single crystal layer. On the other hand, if it exceeds 100 nm, defects due to the surface roughness occur and the quality deteriorates.

多孔質Si単結晶層の表面を被覆する3C−SiC単結晶層の厚さが、0.1nm未満であると、緩衝層としての機能不足となる。一方、100nmを超えると経済的な損失となる。
多孔質Si単結晶層の表面を被覆する3C−SiC単結晶層の厚さは、1〜50nmがより好ましい。
又、多孔質Si単結晶層の厚さは、0.1〜1000μmが好ましく、より好ましくは、1〜100μmである。
多孔質Si単結晶層の厚さが、0.1μm未満であると、緩衝層としての機能不足となる。一方、1000μmを超えると、経済的な損失となる。
When the thickness of the 3C—SiC single crystal layer covering the surface of the porous Si single crystal layer is less than 0.1 nm, the function as a buffer layer is insufficient. On the other hand, if it exceeds 100 nm, an economic loss occurs.
The thickness of the 3C—SiC single crystal layer covering the surface of the porous Si single crystal layer is more preferably 1 to 50 nm.
Further, the thickness of the porous Si single crystal layer is preferably 0.1 to 1000 μm, and more preferably 1 to 100 μm.
When the thickness of the porous Si single crystal layer is less than 0.1 μm, the function as a buffer layer is insufficient. On the other hand, when it exceeds 1000 μm, an economic loss occurs.

多孔質3C−SiC単結晶層の多孔度が、10%未満であると、緩衝層としての機能不足となる。一方、90%を超えると、機械的強度不足となる。
多孔質3C−SiC単結晶層の多孔度は、20〜80%がより好ましい。
When the porosity of the porous 3C-SiC single crystal layer is less than 10%, the function as a buffer layer is insufficient. On the other hand, if it exceeds 90%, the mechanical strength is insufficient.
The porosity of the porous 3C—SiC single crystal layer is more preferably 20 to 80%.

多孔質3C−SiC単結晶層の表面粗さが、0.1未満であるのは、多孔質3C−SiC単結晶層の物理的な寸法から困難となる。一方、100nmを超えると、表面粗さに起因した欠陥が発生して品質の低下となる。   It is difficult for the surface roughness of the porous 3C—SiC single crystal layer to be less than 0.1 due to the physical dimensions of the porous 3C—SiC single crystal layer. On the other hand, if it exceeds 100 nm, defects due to the surface roughness occur and the quality deteriorates.

多孔質3C−SiC単結晶層の厚さは、0.1〜1000μmが好ましく、より好ましくは、1〜100μmである。
多孔質3C−SiC単結晶層の厚さが、0.1μm未満であると、緩衝層としての機能不足となる。一方、1000μmを超えると、経済的な損失となる。
The thickness of the porous 3C—SiC single crystal layer is preferably 0.1 to 1000 μm, and more preferably 1 to 100 μm.
When the thickness of the porous 3C—SiC single crystal layer is less than 0.1 μm, the function as a buffer layer is insufficient. On the other hand, when it exceeds 1000 μm, an economic loss occurs.

多孔質Si単結晶層の多孔度が、10%未満であると、緩衝層としての機能不足となる。一方、90%を超えると、機械的強度不足となる。
多孔質Si単結晶層の多孔度は、20〜80%がより好ましい。
When the porosity of the porous Si single crystal layer is less than 10%, the function as a buffer layer is insufficient. On the other hand, if it exceeds 90%, the mechanical strength is insufficient.
The porosity of the porous Si single crystal layer is more preferably 20 to 80%.

Si単結晶層の厚さが、0.1μm未満であると、その表面が平坦でなくなる。一方、5μmを超えると、品質の向上が恒常的となり、原料の浪費となる。
Si単結晶層の厚さは、0.2〜2μmがより好ましい。
When the thickness of the Si single crystal layer is less than 0.1 μm, the surface is not flat. On the other hand, when the thickness exceeds 5 μm, the improvement in quality becomes constant and the raw material is wasted.
The thickness of the Si single crystal layer is more preferably 0.2 to 2 μm.

3C−SiC単結晶層の表面粗さが0.1nm未満であるのは、3C−SiC単結晶層の物理的な寸法から困難となる。一方、100nmを超えると、表面粗さに起因した欠陥が発生して品質の低下となる。   It is difficult for the surface roughness of the 3C—SiC single crystal layer to be less than 0.1 nm because of the physical dimensions of the 3C—SiC single crystal layer. On the other hand, if it exceeds 100 nm, defects due to the surface roughness occur and the quality deteriorates.

3C−SiC単結晶層の厚さが、1nm未満であると、緩衝層としての機能不足となる。一方、100nmを超えると経済的な損失となる。
3C−SiC単結晶層の厚さは、5〜50nmがより好ましい。
When the thickness of the 3C—SiC single crystal layer is less than 1 nm, the function as a buffer layer is insufficient. On the other hand, if it exceeds 100 nm, an economic loss occurs.
The thickness of the 3C—SiC single crystal layer is more preferably 5 to 50 nm.

Si単結晶基板の上部の多孔質化の方法としては、HF(フッ酸、フッ化水素酸)及びエタノールを含む水溶液中で直流バイアスにより陽極化成処理を行う陽極化成法、HNO3(硝酸)やHF中にSi単結晶基板を浸漬する化学エッチング法等が挙げられる。 Examples of the method for making the upper part of the Si single crystal substrate porous include an anodizing method in which an anodizing treatment is performed by a direct current bias in an aqueous solution containing HF (hydrofluoric acid, hydrofluoric acid), ethanol, HNO 3 (nitric acid), The chemical etching method etc. which immerse a Si single crystal substrate in HF are mentioned.

多孔質Si単結晶層を炭化する熱処理温度が、800℃未満であると、反応が起こらず炭化不足となる。一方、1400℃を超えると、Si融点を越えて物理的に困難となる。
多孔質Si単結晶層を炭化する熱処理温度は、1000〜1200℃がより好ましい。
When the heat treatment temperature for carbonizing the porous Si single crystal layer is less than 800 ° C., no reaction occurs and the carbonization is insufficient. On the other hand, when it exceeds 1400 ° C., it becomes physically difficult to exceed the Si melting point.
As for the heat processing temperature which carbonizes a porous Si single crystal layer, 1000-1200 degreeC is more preferable.

炭素原料としてはC38(プロパン)、CH4(メタン)、C410(ブタン)等のパラフィン炭化水素の如く炭素が含まれていればよく、かつ、気体、液体等の状態を問わない。
又、炭素原料は、水素等で希釈して用いてもよい。
The carbon material only needs to contain carbon such as paraffin hydrocarbons such as C 3 H 8 (propane), CH 4 (methane), C 4 H 10 (butane), etc. It doesn't matter.
The carbon raw material may be diluted with hydrogen or the like.

非多孔質であるSi単結晶層の気相成長温度は、800〜1200℃が好ましく、より好ましくは900〜1100℃である。
Si単結晶層の気相成長温度が、800℃未満であると、原料が分解せず成長が起こらない。一方、1200℃を超えると、不純物汚染が顕著となる。
The vapor phase growth temperature of the non-porous Si single crystal layer is preferably 800 to 1200 ° C, more preferably 900 to 1100 ° C.
When the vapor phase growth temperature of the Si single crystal layer is less than 800 ° C., the raw material is not decomposed and growth does not occur. On the other hand, when it exceeds 1200 ° C., impurity contamination becomes significant.

Si単結晶層の気相成長の原料ガスとしては、SiH4(モノシラン)等の水素化ケイ素原料の他、SiH2Cl2(ジクロロシラン)、SiHCl3(トリクロロシラン)等の塩化シラン系原料が用いられる。 The raw material gas for vapor phase growth of the Si single crystal layer includes a silicon hydride source material such as SiH 2 Cl 2 (dichlorosilane) and SiHCl 3 (trichlorosilane) as well as a silicon hydride source material such as SiH 4 (monosilane). Used.

化合物半導体成長用基板に気相成長される化合物半導体としては、3C−SiC、c−BP(立方晶リン化ホウ素)等の他、AlN(窒化アルミニウム)、InN(窒化インジウム)及び立方晶又は六方晶のGaN(窒化ガリウム)等の窒化物と呼ばれるものが挙げられる。   Compound semiconductors that are vapor-grown on a compound semiconductor growth substrate include 3C—SiC, c-BP (cubic boron phosphide), AlN (aluminum nitride), InN (indium nitride), and cubic or hexagonal. Examples thereof include nitrides such as crystal GaN (gallium nitride).

図1は、本発明に係る化合物半導体成長用基板の実施例1を示す概念的な断面図である。   FIG. 1 is a conceptual cross-sectional view showing Example 1 of a compound semiconductor growth substrate according to the present invention.

この化合物半導体成長用基板1は、厚さ300μmのSi単結晶基板2上に、外方(図1においては上方)へ開孔し、かつ、多孔度が50%で、表面が表面粗さ10nm、厚さ1nmの3C−SiC単結晶層3によって被覆された厚さ10μmの多孔質Si単結晶4が形成されているものである。   This compound semiconductor growth substrate 1 is opened outward (upward in FIG. 1) on a 300 μm thick Si single crystal substrate 2 and has a porosity of 50% and a surface roughness of 10 nm. A porous Si single crystal 4 having a thickness of 10 μm and covered with a 3 C—SiC single crystal layer 3 having a thickness of 1 nm is formed.

上述した化合物半導体成長用基板1を製造するには、先ず、HF及びエタノールを含む水溶液中に厚さ300μmのSi単結晶基板と白金格子電極(いずれも図示せず)とを対向させて浸漬し、かつ、Si単結晶基板に設けたアルミ電極を陽極、白金格子電極を陰極として直流電源により給電しながら陽極化成処理を行い、HFとの接触面であるSi単結晶基板2の上面から10μmの深さに亘り多孔度50%程度に多孔質化して多孔質Si単結晶層4′を形成する(図2参照)。   In order to manufacture the above-described compound semiconductor growth substrate 1, first, a 300 μm thick Si single crystal substrate and a platinum lattice electrode (both not shown) are immersed in an aqueous solution containing HF and ethanol. In addition, anodization is performed while feeding power from a DC power source using an aluminum electrode provided on the Si single crystal substrate as an anode and a platinum lattice electrode as a cathode, and 10 μm from the upper surface of the Si single crystal substrate 2 which is a contact surface with HF. A porous Si single crystal layer 4 ′ is formed by making the porosity about 50% over the depth (see FIG. 2).

次に、多孔質Si単結晶層4′に、C38ガス雰囲気において1000℃の温度で熱処理を施し(図2参照)、表面を表面粗さ10nm程度に調製しつつ、多孔質Si単結晶層4′の表層部を表面から1nm程度の深さに及んで炭化して3C−SiC単結晶層3(図1参照)を形成する。
なお、3C−SiC単結晶層3の表面粗さ及び厚さは、多孔質Si単結晶層4′の多孔度、炭素原料雰囲気での熱処理における時間や温度で調整することが可能である。
Next, the porous Si single crystal layer 4 ′ is heat-treated at a temperature of 1000 ° C. in a C 3 H 8 gas atmosphere (see FIG. 2), and the surface is adjusted to a surface roughness of about 10 nm, while the porous Si single crystal layer 4 ′ is subjected to heat treatment. The surface layer portion of the crystal layer 4 ′ is carbonized to a depth of about 1 nm from the surface to form the 3C—SiC single crystal layer 3 (see FIG. 1).
The surface roughness and thickness of the 3C—SiC single crystal layer 3 can be adjusted by the porosity of the porous Si single crystal layer 4 ′ and the time and temperature in the heat treatment in the carbon raw material atmosphere.

ここで、上述した化合物半導体成長用基板1を使用し、原料ガスとしてSiH4(モノシラン)及びC38を用いると共に、1150℃の温度で、化合物半導体として厚さ5μmの3C−SiC単結晶膜を気相成長により積層し、その結晶欠陥を調べる一方、実施例1の多孔質Si単結晶層に酸化処理を施したものを比較のための従来の化合物半導体成長用基板として使用し、上述した場合と同様に3C−SiC単結晶膜を積層してその結晶欠陥を調べたところ、実施例1のものの化合物半導体の欠陥が従来のもののそれの1/10程度に低減した。
ちなみに、従来の化合物半導体成長用基板において多孔質Si単結晶層に酸化処理を施すのは、多孔質Si単結晶層が熱処理によって再構築されるのを阻止するためであり、酸化処理は、O2(酸素)ガス雰囲気において300〜500℃の温度で熱処理したり、あるいは、酸化剤(例えば、H22:過酸化水素水)を含む化学薬品に浸す方法がとられる。
一方、化合物半導体成長用基板1における多孔質Si単結晶4の多孔度を20%、30%及び60%と変え、上述した場合と同様に3C−SiC単結晶膜を積層し、SiCの検出強度を調べたところ、非多孔質のSi単結晶層のもののそれを併記した図7に示すようになった。
したがって、多孔質Si単結晶層4の多孔度を50〜70%とれば、3C−SiC単結晶膜を良好に作製し得ることが分かる。
Here, the above-described compound semiconductor growth substrate 1 is used, SiH 4 (monosilane) and C 3 H 8 are used as source gases, and a 3C—SiC single crystal having a thickness of 5 μm as a compound semiconductor at a temperature of 1150 ° C. While the films were stacked by vapor phase growth and the crystal defects were examined, the porous Si single crystal layer of Example 1 was oxidized and used as a conventional compound semiconductor growth substrate for comparison. When the 3C-SiC single crystal film was laminated and the crystal defects were examined in the same manner as in the case of the above, the defects of the compound semiconductor of Example 1 were reduced to about 1/10 of that of the conventional one.
Incidentally, the reason why the porous Si single crystal layer is oxidized in the conventional compound semiconductor growth substrate is to prevent the porous Si single crystal layer from being reconstructed by heat treatment. 2 A heat treatment is performed at a temperature of 300 to 500 ° C. in a (oxygen) gas atmosphere, or a method of immersing in a chemical containing an oxidizing agent (for example, H 2 O 2 : hydrogen peroxide solution).
On the other hand, the porosity of the porous Si single crystal 4 in the compound semiconductor growth substrate 1 is changed to 20%, 30%, and 60%, and a 3C-SiC single crystal film is laminated in the same manner as described above, and the SiC detection intensity As a result, the non-porous Si single crystal layer was obtained as shown in FIG.
Therefore, it can be seen that if the porosity of the porous Si single crystal layer 4 is 50 to 70%, a 3C—SiC single crystal film can be satisfactorily produced.

図3は、本発明に係る化合物半導体成長用基板の実施例2を示す概念的な断面図である。   FIG. 3 is a conceptual cross-sectional view showing Example 2 of a compound semiconductor growth substrate according to the present invention.

この化合物半導体成長用基板5は、厚さ300μmのSi単結晶基板6上に、外方(図3においては上方)へ開孔し、かつ、多孔度50%、表面粗さ10nmで、厚さ10μmの多孔質3C−SiC単結晶層7が形成されているものである。   This compound semiconductor growth substrate 5 is opened outward (upward in FIG. 3) on a 300 μm-thick Si single crystal substrate 6 and has a porosity of 50% and a surface roughness of 10 nm. A 10 μm porous 3C—SiC single crystal layer 7 is formed.

上述した化合物半導体成長用基板5を製造するには、先ず、厚さ300μmのSi単結晶基板6の上部を実施例1と同様に多孔質化して外方へ開孔し、多孔度50%で、厚さ10μmの多孔質Si単結晶層7′を形成する(図4参照)。   In order to manufacture the compound semiconductor growth substrate 5 described above, first, the upper part of the Si single crystal substrate 6 having a thickness of 300 μm is made porous in the same manner as in Example 1 and opened outward, and the porosity is 50%. Then, a porous Si single crystal layer 7 ′ having a thickness of 10 μm is formed (see FIG. 4).

次に、多孔質Si単結晶層7′に、C38ガス雰囲気において1000℃の温度で熱処理を施し(図4参照)、表面を表面粗さ10nm程度に調製しつつ、多孔質Si単結晶層7′の全部を炭化して多孔質3C−SiC単結晶層7(図3参照)に変成する。
なお、多孔質3C−SiC単結晶層7の表面粗さ及び厚さは、多孔質Si単結晶層7′の多孔度、炭素原料雰囲気での熱処理における時間や温度で調整することが可能である。
Next, the porous Si single crystal layer 7 ′ is subjected to a heat treatment at a temperature of 1000 ° C. in a C 3 H 8 gas atmosphere (see FIG. 4) to adjust the surface to a surface roughness of about 10 nm, while maintaining the surface of the porous Si single crystal layer 7 ′. The entire crystal layer 7 'is carbonized and transformed into a porous 3C-SiC single crystal layer 7 (see FIG. 3).
The surface roughness and thickness of the porous 3C—SiC single crystal layer 7 can be adjusted by the porosity of the porous Si single crystal layer 7 ′ and the time and temperature in the heat treatment in the carbon raw material atmosphere. .

ここで、上述した化合物半導体成長用基板5を使用し、原料ガスとしてSiH4及びC38を用いると共に、1150℃の温度で、化合物半導体として厚さ5μmの3C−SiC単結晶膜を気相成長により積層し、その結晶欠陥を調べる一方、前述した多孔質Si単結晶層7′を炭化することなく、それに酸化処理を施したものを比較のための従来の化合物半導体成長用基板として使用し、上述した場合と同様に3C−SiC単結晶膜を積層してその結晶欠陥を調べたところ、実施例2のものの化合物半導体の欠陥が従来のもののそれの1/10程度に低減した。 Here, the above-described compound semiconductor growth substrate 5 is used, SiH 4 and C 3 H 8 are used as source gases, and a 3C-SiC single crystal film having a thickness of 5 μm is removed as a compound semiconductor at a temperature of 1150 ° C. Laminated by phase growth and examined for crystal defects, while the porous Si single crystal layer 7 'described above is not carbonized but is subjected to oxidation treatment as a conventional compound semiconductor growth substrate for comparison. Then, as in the case described above, the 3C—SiC single crystal films were stacked and the crystal defects were examined. As a result, the defects of the compound semiconductor of Example 2 were reduced to about 1/10 of that of the conventional one.

図5は、本発明に係る化合物半導体成長用基板の実施例3を示す概念的な断面図である。   FIG. 5 is a conceptual sectional view showing Example 3 of a compound semiconductor growth substrate according to the present invention.

この化合物半導体成長用基板8は、厚さ300μmのSi単結晶基板9上に、外方(図5においては上方)へ開孔し、かつ、多孔度50%、厚さ10μmの多孔質Si単結晶層10、厚さ1μmの非多孔質であるSi単結晶層11及び表面粗さ10nm、厚さ1nmの3C−SiC単結晶層12が順に形成されているものである。   This compound semiconductor growth substrate 8 is opened outward (upward in FIG. 5) on a 300 μm-thick Si single crystal substrate 9 and has a porosity of 50% and a thickness of 10 μm. A crystal layer 10, a non-porous Si single crystal layer 11 having a thickness of 1 μm, and a 3C—SiC single crystal layer 12 having a surface roughness of 10 nm and a thickness of 1 nm are sequentially formed.

上述した化合物半導体成長用基板8を製造するには、先ず、厚さ300μmのSi単結晶基板9の上部を実施例1と同様に多孔質化して外方へ開孔して、多孔度50%、厚さ10μmの多孔質Si単結晶層10(図6(a)参照)を形成する。   In order to manufacture the compound semiconductor growth substrate 8 described above, first, the upper part of the Si single crystal substrate 9 having a thickness of 300 μm is made porous in the same manner as in Example 1 and opened outwardly, and the porosity is 50%. Then, a porous Si single crystal layer 10 (see FIG. 6A) having a thickness of 10 μm is formed.

次に、多孔質Si単結晶層10上に、SiH4ガス雰囲気、1000℃の条件の気相成長条件で(図6(a)参照)、厚さ1μmの非多孔質であるSi単結晶層11(図6(b)参照)を積層する。 Next, a non-porous Si single crystal layer having a thickness of 1 μm is formed on the porous Si single crystal layer 10 under vapor phase growth conditions of SiH 4 gas atmosphere and 1000 ° C. (see FIG. 6A). 11 (see FIG. 6B) are stacked.

次いで、Si単結晶層11上にC38ガス雰囲気において1000℃の温度で熱処理を施し(図6(b)参照)、表面を表面粗さ10nm程度に調製しつつ、Si単結晶層11の上部を表面から1nmの深さに及んで炭化して3C−SiC単結晶層12(図5参照)に変成する。 Next, heat treatment is performed on the Si single crystal layer 11 at a temperature of 1000 ° C. in a C 3 H 8 gas atmosphere (see FIG. 6B), and the surface of the Si single crystal layer 11 is adjusted to a surface roughness of about 10 nm. The upper part of carbon is carbonized to a depth of 1 nm from the surface and transformed into a 3C—SiC single crystal layer 12 (see FIG. 5).

ここで、上述した化合物半導体成長用基板8を使用し、原料ガスとしてSiH4及びC38を用いると共に、1150℃の温度で、化合物半導体として厚さ5μmの3C−SiC単結晶膜を気相成長により積層し、その結晶欠陥を調べる一方、前述したSi単結晶層11の上部に炭化処理を施すことなくそのままとしたものを比較のための従来の化合物半導体成長用基板として使用し、上述した場合と同様に3C−SiC単結晶膜を積層してその結晶欠陥を調べたところ、実施例3のものの化合物半導体の欠陥が従来のもののそれの1/100程度に低減した。 Here, the above-described compound semiconductor growth substrate 8 is used, SiH 4 and C 3 H 8 are used as source gases, and a 3C—SiC single crystal film having a thickness of 5 μm is removed as a compound semiconductor at a temperature of 1150 ° C. While stacking by phase growth and examining the crystal defects, the above-described Si single crystal layer 11 was left as it was without being carbonized as a conventional compound semiconductor growth substrate for comparison. When the 3C-SiC single crystal film was laminated and the crystal defects were examined in the same manner as in the case of the above, the defect of the compound semiconductor of Example 3 was reduced to about 1/100 of that of the conventional one.

本発明に係る化合物半導体成長用基板の実施例1を示す概念的な断面図である。1 is a conceptual cross-sectional view showing Example 1 of a compound semiconductor growth substrate according to the present invention. 図1の化合物半導体成長用基板の製造方法を示す説明図である。It is explanatory drawing which shows the manufacturing method of the substrate for compound semiconductor growth of FIG. 本発明に係る化合物半導体成長用基板の実施例2を示す概念的な断面図である。It is a conceptual sectional view showing Example 2 of the substrate for compound semiconductor growth concerning the present invention. 図3の化合物半導体成長用基板の製造方法を示す説明図である。It is explanatory drawing which shows the manufacturing method of the substrate for compound semiconductor growth of FIG. 本発明に係る化合物半導体成長用基板の実施例3を示す概念的な断面図である。It is a conceptual sectional view showing Example 3 of the compound semiconductor growth substrate concerning the present invention. 図5の化合物半導体成長用基板の製造方法を示すもので、(a)は第1工程説明図、(b)は最終工程説明図である。5A and 5B show a method for manufacturing the compound semiconductor growth substrate of FIG. 5, where FIG. 5A is a first process explanatory diagram and FIG. 5B is a final process explanatory diagram. 図1の化合物半導体成長用基板において多孔質Si単結晶層の多孔度を変えて3C−SiC単結晶膜を積層した場合に検出されるSiCの強度を示す説明図である。FIG. 2 is an explanatory diagram showing SiC intensity detected when a 3C—SiC single crystal film is laminated while changing the porosity of a porous Si single crystal layer in the compound semiconductor growth substrate of FIG. 1.

符号の説明Explanation of symbols

2 Si単結晶基板
3 3C−SiC単結晶層
4 多孔質Si単結晶層
6 Si単結晶基板
7 多孔質3C−SiC単結晶層
7′ 多孔質Si単結晶層
9 Si単結晶基板
10 多孔質Si単結晶層
11 Si単結晶層
12 3C−SiC単結晶層
2 Si single crystal substrate 3 3C-SiC single crystal layer 4 Porous Si single crystal layer 6 Si single crystal substrate 7 Porous 3C-SiC single crystal layer 7 'Porous Si single crystal layer 9 Si single crystal substrate 10 Porous Si Single crystal layer 11 Si single crystal layer 12 3C-SiC single crystal layer

Claims (6)

Si単結晶基板上に外方へ開孔し、かつ、多孔度が10〜90%で、表面が表面粗さ0.1〜100nm、厚さ0.1〜100nmの3C−SiC単結晶層によって被覆された多孔質Si単結晶層が形成されていることを特徴とする化合物半導体成長用基板。   A 3C-SiC single crystal layer that opens outward on a Si single crystal substrate, has a porosity of 10 to 90%, has a surface roughness of 0.1 to 100 nm, and a thickness of 0.1 to 100 nm. A substrate for growing a compound semiconductor, wherein a coated porous Si single crystal layer is formed. Si単結晶基板上に外方へ開孔し、かつ、多孔度10〜90%、表面粗さ0.1〜100nmの多孔質3C−SiC単結晶層が形成されていることを特徴とする化合物半導体成長用基板。   A compound characterized in that a porous 3C-SiC single crystal layer having a porosity of 10 to 90% and a surface roughness of 0.1 to 100 nm is formed on a Si single crystal substrate. Semiconductor growth substrate. Si単結晶基板上に外方へ開孔し、かつ、多孔度10〜90%の多孔質Si単結晶層、厚さ0.1〜5μmのSi単結晶層及び表面粗さ0.1〜100nm、厚さ0.1〜100nmの3C−SiC単結晶層が順に形成されていることを特徴とする化合物半導体成長用基板。   A porous Si single crystal layer having a porosity of 10 to 90%, a Si single crystal layer having a thickness of 0.1 to 5 μm, and a surface roughness of 0.1 to 100 nm. A compound semiconductor growth substrate, wherein a 3C—SiC single crystal layer having a thickness of 0.1 to 100 nm is formed in order. Si単結晶基板の上部を多孔質化して外方へ開孔し、かつ、多孔度10〜90%の多孔質Si単結晶層を形成した後、多孔質Si単結晶層に炭素原料雰囲気において800〜1400℃の温度で熱処理を施して表面を表面粗さ0.1〜100nmに調製しつつ、多孔質Si単結晶層の表層部を表面から0.1〜100nmの深さに及んで炭化することを特徴とする化合物半導体成長用基板の製造方法。   The upper part of the Si single crystal substrate is made porous to open outward, and after forming a porous Si single crystal layer having a porosity of 10 to 90%, the porous Si single crystal layer is subjected to 800 in a carbon raw material atmosphere. While heat-treating at a temperature of ˜1400 ° C. to adjust the surface to a surface roughness of 0.1 to 100 nm, the surface layer portion of the porous Si single crystal layer is carbonized to a depth of 0.1 to 100 nm from the surface. A method for manufacturing a compound semiconductor growth substrate. Si単結晶基板の上部を多孔質化して外方へ開孔し、かつ、多孔度が10〜90%の多孔質Si単結晶層を形成した後、多孔質Si単結晶層に炭素原料雰囲気において800〜1400℃の温度で熱処理を施して表面を表面粗さ0.1〜100nmに調製しつつ、多孔質Si単結晶層の全部を炭化することを特徴とする化合物半導体成長用基板の製造方法。   The upper part of the Si single crystal substrate is made porous to open outward, and after forming a porous Si single crystal layer having a porosity of 10 to 90%, the porous Si single crystal layer is exposed to a carbon source atmosphere. A method for producing a compound semiconductor growth substrate, characterized by carbonizing the entire porous Si single crystal layer while performing a heat treatment at a temperature of 800 to 1400 ° C. to prepare a surface roughness of 0.1 to 100 nm. . Si単結晶基板の上部を多孔質化して外方へ開孔し、かつ、多孔度が10〜90%の多孔質Si単結晶層を形成した後、多孔質Si単結晶層上に気相成長により厚さ0.1〜5μmのSi単結晶層を積層し、しかる後に、Si単結晶層に炭素原料雰囲気において800〜1400℃の温度で熱処理を施して表面を表面粗さ0.1〜100nmに調製しつつ、Si単結晶層の表層部を表面から0.1〜100nmの深さに及んで炭化することを特徴とする化合物半導体成長用基板の製造方法。
The upper part of the Si single crystal substrate is made porous to open outward, and after forming a porous Si single crystal layer having a porosity of 10 to 90%, vapor phase growth is performed on the porous Si single crystal layer. Then, a Si single crystal layer having a thickness of 0.1 to 5 μm is laminated, and then the Si single crystal layer is subjected to a heat treatment at a temperature of 800 to 1400 ° C. in a carbon raw material atmosphere so that the surface has a surface roughness of 0.1 to 100 nm. A method for producing a compound semiconductor growth substrate, characterized in that the surface layer portion of the Si single crystal layer is carbonized to a depth of 0.1 to 100 nm from the surface while being prepared.
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JP2010232380A (en) * 2009-03-26 2010-10-14 Seiko Epson Corp Method of manufacturing semiconductor substrate and semiconductor substrate
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WO2024126216A1 (en) * 2022-12-12 2024-06-20 Iqe Plc Systems and methods for porous wall coatings

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