JP2006042493A - Apparatus and method for controlling motor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motor controller with which the following problems can be solved: a problem that, when the speed of a phase excitation motor is changed during constant speed rotation, the CPU resources become insufficient; a problem that, when the motor speed is controlled simply using acceleration/deceleration tables, much processing time is required. <P>SOLUTION: An image forming apparatus includes: CPU 200 having a clock oscillator 210 and a communication control unit 211; and ASIC 203 having a clock oscillator 221, a control unit 223, and a port register 224. The control unit 223 of the ASIC 203 operates as follows: when a stepping motor 204 is controlled at acceleration, it outputs to the stepping motor 204 a phase excitation signal synchronized with internal clock and corresponding to a phase excitation pattern; when the stepping motor 204 is controlled at constant speed, it outputs to the stepping motor 204 a phase excitation signal synchronized with external clock from the CPU 200; and when the stepping motor 204 is controlled at deceleration, it outputs to the stepping motor 204 a phase excitation signal synchronized with internal clock. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a motor control device applicable to control of a phase excitation motor such as a stepping motor and a control method thereof.

  Conventionally, when controlling a phase excitation motor, control is performed using a general-purpose CPU (central processing unit) or a control circuit in place of the CPU. In particular, an image forming apparatus uses a very large number of phase excitation motors. Therefore, in an image forming apparatus, operating all motors under the control of one CPU restricts CPU resources (timer, number of ports, DTC (Data Transfer Controller), DMAC (Direct Memory Access Controller), etc.). And is accompanied by an increase in processing load on the CPU, which is very difficult.

  Therefore, when an apparatus such as an image forming apparatus is equipped with a plurality of phase excitation motors, a motor that does not require complicated control is independent of the CPU through a control circuit such as an ASIC (Application Specific Integrated Circuit). Have been proposed (see, for example, Patent Document 1 and Patent Document 2).

Further, control information for controlling the phase excitation type motor is transferred in advance from the CPU to the ASIC, and when the motor is controlled, the ASIC starts the motor control only by giving a trigger for the CPU to operate the motor. A configuration is proposed.
Japanese Patent Laid-Open No. 11-21587 JP 2002-23283 A

  However, in the prior art, when the speed change is performed at the constant speed rotation of the phase excitation motor at a constant speed, the speed change control is performed by an ASIC or the like in which the rotation pattern of the motor is determined in advance. Is very difficult. In such a case, control using a CPU is suitable. However, when many phase excitation motors are used as in an image forming apparatus, there is a problem that CPU resources are insufficient.

  On the other hand, when controlling the speed of a phase excitation type motor, it is also possible to perform speed control using an acceleration / deceleration table storing acceleration patterns / deceleration patterns for controlling acceleration / deceleration of the motor. However, when the acceleration / deceleration table is used, the table length becomes very long, and there is a problem that it takes time to set the acceleration pattern / deceleration pattern in the ASIC in advance.

  It is an object of the present invention to have a problem that CPU resources are insufficient when changing the speed of a phase excitation motor at a constant speed, or a problem that takes a long processing time when motor speed control is simply performed using an acceleration / deceleration table. It is an object of the present invention to provide a motor control device and a control method thereof that can eliminate the above-described problem.

  In order to achieve the above-described object, a motor control device of the present invention is a motor control device that controls driving of a phase excitation type motor, and is generated from a generating means for generating a clock, and from outside the motor control device. A receiving means for receiving a clock; a selecting means for selectively switching between a clock generated by the generating means and a clock received by the receiving means in accordance with a control target state of the motor; and the selection means selected by the selecting means Output means for outputting a phase excitation signal corresponding to a phase excitation pattern to the motor while synchronizing with a clock.

  In order to achieve the above-described object, a motor control device of the present invention is a motor control device that drives and controls a phase excitation type motor, and includes an internal supply means for supplying a phase excitation pattern, and an outside of the motor control device. The external supply means for supplying the input phase excitation pattern, and the phase excitation pattern supplied by the internal supply means and the phase excitation pattern supplied by the external supply means are selected according to the control target state of the motor Selection means for switching automatically, and output means for outputting to the motor a phase excitation signal corresponding to the phase excitation pattern selected by the selection means.

  According to the present invention, the clock generated inside the motor control device and the clock received from the outside of the motor control device are selectively switched according to the control target of the phase excitation motor, and synchronized with the selected clock. A phase excitation signal corresponding to the phase excitation pattern is output to the motor. This makes it possible to freely switch the control subject (motor control device, device outside the motor control device) that controls the motor in accordance with the motor control target (acceleration control, constant speed control, deceleration control). As a result, it is possible to solve the conventional problem that the CPU resource is insufficient when changing the speed at the constant speed of the motor, and the processing time when the motor speed control is simply performed using the acceleration / deceleration table. Can do.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing the internal structure of the image forming apparatus according to the first embodiment of the present invention.

  In FIG. 1, the image forming apparatus is configured as a digital copying machine, and includes an automatic document feeder 10, a main body image input unit 11, a main body image output unit 12, and a finisher 13. In the following, description of parts not directly related to the motor control of the present invention will be simplified or omitted.

  The automatic document feeder 10 is mounted on the upper part of the main body image input unit 11 and feeds a document to a reading position on a document table.

  The main body image input unit 11 is a mechanism for reading an image from a document. The light source 21 reciprocates in the left-right direction in FIG. 1 by the driving force of an optical system motor (not shown), and scans while illuminating the document on the document table. Reflected light (optical image) from the original is imaged on the CCD 26 through mirrors 22, 23, 24 and a lens 25 that are driven integrally with the light source 21. The CCD 26 converts the optical image into an electric signal. The electrical signal is further converted into a digital signal (image data). The image data is subjected to various correction processes and image processes, stored in an image memory (not shown), and transferred to the main body image output unit 11.

  The main body image output unit 12 is a mechanism for forming and outputting a read image of a document on a recording sheet. The image data transferred from the main body image output unit 11 is converted again from a digital signal to an analog signal, further amplified to an appropriate output value by an exposure control unit (not shown), and converted to an optical signal by the optical irradiation unit 27. The The optical signal propagates through the scanner 28, the lens 29, and the mirror 30 and is irradiated onto the photosensitive drum 31 to form an electrostatic latent image. The electrostatic latent image is developed with toner, and the toner image is transferred onto the conveyed recording paper. Further, the toner image is fixed by the fixing roller 32, thereby forming an image. The recording paper after the image formation is sent to the finisher 13.

  The paper feed trays 34 and 35 and the paper feed deck 36 can store a plurality of recording sheets. Any type of recording paper (including special paper such as an OHP sheet) can be fed from the manual feed tray 37. The paper feed rollers 38, 39, 40, 41, and 42 are rollers for transporting the recording paper, and are connected to a stepping motor as a drive source via a transmission mechanism such as a gear.

  Here, the rotational speed of the photosensitive drum 31 and the fixing roller 32 driven by the stepping motor is called a process speed. The process speed greatly depends on the toner particle shape, toner fixing characteristics, laser emission characteristics, and the like, and is a speed specific to each image forming apparatus, so that it is difficult to variably control the process speed. Therefore, in the image forming apparatus, a stepping motor that can output a torque sufficient for conveying thick paper is selected.

  On the other hand, the paper feed rollers 38, 39, 40, 41, 42 and the transport rollers only feed and transport the recording paper. Therefore, when the recording paper is not sandwiched between the photosensitive drum 31 and the fixing roller 32, the paper feed rollers 38, 39, 40, 41, 42 and the conveying roller are driven as fast as possible to reduce the distance between the recording papers. Control as short as possible. As a result, the productivity as an image forming apparatus can be improved.

  The finisher 13 is an apparatus attached to the main body image output unit 12 and sorts the recording paper sent from the main body image output unit 12 into the paper discharge tray 33 instructed by the control unit.

  FIG. 2 is a block diagram showing the configuration of the control system of the image forming apparatus shown in FIG.

  In FIG. 2, the control system of the image forming apparatus includes a CPU 200, a ROM 201, a RAM 202, an ASIC 203, and a data bus / address bus 207. The CPU 200 includes a clock oscillator 210 and a communication control unit (data transmission / reception unit) 211. The ASIC 203 includes a clock receiver 220, a clock oscillator 221, a control unit 223, a port register 224, a ROM 225, and a RAM 226.

  The CPU 200 is a central processing unit that controls the image forming apparatus. A clock signal line 205 is connected between the clock oscillator 210 of the CPU 200 and the clock receiver 220 of the ASIC 203. The clock signal line 205 is a signal line for transmitting the clock generated by the clock oscillator 210 to the ASIC 203. Communication signal lines 206-1 and 206-2 are connected between the communication control unit 211 of the CPU 200 and the control unit 223 of the ASIC 203. Communication signal line 206-1 is a signal line for transmitting data from CPU 200 to ASIC 203. The communication signal line 206-2 is a signal line for transmitting data from the ASIC 203 to the CPU 200.

  The clock oscillator 210 generates a clock having an arbitrary period. The communication control unit 211 performs communication with the ASIC 203. The ROM 201 stores a program used for controlling the image forming apparatus, a program for communicating with the ASIC 203, and a program for controlling the clock oscillator 210. The RAM 202 is used by the CPU 200 as a work area and a temporary storage area. In this configuration, the ROM 201 and the RAM 202 are disposed outside the CPU 200, but may be built in the CPU 200.

  The stepping motor 204 is a drive source that drives the mechanism of the image forming apparatus. Although only one stepping motor is shown in FIG. 2, the image forming apparatus is equipped with a plurality of stepping motors that respectively drive the photosensitive drum 31, the fixing roller 32, and other mechanisms. Further, in FIG. 2, sensors and the like are not shown.

  The ASIC 203 is a control circuit that drives the stepping motor 204. The clock receiver 220 receives a clock generated by the clock oscillator 210 of the CPU 200 via the clock signal line 205. The clock oscillator 221 generates a clock having an arbitrary period inside the ASIC 203. The clock oscillator 221 can oscillate by operating a timer (not shown) in the control unit 223.

  The control unit 223 controls the ASIC 203, and controls the stepping motor 204 and sensors (not shown) connected to the ASIC 203 using the ROM 225 and the RAM 226. The control unit 223 selectively switches between a clock (internal clock) generated by the clock oscillator 221 inside the ASIC 203 and a clock (external clock) input from the clock oscillator 210 of the CPU 200 via the clock signal line 205. Further, the control unit 223 executes processing shown in the flowcharts of FIGS. 10 to 12 based on a program stored in the ROM 225.

  The ROM 225 stores a plurality of phase excitation patterns for driving the stepping motor 204 and a plurality of acceleration patterns / deceleration patterns for accelerating / decelerating the stepping motor 204. The RAM 226 is used by the control unit 223 for a work area and a temporary storage area. The phase excitation pattern stored in the ROM 225 can be set and changed from outside the ASIC 203.

  Four signal lines 230, 231, 232, and 233 are connected between the port register 224 and the stepping motor 204. The port register 224 outputs a phase excitation signal corresponding to the phase excitation pattern read from the ROM 225 by the control unit 223 and output to the port register 224 to the stepping motor 204 via the signal lines 230, 231, 232, and 233. .

  FIG. 3 is a timing chart showing a method for driving the stepping motor 204.

  In FIG. 3, “clock” indicates a clock (external clock) supplied from the clock oscillator 210 of the CPU 200 via the clock signal line 205 or a clock (internal clock) supplied from the clock oscillator 221 inside the ASIC 203. ing. With the supply of the clock, the illustrated phase excitation signal is output from the port register 224 to the signal lines 230, 231, 232, and 233 so as to be synchronized with the clock. The stepping motor 204 can be rotated by sequentially inputting a sequence of predetermined phase excitation patterns via the signal lines 230, 231, 232, and 233.

The illustrated phase excitation signals output from the port register 224 to the signal lines 230, 231, 232, and 233 indicate phase excitation patterns when the stepping motor 204 is in two-phase excitation. When the signal lines 230 to 233 are expressed as bit0 to bit3, respectively,
Combination of phase excitation patterns (bit3, bit2, bit1, bit0)
= {(0,1,0,1) → (1,0,0,1) → (1,0,1,0) → (0,1,1,0)}: Forward rotation = {(0, 1,0,1) → (0,1,1,0) → (1,0,1,0) → (1,0,0,1)}: It looks like reverse. If the phase excitation pattern is regarded as 4-bit data, the phase excitation pattern is arranged with data such as “5 → 9 → A → 6” at the time of forward rotation of the stepping motor 204 and “5” at the time of reverse rotation of the stepping motor 204. It can be thought of as an array of data such as “→ 6 → A → 9”. The data is expressed in hexadecimal.

  Next, in the image forming apparatus of the present embodiment having the above-described configuration, acceleration and deceleration of the stepping motor 204 are controlled by the ASIC 203, and speed and advance amount control of the stepping motor 204 are controlled by the CPU 200. Examples will be described in detail with reference to FIGS.

  4A is a diagram showing the speed change of the acceleration section / constant speed section / deceleration section of the stepping motor 204, and FIGS. 4B and 4C are communication signal lines 206- between the CPU and the ASIC. 1 is a diagram illustrating a relationship between data flowing on 1 and 206-2 and a clock signal line 205. FIG.

  In FIG. 4A, the horizontal axis represents time, and the vertical axis represents the speed (number of rotations) of the stepping motor 204. In the present embodiment, the stepping motor 204 is accelerated and driven at a constant speed (may be changed) after being accelerated, and then decelerated and stopped. In FIG. 4B and FIG. 4C, the horizontal axis indicates the time common to the time shown in FIG.

  When the stepping motor 204 is started, communication data A and B are exchanged between the CPU 200 and the ASIC 203 before the zero point on the horizontal axis in FIG. The contents of the communication data A and B will be described later. After the communication data A and B are exchanged, the CPU 200 enables the clock signal line 205 for a predetermined time. At this time, the control unit 223 of the ASIC 203 detects the timing at which the clock supplied from the clock signal line 205 changes from High to Low, and synchronizes with the detection timing to generate a clock (internally generated by the clock oscillator 221 inside the ASIC 203. The stepping motor 204 is accelerated using a clock.

  Thereafter, when the stepping motor 204 enters the constant speed section, the control unit 223 of the ASIC 203 ends the acceleration control of the stepping motor 204 using the clock generated by the clock oscillator 221, and connects the clock signal line 205 from the clock oscillator 210 of the CPU 200. The phase excitation pattern stored in the ROM 225 in the ASIC 203 is transferred to the port register 224 while synchronizing with the clock (external clock) input via the port 224.

  When stopping the stepping motor 204, the CPU 200 sends the data C in FIG. 4B to the ASIC 203 via the communication signal line 206-1. When the control unit 223 of the ASIC 203 receives the data C from the CPU 200, it starts deceleration control of the stepping motor 204. The control unit 223 of the ASIC 203 restarts the clock oscillator 221 inside the ASIC 203 and transfers the phase excitation pattern stored in the ROM 225 to the port register 224 while synchronizing with the clock (internal clock) generated by the clock oscillator 221. .

  4B and 4C, communication data A is a stepping motor start command, communication data B is a stepping motor start response command, data C is a stepping motor stop command, and data D is a stepping motor stop response command. . The stepping motor start command, stepping motor stop command, etc. will be described in detail below.

  In the example shown in FIG. 4B (internal clock / external clock output pattern 1), the acceleration interval and deceleration interval of the stepping motor 204 are synchronized with the clock (internal clock) supplied from the clock oscillator 221 of the ASIC 203. A phase excitation signal corresponding to the phase excitation pattern is output to the stepping motor 204, and the constant speed section of the stepping motor 204 corresponds to the phase excitation pattern in synchronization with a clock (external clock) supplied from the clock oscillator 210 of the CPU 200. A phase excitation signal is output to the stepping motor 204.

  In the example shown in FIG. 4C (internal clock / external clock output pattern 2), the acceleration interval and deceleration interval of the stepping motor 204 are synchronized with the clock (external clock) supplied from the clock oscillator 210 of the CPU 200. A phase excitation signal corresponding to the phase excitation pattern is output to the stepping motor 204, and the constant velocity section of the stepping motor 204 corresponds to the phase excitation pattern in synchronization with the clock (internal clock) supplied from the clock oscillator 221 of the ASIC 203. A phase excitation signal is output to the stepping motor 204.

  FIG. 5 is a diagram illustrating a configuration necessary for the control unit 223 of the ASIC 203 to control the stepping motor 204.

  In FIG. 5, a timer counter 401 and a timer register 402 are for controlling a timer (not shown) in the ASIC 203. When the value of the timer counter 401 matches the value of the timer register 402, the clock oscillator 221 in the ASIC 203 can output a pulsed clock.

  The acceleration / deceleration table 403, the sequence table 404, and the phase excitation pattern table 408 are stored in the ROM 225, and are read from the ROM 225 onto the RAM 226 and referred to as necessary.

  The acceleration / deceleration table 403 is a table for performing acceleration control / deceleration control of the stepping motor 204, and includes a plurality of tables (table 1, table 2, table 3). Table 1, table 2, and table 3 are each composed of an acceleration table and a deceleration table.

  The sequence table 404 includes steps of the phase excitation pattern for each table (table 1, table 2,...) Of the acceleration / deceleration table 403 and steps of an external clock (clock supplied from the clock oscillator 210 of the CPU 200 to the ASIC 203). It is a table which memorize | stores a number (clock number).

  The phase excitation pattern table 408 stores a plurality of phase excitation patterns for performing phase excitation of the stepping motor 204 in association with individual addresses. The address excitation pattern of the phase excitation pattern table 408 up to which phase excitation pattern is output to the port register 405 (corresponding to 224 in FIG. 2) can be grasped by the output pointer 409 of the circular pointer by the control unit 223 of the ASIC 203.

  When the phase excitation pattern is written in the port register, the port register 405 transmits a phase excitation signal corresponding to the phase excitation pattern to the signal lines 230, 231, 232, and 233.

  The step number counter 406 counts the number of phase excitation patterns (phase excitation signals corresponding to the phase excitation patterns) output from the ASIC 203 to the stepping motor 204.

  The step number setting register 407 is an acceleration step number register in which the number of clocks (acceleration step number) necessary for accelerating the stepping motor 204 is set, and the number of clocks necessary for driving the stepping motor 204 at a constant speed ( A constant speed step number register in which a constant speed step number) is set, and a deceleration step number register in which the number of clocks (deceleration step number) necessary to decelerate and stop the stepping motor 204 is provided.

  The step number counter 406 and the step number setting register 407 are for measuring the timing at which the ASIC 203 switches the control of the stepping motor 204 between acceleration / constant speed / deceleration.

  The ASIC 203 may have a plurality of the acceleration / deceleration table 403, the step number setting register 407, and the phase excitation pattern table 408, or may be communicated from the CPU 200 via the communication signal lines 206-1 and 206-2. It is good also as a structure which can be changed.

  FIG. 6 is a diagram showing a basic structure of transmission / reception data between the CPU 200 and the ASIC 203.

  In FIG. 6, the illustrated block shows the structure of data exchanged in units of commands on the communication signal lines 206-1 and 206-2 between the CPU 200 and the ASIC 203. The head of the data is 2-byte data called a header, and is data for distinguishing the type of command. Following the header, 2-byte data called data length is arranged. The data length indicates the length of data (data 1 to data N) excluding the header, the data length itself, and SUM described later.

  Following the data length, N bytes (1 byte each) of data 1 to data N are arranged. After the data 1 to N, data called SUM is arranged. The SUM is 1-byte data for confirming whether the data receiving side (the ASIC 203 when transmitting data from the CPU 200 to the ASIC 203, or the CPU 200 when transmitting data from the ASIC 203 to the CPU 200) correctly receives the data. . The sum of each data from the header to the data N is calculated, and the data of the lowest 1 byte is set in the SUM.

  FIG. 7 is a diagram showing a stepping motor start command and a stepping motor start response command for starting the stepping motor 204.

  In FIG. 7, the illustrated block indicates a stepping motor start command and a stepping motor start response command, and is a command for controlling the stepping motor 204. The stepping motor start command is composed of an upper header, lower header, upper data length, lower data length, motor number, sequence number, and SUM. The stepping motor activation response command is composed of an upper header, lower header, upper data length, lower data length, result, and SUM.

  The communication data A shown in FIG. 4 is a stepping motor start command, and the communication data B is a stepping motor start response command. When the stepping motor 204 is activated, a stepping motor activation command and a stepping motor activation response command are always exchanged between the CPU and the ASIC before activation. This is a countermeasure against malfunction when noise is applied to the clock signal line 205. While the stepping motor activation command is not received from the CPU 200, the control unit 223 of the ASIC 203 performs control so that the stepping motor 204 is not operated.

  FIG. 8 is a diagram showing a stepping motor stop command and a stepping motor stop response command for stopping the stepping motor 204.

  In FIG. 8, the illustrated block indicates a stepping motor stop command and a stepping motor stop response command, and is a command for controlling the stepping motor 204. The stepping motor stop command is composed of an upper header, lower header, upper data length, lower data length, motor number, and SUM. The stepping motor stop response command is composed of an upper header, lower header, upper data length, lower data length, result, and SUM.

  Normally, the control unit 223 of the ASIC 203 controls the stepping motor 204 according to the counter values set in the acceleration step number register, the constant speed step number register, and the deceleration step number register in the step number setting register 407, respectively. However, when it is desired to stop the stepping motor 204 urgently, a stepping motor stop command and a stepping motor stop response command are used.

  FIG. 9 is a diagram showing a motor sequence setting command and a motor sequence setting response command of the stepping motor 204.

  In FIG. 9, the illustrated block indicates a motor sequence setting command and a motor sequence setting response command. Stepping motor setting commands are: header high, header low, data length, motor number, sequence number, acceleration / deceleration state, clock trigger, step number, frequency, ... acceleration / deceleration state, clock trigger, step number, frequency, # 3 It is composed of The stepping motor setting response command is composed of an upper header, lower header, upper data length, lower data length, motor number, setting result, and SUM.

  The driving / stopping of the stepping motor 204 may be controlled by a hardware signal or the like without using the communication command described above.

  10 to 12 are flowcharts showing clock switching control for the stepping motor 204 by the control unit 223 of the ASIC 203.

  In FIG. 10 to FIG. 12, it is the start timing of the stepping motor 204 (step S100), and when the control unit 223 of the ASIC 203 detects the H (High) edge of the clock of the clock signal line 205 (YES in step S101), the next step is performed. Perform the process. That is, the control unit 223 of the ASIC 203 sets the start address of the acceleration table in the acceleration / deceleration table 403 of the ROM 225 in the timer register 402, and then outputs the data of the start address of the phase excitation pattern table 408 of the ROM 225 on the RAM 226. Preparation is performed, the step number counter 406 is cleared to 0, and the drive current value of the stepping motor 204 is set (step S102).

  Next, when the control unit 223 of the ASIC 203 detects the L (Low) edge of the clock signal line 205 (YES in Step S103), the internal clock input setting for inputting the clock from the clock oscillator 221 in the ASIC is performed, and the timer (not set) is set. Is started (step S104). Here, the timer counter 401 is automatically counted up in synchronization with the clock input from the clock oscillator 221 inside the ASIC.

  When the value of the timer counter 401 becomes equal to the value set in the timer register 402 (YES in step S105), the control unit 223 of the ASIC 203 indicates the area indicated by the address of the phase excitation pattern table 408 read from the ROM 225 onto the RAM 226. Is read out and set in the port register 405 to output one phase excitation pattern. At this time, the control unit 223 of the ASIC 203 increases the value of the step number counter 406 by 1 (step S106).

  Next, the control unit 223 of the ASIC 203 compares the count value of the step number counter 406 (the number of phase excitation patterns output from the ASIC 203) with the set value of the acceleration step number register in the step number setting register 407 ( Step S107). If the values do not match (NO in step S107), the control unit 223 of the ASIC 203 determines that the acceleration of the stepping motor 204 has not ended, and the address of the acceleration table in the acceleration / deceleration table 403 is determined. The address of the phase excitation pattern table 408 is incremented by 1 (step S108).

  When the address is incremented by 1 and the address of the phase excitation pattern table 408 is n (the address of the final data in the phase excitation pattern table 408 + 1 (excess address)) (YES in step S109), the control unit 223 of the ASIC 203 Then, the reference address of the phase excitation pattern table 408 is set as the head address (step S110), and the process waits until the value of the timer counter 401 matches the value of the timer register 402 (step S105). If the address of the phase excitation pattern table 408 is not n (address of the phase excitation pattern final data + 1) (NO in step S109), the control unit 223 of the ASIC 203 does nothing and shifts the control to step S105.

  On the other hand, if the count value of the step number counter 406 (the number of phase excitation patterns output from the ASIC 203) matches the set value of the acceleration step number register in the step number setting register 407 (YES in step S107). ) Since the acceleration of the stepping motor 204 is completed, the control unit 223 of the ASIC 203 shifts to the constant speed control of the stepping motor 204.

  In the constant speed control of the stepping motor 204, first, the control unit 223 of the ASIC 203 sets the internal clock input (clock input from the clock oscillator 221 of the ASIC 203) to the external clock input (clock input from the clock oscillator 210 of the CPU 200). Switch. Then, the control unit 223 of the ASIC 203 clears the step number counter 406 to 0 and increments the address of the phase excitation pattern table 408 by 1 (step S111).

  Next, when the control unit 223 of the ASIC 203 detects the edge of the clock output from the clock oscillator 210 of the CPU 200 via the clock signal line 205 (YES in step S112), the phase excitation pattern table 408 determined in step S111. The phase excitation pattern stored in the area indicated by the address is output to the port register 405, and the value of the step number counter 406 is incremented by 1 (step S113).

  Thereafter, the control unit 223 of the ASIC 203 compares the count value of the step number counter 406 (the number of phase excitation patterns output from the ASIC 203) with the set value of the constant speed step number register in the step number setting register 407. At this time, the control unit 223 of the ASIC 203 checks whether or not the two values match or whether a stepping motor stop command (see FIG. 8) has been received from the CPU 200 (step S114). If the two values do not match or if a stepping motor stop command has not been received from CPU 200 (NO in step S114), control unit 223 of ASIC 203 increments the address of phase excitation pattern table 408 by one. (Step S115).

  At this time, if the address of the phase excitation pattern table 408 is n (the address of the final data in the phase excitation pattern table 408 + 1 (excess address)) (YES in step S116), the control unit 223 of the ASIC 203 performs the phase excitation pattern table. The reference address 408 is set as the head address (step S117), and the detection of the edge of the clock output from the clock oscillator 210 of the CPU 200 via the clock signal line 205 is awaited again (step S112). If the address of phase excitation pattern table 408 is not n (address of phase excitation pattern final data + 1 (excess address)) (NO in step S116), control unit 223 of ASIC 203 does nothing and shifts control to step S112. .

  On the other hand, when the count value of the step number counter 406 (the number of phase excitation patterns output from the ASIC 203) matches the set value of the constant speed step number register in the step number setting register 407, or from the CPU 200 If the stepping motor stop command has been received (YES in step S114), the constant speed control of the stepping motor 204 has been completed, and the control unit 223 of the ASIC 203 shifts to the deceleration control of the stepping motor 204.

  In the deceleration control of the stepping motor 204, the control unit 223 of the ASIC 203 switches from the setting of the external clock input (clock input from the clock oscillator 210 of the CPU 200) to the setting of the internal clock input (clock input from the clock oscillator 221 of the ASIC 203). . Then, the control unit 223 of the ASIC 203 sets the start address of the deceleration table in the acceleration / deceleration table 403 in the timer register 402, clears the step number counter 406 to 0, increments the address of the phase excitation pattern table 408 by 1, A timer (not shown) is started. (Step S118).

  When the value of the timer counter 401 matches the value of the timer register 402 (YES in step S119), the control unit 223 of the ASIC 203 refers to the address of the phase excitation pattern table 408, and stores the phase stored in the area indicated by the address. The excitation pattern is output to the port register 405, and the step number counter 406 is incremented by 1 (step S120).

  Next, the control unit 223 of the ASIC 203 compares the count value of the step number counter 406 (the number of phase excitation patterns output from the ASIC 203) with the set value of the deceleration step number register in the step number setting register 407 ( Step S121). If the value of the step number counter 406 (the number of phase excitation patterns output from the ASIC 203) and the two values do not match (NO in step S121), the controller 223 of the ASIC 203 causes the stepping motor 204 to decelerate. It is determined that the process has not been completed, and the address of the deceleration table in the acceleration / deceleration table 403 and the address of the phase excitation pattern table 408 are incremented by 1 (step S122).

  At this time, if the address of the phase excitation pattern table 408 is n (address of phase excitation pattern final data + 1 (excess address)) (YES in step S123), the control unit 223 of the ASIC 203 refers to the phase excitation pattern table 408. The address is set as the head address (step S124), and the process waits again for the value of the timer counter 401 to match the value of the timer register 402 (step S119). If the address of phase excitation pattern table 408 is not n (address of phase excitation pattern final data + 1 (excess address)) (NO in step S123), control unit 223 of ASIC 203 does nothing and shifts control to step S119. .

  On the other hand, when the count value of the step number counter 406 (the number of phase excitation patterns output from the ASIC 203) matches the set value of the deceleration step number register in the step number setting register 407 (YES in step S121). ) Since the deceleration control of the stepping motor 204 is completed, the control unit 223 of the ASIC 203 sets the current value of the stepping motor 204 to 0 so that the clock on the clock signal line 205 can be detected again. The external clock input (clock input from the clock oscillator 210 of the CPU 200) is set (step S125), and the series of processing ends (step S126).

  To summarize the control of the present embodiment, in the acceleration section of the stepping motor 204, it is synchronized with the internal clock until the count value of the step number counter 406 matches the set value of the acceleration step number register in the step number setting register 407. Thus, a phase excitation signal corresponding to the phase excitation pattern is output to the stepping motor 204. In the constant speed section of the stepping motor 204, the phase excitation pattern is synchronized with the external clock until the count value of the step number counter 406 matches the set value of the constant speed step number register in the step number setting register 407. A corresponding phase excitation signal is output to the stepping motor 204. In the deceleration zone of the stepping motor 204, the phase excitation pattern is synchronized with the internal clock until the count value of the step number counter 406 matches the set value of the deceleration step number register in the step number setting register 407. A phase excitation signal is output to the stepping motor 204.

  As described above, according to the present embodiment, the control unit 223 of the ASIC 203 transmits the phase excitation signal corresponding to the phase excitation pattern in synchronization with the internal clock of the ASIC 203 during the acceleration control of the stepping motor 204. When the stepping motor 204 is controlled at a constant speed, a phase excitation signal is output to the stepping motor 204 in synchronization with the external clock from the CPU 200. When the stepping motor 204 is controlled to be decelerated, the phase is synchronized with the internal clock of the ASIC 203. Control to output an excitation signal to the stepping motor 204 is performed.

  This makes it possible to freely switch the control device (CPU 200 or ASIC 203) that controls the stepping motor 204 according to the control target (acceleration control, constant speed control, deceleration control) of the stepping motor 204. As a result, it is possible to solve the conventional problem that the CPU resource is insufficient when changing the speed at the constant speed of the motor, and the processing time when the motor speed control is simply performed using the acceleration / deceleration table. Can do.

[Second Embodiment]
FIG. 13 is a block diagram showing the configuration of the control system of the image forming apparatus according to the second embodiment of the present invention.

  In FIG. 13, the control system of the image forming apparatus includes a CPU 700, a ROM 701, a RAM 702, an ASIC 703, and a data bus / address bus 707. The CPU 700 includes a communication control unit 711. The ASIC 703 includes a multiplexer 720, a clock oscillator 721, a control unit 723, a port register 724, a ROM 725, and a RAM 724.

  The present embodiment is connected to the CPU 700 by the multiplexer 720 in that the clock oscillator is removed from the CPU 700, the clock receiver is removed from the ASIC 703, and the multiplexer 720 is added to the first embodiment described above. The difference is that the motor control signal line and the motor control signal line inside the ASIC 703 are selectively switched. Since the other elements of the present embodiment are the same as the corresponding ones of the first embodiment (FIG. 2) described above, description thereof is omitted.

  Communication signal lines 706-1 and 706-2 are connected between the communication control unit 711 of the CPU 700 and the control unit 723 of the ASIC 703. The communication signal line 706-1 is a signal line for transmitting data from the CPU 700 to the ASIC 703. A communication signal line 706-2 is a signal line for transmitting data from the ASIC 703 to the CPU 700. The control unit 723 of the ASIC 703 can receive predetermined data from the communication control unit 711 of the CPU 700 and control the stepping motor 704.

  Motor control signal lines 705-1, 705-2, 705-3, and 705-4 are connected between the CPU 700 and the multiplexer 720 of the ASIC 703. The multiplexer 720 receives a motor control signal from the CPU 700 via the motor control signal lines 705-1, 705-2, 705-3, and 705-4.

  Motor control signal lines 730, 731, 732, and 733 are connected via a multiplexer 720 between the port register 724 of the ASIC 703 and the stepping motor 704. The phase excitation pattern stored in the ROM 725 is read by the controller 223 and supplied to the motor control signal lines 730, 731, 732, and 733 via the port register 724. The phase excitation pattern stored in the ROM 725 can be set and changed from outside the ASIC 703.

  The multiplexer 720 receives a motor control signal (phase excitation signal corresponding to the phase excitation pattern) for driving the stepping motor 704 from the CPU 700 based on an instruction from the control unit 723, and motor control signal lines 705-1 to 705-4. And the motor control signal supplied from the control unit 723 via the port register 724 via the motor control signal lines 730 to 733.

  To summarize the control of the present embodiment, in the acceleration section of the stepping motor 704, the phase inside the ASIC is kept until the count value of the step number counter 406 matches the set value of the acceleration step number register in the step number setting register 407. A phase excitation signal corresponding to the excitation pattern is output to the stepping motor 704. Further, in the constant speed section of the stepping motor 704, it corresponds to the phase excitation pattern input from the CPU 700 until the count value of the step number counter 406 matches the set value of the constant speed step number register in the step number setting register 407. The phase excitation signal thus output is output to the stepping motor 704. In the deceleration zone of the stepping motor 704, the phase excitation signal corresponding to the phase excitation pattern in the ASIC until the count value of the step number counter 406 matches the set value of the deceleration step number register in the step number setting register 407. Is output to the stepping motor 704.

  As described above, according to the present embodiment, the motor control signal (the phase corresponding to the phase excitation pattern) for driving the stepping motor 704 in accordance with the acceleration / constant speed / deceleration sections of the stepping motor 704. The four motor control signal lines (motor control signal lines 705-1 to 705-4 or motor control signal lines 730 to 733) that output the excitation signal are switched by the multiplexer 720.

  This makes it possible to freely switch the control device (CPU 700 or ASIC 703) that controls the stepping motor 704 in accordance with the control target (acceleration control, constant speed control, deceleration control) of the stepping motor 704. As a result, it is possible to solve the conventional problem that the CPU resource is insufficient when changing the speed at the constant speed of the motor, and the processing time when the motor speed control is simply performed using the acceleration / deceleration table. Can do.

[Other embodiments]
In the first embodiment, the acceleration interval and the deceleration interval of the stepping motor 204 output a phase excitation signal corresponding to the phase excitation pattern in synchronization with the internal clock of the ASIC 203, and the constant velocity interval of the stepping motor 204 is A method of outputting a phase excitation signal corresponding to the phase excitation pattern in synchronization with the external clock from the CPU 200 (in the case of FIG. 4B) was used. However, when the processing load of the CPU 200 increases in the acceleration section and the deceleration section, the acceleration section and the deceleration section output a phase excitation signal corresponding to the phase excitation pattern in synchronization with the external clock from the CPU 200, and the constant speed For the section, a method of outputting a phase excitation signal in synchronization with the internal clock of the ASIC 203 (in the case of FIG. 4C) may be used.

  In the second embodiment, the acceleration interval and the deceleration interval of the stepping motor 704 output phase excitation signals corresponding to the phase excitation pattern inside the ASIC via the motor control signal lines 730 to 733, and the stepping motor 704 For the constant velocity section, a method of outputting a phase excitation signal corresponding to the phase excitation pattern input from the CPU 700 via the motor control signal lines 705-1 to 705-4 was used. However, when the processing load on the CPU 700 increases in the acceleration section and the deceleration section, the acceleration section and the deceleration section correspond to the phase excitation pattern input from the CPU 700 via the motor control signal lines 705-1 to 705-4. A method may be used in which the phase excitation signal is output and the phase excitation signal corresponding to the phase excitation pattern in the ASIC is output via the motor control signal lines 730 to 733 in the constant velocity section.

  In the first and second embodiments, the CPU and the ASIC are used to control the stepping motor. However, the present invention is not limited to the configuration using the CPU and the ASIC. Any configuration can be used as long as it uses two control devices to control the stepping motor and controls the stepping motor while switching between the two control devices.

  In the first and second embodiments, the example in which the motor control device of the present invention is applied to an image forming apparatus (copier) has been described. However, the present invention is not limited to application only to a copier. The motor control apparatus of the present invention can be applied to an image forming apparatus (printer, multifunction machine) other than a copying machine, an image communication apparatus (facsimile), or the like.

  The present invention supplies a software program (flowcharts in FIGS. 10 to 12) for realizing the functions of the above-described embodiments to a computer or CPU, and the computer or CPU reads and executes the supplied program. Can be achieved.

  In this case, the program is directly supplied from a storage medium storing the program, or downloaded from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like. Supplied.

  The form of the program may be in the form of object code, program code executed by an interpreter, script data supplied to an OS (operating system), and the like.

  The present invention also supplies a computer or CPU with a storage medium storing a software program that implements the functions of the above-described embodiments, and the computer or CPU reads and executes the program stored in the storage medium. Can also be achieved.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  As a storage medium for storing the program code, for example, ROM, RAM, NV-RAM, floppy (registered trademark) disk, hard disk, optical disk (registered trademark), magneto-optical disk, CD-ROM, MO, CD-R, CD -RW, DVD-ROM, DVD-RAM, DVD-RW, DVD + RW, magnetic tape, nonvolatile memory card, etc.

  The function of the above-described embodiment is not only by executing the program code read from the computer, but the OS or the like running on the computer performs part or all of the actual processing based on the instruction of the program code. Can also be realized.

1 is a configuration diagram showing an internal structure of an image forming apparatus according to a first embodiment of the present invention. 2 is a block diagram illustrating a configuration of a control system of the image forming apparatus. FIG. 3 is a timing chart illustrating a method for driving a stepping motor of the image forming apparatus. (A) is a figure which shows the speed change at the time of acceleration / constant speed / deceleration of a stepping motor, (b), (c) shows the relationship between the data which flow on the communication signal line between CPU and ASIC, and a clock signal line. FIG. It is a figure which shows a structure required in order that the control part of ASIC may control a stepping motor. It is a figure which shows the basic structure of the transmission / reception data between CPU and ASIC. It is a figure which shows a stepping motor starting command and a stepping motor starting response command. It is a figure which shows a stepping motor stop command and a stepping motor stop response command. It is a figure which shows the motor sequence setting command and motor sequence setting response command of a stepping motor. It is a flowchart which shows the clock switching control with respect to the stepping motor by the control part of ASIC. It is a continuation of the flowchart of FIG. It is a continuation of the flowchart of FIG. FIG. 6 is a block diagram illustrating a configuration of a control system of an image forming apparatus according to a second embodiment of the present invention.

Explanation of symbols

200 CPU (external to motor controller)
203 ASIC (corresponding to motor control device)
204 Stepping motor (compatible with phase excitation motor)
220 Clock receiver (corresponding to receiving means)
221 Clock oscillator (corresponding to generating means)
223 control unit (corresponding to selection means)
224 port register (corresponding to output means)
406 Step number counter (corresponding to counting means)
407 Step number setting register (corresponding to acceleration setting means, constant speed setting means, deceleration setting means)
700 CPU (external to motor controller)
703 ASIC (corresponding to motor control device)
704 Stepping motor (compatible with phase excitation motor)
705-1 to 705-4 Motor control signal line (corresponding to external supply means)
720 Multiplexer (corresponding to selection means)
725 port register (corresponding to output means)
730-733 Motor control signal line (corresponding to internal supply means)

Claims (10)

A motor control device for driving and controlling a phase excitation motor,
Generating means for generating a clock;
Receiving means for receiving a clock input from outside the motor control device;
Selection means for selectively switching between the clock generated by the generation means and the clock received by the reception means according to the control target state of the motor;
A motor control apparatus comprising: output means for outputting a phase excitation signal corresponding to a phase excitation pattern to the motor while synchronizing with a clock selected by the selection means. Acceleration setting means for setting the number of clocks required for acceleration of the motor;
Constant speed setting means for setting the number of clocks required for constant speed driving of the motor;
Deceleration setting means for setting the number of clocks required for the deceleration and stop of the motor;
Counting means for counting the number of phase excitation signals output to the motor;
Until the count value of the counting means matches the set value of the acceleration setting means, a phase excitation signal is output in synchronization with the clock generated by the generating means,
Until the count value of the counting means matches the set value of the constant velocity setting means, the phase excitation signal is output in synchronization with the clock received by the receiving means,
2. The motor control device according to claim 1, wherein a phase excitation signal is output in synchronization with a clock generated by the generating means until a count value of the counting means coincides with a set value of the deceleration setting means. Acceleration setting means for setting the number of clocks required for acceleration of the motor;
Constant speed setting means for setting the number of clocks required for constant speed driving of the motor;
Deceleration setting means for setting the number of clocks required for the deceleration and stop of the motor;
Counting means for counting the number of phase excitation signals output to the motor;
Until the count value of the counting means matches the set value of the acceleration setting means, a phase excitation signal is output in synchronization with the clock received by the receiving means,
Until the count value of the counting means matches the set value of the constant speed setting means, a phase excitation signal is output in synchronization with the clock generated by the generating means,
2. The motor control device according to claim 1, wherein a phase excitation signal is output in synchronization with a clock received by the receiving means until a count value of the counting means coincides with a set value of the deceleration setting means. A motor control device for driving and controlling a phase excitation motor,
An internal supply means for supplying a phase excitation pattern;
An external supply means for supplying a phase excitation pattern inputted from the outside of the motor control device;
A selection means for selectively switching between a phase excitation pattern supplied by the internal supply means and a phase excitation pattern supplied by the external supply means according to a control target state of the motor;
A motor control apparatus comprising: output means for outputting a phase excitation signal corresponding to the phase excitation pattern selected by the selection means to the motor. Acceleration setting means for setting the number of clocks required for acceleration of the motor;
Constant speed setting means for setting the number of clocks required for constant speed driving of the motor;
Deceleration setting means for setting the number of clocks required for the deceleration and stop of the motor;
Counting means for counting the number of phase excitation signals output to the motor;
Output a phase excitation signal corresponding to the phase excitation pattern supplied by the internal supply means until the count value of the counting means matches the set value of the acceleration setting means,
Output a phase excitation signal corresponding to the phase excitation pattern supplied by the external supply means until the count value of the counting means matches the set value of the constant speed setting means,
5. The motor according to claim 4, wherein a phase excitation signal corresponding to the phase excitation pattern supplied by the internal supply means is output until a count value of the counting means matches a set value of the deceleration setting means. Control device. Acceleration setting means for setting the number of clocks required for acceleration of the motor;
Constant speed setting means for setting the number of clocks required for constant speed driving of the motor;
Deceleration setting means for setting the number of clocks required for the deceleration and stop of the motor;
Counting means for counting the number of phase excitation signals output to the motor;
Output a phase excitation signal corresponding to the phase excitation pattern supplied by the external supply means until the count value of the counting means matches the set value of the acceleration setting means,
Until the count value of the counting means matches the set value of the constant speed setting means, a phase excitation signal corresponding to the phase excitation pattern supplied by the internal supply means is output,
5. The motor according to claim 4, wherein a phase excitation signal corresponding to a phase excitation pattern supplied by the external supply means is output until a count value of the counting means matches a set value of the deceleration setting means. Control device.   The motor control device according to claim 1, wherein the phase excitation pattern can be set and changed from outside the motor control device.   An image forming apparatus comprising the motor control device according to claim 1. A control method of a motor control device that drives and controls a phase excitation motor,
Generating step for generating a clock inside the motor control device;
A receiving step of receiving a clock input to the motor control device from outside the motor control device;
A selection step of selectively switching between the clock generated by the generation step and the clock received by the reception step according to the control target state of the motor;
And a step of outputting a phase excitation signal corresponding to a phase excitation pattern to the motor while synchronizing with the clock selected in the selection step. A program for causing a computer to execute a control method of a motor control device that drives and controls a phase excitation motor,
A generation module for generating a clock inside the motor control device;
A receiving module for receiving a clock input to the motor control device from the outside of the motor control device;
A selection module that selectively switches between a clock generated by the generation module and a clock received by the reception module in accordance with a control target state of the motor;
A program comprising: an output module for outputting a phase excitation signal corresponding to a phase excitation pattern to the motor while synchronizing with a clock selected by the selection module.

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