JPH04247760A - Image forming device - Google Patents

Abstract

PURPOSE:To attain miniaturization and to reduce the cost by reducing number of signal lines used for signal transmission reception in the inside of the image forming device. CONSTITUTION:An engine driver 60 is provided with a signal synthesis circuit 80 being a transmission means and a controller 50 is provided with a signal separate circuit 90 being a reception means respectively and a horizontal synchronizing signal LSYNC and a vertical synchronizing signal FSYNC sent from the engine driver 60 to the controller 50 having been sent through other signal line in the conventional system are synthesized into a synthesis signal LSYNC/ FSYNC and the result is communicated through one signal line.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus equipped with first and second control devices that function by transmitting and receiving a plurality of signals to and from each other.

0002

2. Description of the Related Art For example, there are image forming apparatuses such as laser printers (also called laser beam printers), digital copying machines, and color copying machines that form images on plain paper using electrostatic latent image technology.

[0003] Generally, such an image forming apparatus mainly includes an engine driver that controls a mechanical section that forms an image, or a controller that processes image data, inputs instructions from external equipment or an operator, or outputs messages. A control device is built in, and these control devices function effectively by transmitting and receiving various signals to and from each other through a plurality of signal lines to determine timing.

[0004] These signals are disclosed in, for example, Japanese Patent Application Laid-Open No. 2-153.
As in the example shown in FIG. 12 of Publication No. 762 or the conventional example shown in FIG. It was being sent and received. As image forming devices become faster and more sophisticated, the number of signals increases.
Therefore, there is a tendency for the number of signal lines to increase.

[0005] On the other hand, as a similar technology, there is a TV device as disclosed in Japanese Patent Laid-Open No. 2-186393, in which luminance signals and An image signal consisting of two types of color signals I and Q and both horizontal and vertical synchronization signals are transmitted and received through one signal line.

[0006]

[Problems to be Solved by the Invention] However, there is a strong desire for image forming apparatuses to be more compact as well as to have higher performance.To achieve this, it is necessary to reduce the number of internal signal lines as much as possible to save space including connectors. It is necessary to aim for

[0007] Considering only the number of signal lines, the communication technology for TV equipment is most desirable; It is a composite signal in which a quadrature-modulated color signal is superimposed on a luminance signal, and horizontal and vertical synchronization signals with different waveforms are combined with opposite polarities, so complex circuits are required to combine and separate the signals. Due to cost considerations, this method cannot be applied to signal transmission and reception within the same device.

The present invention has been made in view of the above points, and an object of the present invention is to reduce the number of signal lines and contribute to miniaturization and cost reduction of the device.

[0009]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an image forming apparatus including first and second control devices that function by transmitting and receiving a plurality of signals to and from each other. In the apparatus, the first control device is provided with a transmitting means for combining a horizontal synchronizing signal and a vertical synchronizing signal and transmitting the combined signal through the same signal line.

The transmitting means is a first pulse signal that generates a first pulse signal having a predetermined pulse width in accordance with the horizontal synchronizing signal.
a second pulse signal generating means for generating a second pulse signal having a pulse width different from the pulse width of the first pulse signal in accordance with the vertical synchronization signal; It is preferable to include a pulse width modulation signal synthesizing means for synthesizing and outputting pulse signals.

[0011] The transmitting means also includes a first pulse signal generating means for generating a first pulse signal having a predetermined amplitude in accordance with a horizontal synchronizing signal, and a first pulse signal generating means for generating a first pulse signal having a predetermined amplitude in accordance with a vertical synchronizing signal. It may be configured by a second pulse signal generating means that generates second pulse signals having different amplitudes, and an amplitude modulated signal synthesizing means that synthesizes and outputs the first and second pulse signals.

[0012] The second invention provides an image forming apparatus including first and second control devices that function by transmitting and receiving a plurality of signals to and from each other. It is provided with a receiving means that separates the signal and outputs it as a horizontal synchronization signal and a vertical synchronization signal, respectively.

The receiving means separates the input signal into first and second pulse signals according to the pulse width, and uses the first pulse signal as a horizontal synchronizing signal and the second pulse signal as a vertical synchronizing signal, respectively. It is preferable to configure the output signal pulse width determination means.

Further, the receiving means separates the input signal into first and second pulse signals according to the amplitude, and outputs the first pulse signal as a horizontal synchronizing signal and the second pulse signal as a vertical synchronizing signal, respectively. It may also be configured by a signal amplitude discriminating means.

[0015]

[Operation] According to the first invention, the transmitting means provided in the first control device generates a first pulse signal having a predetermined pulse width or amplitude in response to a horizontal synchronizing signal. The second pulse signal generating means generates a second pulse signal having a pulse width or amplitude different from that of the first pulse signal in accordance with the vertical synchronization signal, and generates a pulse width modulated signal. Since the combining means or the amplitude modulated signal combining means combines and outputs the first and second pulse signals, the two signals can be transmitted on the same signal line.

According to the second invention, in the receiving means provided in the second control device, the signal pulse width determining means or the signal amplitude determining means determines the pulse width or amplitude of the signal input from the same signal line. The first pulse signal is divided into a horizontal synchronizing signal and the second pulse signal is divided into a first pulse signal and a second pulse signal, respectively.
Since each pulse signal is output as a vertical synchronization signal, two signals can be received independently from the same signal line.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings.

FIG. 4 is a schematic diagram showing the internal mechanism of a laser printer according to an embodiment of the present invention. A charging charger 11, an optical writing unit 12, a developing unit 13, a transfer charger 14, and a cleaning unit 15 are arranged around the photosensitive drum 10, which rotates counterclockwise as shown by the arrow, in the order of the rotational direction. There is.

The surface of the photosensitive drum 10 is first uniformly charged by a charging charger 11, and then a spot is formed on which a beam modulated by image data from an optical writing unit 12 and deflected in the main scanning direction forms an image. main scanning is performed, and an electrostatic latent image is formed. The electrostatic latent image is developed by the developing unit 13 and converted into a visualized toner image, and then the toner image is transferred by the transfer charger 14 onto a sheet of paper conveyed along the route shown by the dashed line. be done.

The toner and charge remaining on the photosensitive drum 10 are removed by a cleaning unit 15, and the removed toner is collected by the cleaning unit 15.

The paper is fed from a paper stack 18 on a paper feed cassette 17, which is a paper storage section, by a paper feed roller 19, which is a paper feeding means, and its leading end is brought into contact with a registration sensor 2.
7, the paper feed roller 19 stops at a timing when the paper is further fed until the leading end comes into contact with the pair of registration rollers 20, and the feeding cycle ends.

Next, timing is taken to match the image written on the photosensitive drum 10 by the optical writing unit 12, and the transfer charger 14 is moved by the registration roller pair 20.
The paper is conveyed to the position shown in FIG. It rotates idly according to the conveyance and does not interfere with the conveyance.

The paper onto which the toner image has been transferred is conveyed to the fixing unit 21, pressed against the heated fixing roller 21a by the pressure roller 21b, and fixed by the heat and pressure. The paper is transported to output port 2.
3 and is discharged onto the paper discharge tray 24.

FIG. 5 is a perspective view of essential parts of an example of the optical writing unit 12. As shown in FIG. The optical writing unit 12 includes an LD (laser diode) unit 30 which is a modulated light source, a first cylinder lens 31, a first mirror 32, a pre-object type imaging lens 33, a polygon motor 34, and an arrow A rotating deflector 36 consisting of a polygon mirror 35 rotationally driven in the direction of A, a scanning imaging optical system consisting of a second mirror 37 and a second cylinder lens 38, a third mirror 40, a light receiving lens 41, and a synchronization system. sensor 42
It is composed of a synchronous optical system consisting of.

The LD unit 30 includes a laser diode (hereinafter also referred to as "LD") inside, a collimator lens that converts the diverging beam emitted from the LD into a parallel light beam, and an aperture that regulates the thickness of the beam. It is a combination of the following. The parallel light beam emitted from the LD unit 30 is transmitted through the first cylinder lens 31 and
After being reflected by the mirror 32, the light passes through the imaging lens 33 and enters the reflective surface 35a of the polygon mirror 35.

The imaging lens 33 functions to form an image of the parallel main scanning direction component of the incident beam on the photosensitive drum 10, which will be described later. The power acts to once image the sub-scanning direction component of the parallel beam onto the reflective surface 35a of the polygon mirror 35.

The beam reflected by the polygon mirror 35 and repeatedly deflected in the main scanning direction is reflected by the second mirror 37, passes through the second cylinder lens 38, and reaches the photosensitive drum 10 rotating in the direction of arrow B. do. The second cylinder lens 38 re-images the sub-scanning direction component of the beam once imaged on the reflecting surface 35a onto the photoreceptor drum 10, so that the beam is focused in the main scanning direction where it is imaged by the imaging lens 33. The image is formed into a spot along with the components, and main scanning is performed on the main scanning line 10a of the photosensitive drum 10 in the direction of arrow C.

[0028] Immediately before the beam deflected by the rotary deflector 36 enters the effective image area on the main scanning line 10a, the beam is reflected by the third mirror 40 and focused on the light receiving surface by the light receiving lens 41. A synchronization sensor 42 that outputs a main scanning synchronization signal is also provided.

FIG. 6 is a block diagram showing an example of the control system of this laser printer. The engine driver 60 is
A microcomputer (hereinafter referred to as "CPU") 61, a ROM 62 that stores programs and constant data required by the CPU 61, a RAM 63 that stores temporary data, and an I/O device that controls data input and output. A certain optical writing control unit 45, MM (main motor) driver 71, PM (polygon motor) driver 72, paper feed CL
It is composed of a driver 74 and a resist CL driver 76.

The controller 50 receives print commands, character codes, and image data from the host machine 58, and
After editing those codes and data and converting character codes into dot patterns necessary for writing images using character fonts, the dot patterns of those characters and images (hereinafter collectively referred to as "images") are built-in (not shown). Store it in memory in VRAM (video RAM).

Ready signal PE from engine driver 60
DTR, vertical synchronization signal FSYNC, horizontal synchronization signal LSY
When the image clock WCLK is input together with NC, the controller 50 converts the dot pattern stored in the VRAM into an image signal WD synchronized with the image clock WCLK.
It is output to the engine driver 60 as ATA.

The engine driver 60 is connected to the controller 5
0, the sequence equipment group such as the optical writing unit 12 of the printer engine is controlled, and the optical writing unit 12 converts the image signal WDATA input from the controller 50 into the signal VIDEO necessary for image writing.
It also inputs and processes signals indicating the status of each part of the engine from the synchronous sensor 42 and other sensors, and outputs necessary information and error signals to the controller 50.

Paper size switch 26, registration sensor 27, main motor 70, paper feed clutch 73, registration clutch 75, polygon motor 34, and synchronization sensor 42 of optical writing unit 12, laser diode (LD) 43, which constitute the printer engine. , LD driver 44 directly or via a driver, the engine driver 60
is connected to the CPU 61 or the controller 50.

When the controller 50 receives the print command, character code, and image data from the host machine 58, the controller 50 sends a reception ready signal PEDT of the engine driver 60.
R is confirmed and a print operation start is commanded, and the specified pixel density is transmitted from the host machine 58 or an operation panel (not shown), and a bitmap of the edited image is formed on the VRAM.

[0035] The CPU 61 of the engine driver 60
The start signal MMST of the M driver 71 is turned on, and the rotation speed corresponding to the pixel density is instructed to the PM driver 72, and the start signal PMST is turned on.

The MM driver 71 receives the start signal MMS
By inputting T, the main motor 70, which is a common power source for each part of the printer, is controlled to rotate at a constant speed. PM driver 72
inputs the start signal PMST and synchronously controls the polygon motor 34 to maintain the specified rotation speed,
When the signal FG from the polygon motor 34 is detected and the synchronization is maintained, the signal PMLK indicating that the lock is in progress is sent to C.
Output to PU61.

On the other hand, the CPU 61 determines the paper size indicated by the notch (not shown) of the attached paper feed cassette 17,
Read the direction code with the paper size switch 26,
The desired paper is selected by the signals PS0 to PS3 and the signal FDCL to the corresponding paper feed CL driver 74 is turned on, so the paper feed clutch 73 that connects the paper feed roller 19 and the main motor 70 is activated. , paper feed roller 19
When the registration sensor 27 detects the paper fed from the paper feed cassette 17, the paper feed roller 19 is stopped.

The CPU 61 receives the signal RGSNR from the registration sensor 27 and the signal PMLK from the PM driver 72.
When this is confirmed, a signal FSYN to start sub-scanning writing (writing for one page) is sent to the controller 50 via the optical writing control unit 45.
C, and then outputs the signal RGC after a predetermined timing.
L is output, the resist CL driver 76 is turned on, the resist clutch 75 is operated, and the resist roller pair 20 is turned on.
is rotated to convey the paper to the photosensitive drum 10.

When the signal FSYNC is input, the controller 50 outputs the image data WDATA to the optical write control unit in synchronization with the image clock WCLK in accordance with the horizontal synchronization signals LGATE and LSYNC input from the optical write control unit 45 after a predetermined time. 45. The optical write control unit 45 converts the data WDATA into a pulse signal VIDEO and outputs it to the LD driver 44, and the LD driver 44 receives the input signal V while the signal LGATE indicating the main scanning write period is "H".
By controlling the drive current of the laser diode 43 on and off according to IDEO, one line of image is written, and this is repeated for each horizontal synchronization signal LSYNC.
Optical writing for pages is performed.

Note that before starting writing for one page, a photoelectric conversion element such as a phototransistor (not shown) built in the laser diode 43 monitors its optical output, and the LD
The signal LDCT converted from A/D by the driver 44 is fed back to the optical writing control section 45 or the CPU 61, thereby controlling the optical output of the laser diode 43 to a predetermined power.

FIG. 1 shows a controller 50 and an engine driver 60 in order to smoothly perform the above operations in this embodiment.
FIG. 2 is a block diagram illustrating an example of a signal line that transmits each signal and data transmitted and received between the two.

That is, the engine driver 60, which is the first control device, is provided with a signal synthesis circuit 80, which is a transmitting means, and receives a horizontal synchronizing signal LS indicating the start of writing for one line.
YNC and vertical synchronization signal FSYN indicating the start of writing for one page
C is the composite signal L synthesized by the signal synthesis circuit 80.
SYNC/FSYNC, engine driver 60
(optical write control unit 45) is outputted to one signal line.

Further, the controller 50, which is the second control device, is provided with a signal separation circuit 90, which is a receiving means.
The composite signal LSYNC/FSYNC received from the engine driver 60 via one signal line is separated into a horizontal synchronization signal LSYNC and a vertical synchronization signal F by the signal separation circuit 90.
SYNC and input, respectively.

Other signals and data that the engine driver 60 transmits to the controller 50 are the transmission data PETXD, the reception ready signal PEDTR, the image clock WCCK, and the horizontal write area signal LGATE, and the signals and data received from the controller 50 are The data is received data P
ERXD, transmission ready signal PECTS, image data WD
It is ATA.

FIGS. 2 and 3 show the signal synthesis circuit 8, respectively.
0 is a block diagram showing an example of a signal separation circuit 90. FIG.

The signal synthesis circuit 80 shown in FIG.
Consisting of an NC generation circuit 81, an FSYNC generation circuit 82, and a synthesis circuit 83, the LSYNC generation circuit 81 outputs a horizontal synchronization signal LSYNC having a predetermined pulse width and amplitude according to the timing signal DETP input from the synchronization sensor 42, The generation circuit 82 outputs a vertical synchronization signal FSYNC having a predetermined pulse width and amplitude according to the timing signal Fsync input from the CPU 61.

The synthesis circuit 83 is an LSYNC generation circuit 81
The signals LSYNC and FSYNC input from the FSYNC generation circuit 82 and FSYNC generation circuit 82 are synthesized depending on whether the pulse widths or amplitudes are different from each other, and a synthesized signal LSYNC/F is generated.
SYNC is output to the controller 50. In addition, FSY
The NC generation circuit 82 is omitted and the signal Fsync outputted by the CPU 61 is directly used as the signal FSYNC in the synthesis circuit 8.
3 may be entered.

The signal separation circuit 90 shown in FIG. 3 separates the first pulse signal, that is, the horizontal It is separated into a synchronizing signal LSYNC and a second pulse signal, that is, a vertical synchronizing signal FSYNC.

FIGS. 7 and 8 show a first embodiment of the combining circuit 83 and signal separating circuit 90 shown in FIGS. 2 and 3, respectively, in which two pulse signals have the same amplitude and different pulse widths. Synthesizing circuit 83a and signal separating circuit 9 in case
Indicates 0a. In this first embodiment, the LSY shown in FIG.
Since the NC generating circuit 81 and the FSYNC generating circuit 82 may be configured by, for example, known monostable multi-circuits having mutually different time constants, illustrations and explanations will be omitted.

FIG. 9 is a waveform diagram showing an example of the signals of each part of the circuit shown in FIGS. 7 and 8, and shows an example where the pulse width of the signal FSYNC is longer than the pulse width of the signal LSYNC. Signals FSYNC, LSYNC before synthesis, combined signals LSYNC/FSYNC, respective outputs of two monostable multi (circuits) 91, 92 and D-FF (flip-flop circuit) 93, separated synchronization signals FSYNC, LSYNC
are shown respectively. Further, A and B in FIG. 9 respectively show an example where the signals FSYNC and LSYNC are separated, and where they are continuous or overlap.

The synthesis circuit 83a shown in FIG. 7 consists of one OR circuit, and its synthesis operation is clear from FIG. 9, so a description thereof will be omitted.

The signal separation circuit 90a shown in FIG. 8 is a monostable (MS) multi-channel circuit 91 that operates at the rising edge of the input composite signal and outputs a pulse signal having a pulse width longer than the signal LSYNC and shorter than the signal FSYNC. , a monostable multi 92 that operates at the falling edge of its output pulse signal and outputs the reference pulse signal of the separated synchronization signal, and D that similarly latches the composite signal inputted at the falling edge of the output pulse signal of the monostable multi 91. -FF93, the reference pulse signal output by the monostable multi 92, and the output Q or /Q of the D-FF93 are respectively input, and the separated synchronization signals FSYNC and LSYNC are input.
It is composed of two AND circuits 94 and 95 that output .

As shown in FIG. 9, the monostable multi 91 sends a single pulse signal P91 to the monostable multi 92 and D-F every time the input composite signal LSYNC/FSYNC rises.
Output to F93. The monostable multi 92 outputs a reference pulse signal Pr having a predetermined pulse width to the AND circuits 94 and 95 in response to the fall of the input pulse signal P91.

At the same time, the D-FF93 receives the pulse signal P91.
The input composite signal is latched at the falling edge of the pulse signal P91, but the pulse width of the pulse signal P91 is longer than the signal LSYNC, and the signal F
Since it is set shorter than SYNC, when the signal FSYNC (A in Figure 9) or both signals are input as a composite signal (A in Figure 9) or both signals are input consecutively or overlapped (B in Figure 9), the output Q is "H" and the signal LSYNC is When input, output/Q is “H”
"become.

The AND circuit 94 or 95 includes a D-FF4
Since the output Q or /Q of 3 and the reference pulse signal Pr are inputted, each acts as a gate circuit for the reference pulse signal Pr, and when the output Q is "H", the second
The separated vertical synchronization signal FSYNC is a pulse signal of
However, when the output /Q is "H", the separated horizontal synchronizing signal LSYNC, which is the first pulse signal, is output from the AND circuit 95 as a separate synchronizing signal.

As explained above and as is clear from FIG. 9, the rise of the separated synchronization signals FSYNC and LSYNC is delayed by the pulse width of the pulse signal P91 from the rise of the original synchronization signals FSYNC and LSYNC, respectively, and the delay time is There is no problem because it is always constant. Also, B in Figure 9
As shown in , when the original synchronization signals overlap, the separate horizontal synchronization signal LSYNC is not output, but the vertical synchronization signal FSYNC is output once at the beginning of printing one page; Sometimes horizontal synchronization signal LSY
There is no need for NC and there is no problem.

FIGS. 10 and 11 show a second embodiment of the combining circuit 83 and signal separating circuit 90 shown in FIGS. 2 and 3, respectively, that is, a combining circuit 83b when the amplitudes of two pulse signals are different from each other. and a signal separation circuit 90b.

FIG. 12 is a waveform diagram showing an example of signals of each part of the circuit shown in FIGS. 10 and 11.
An example is shown in which the amplitude of the signal FSYNC is larger than that of the signal LSYNC.
2A and 2B, the combined signal LSYNC/FSYNC, the outputs of the two comparators 97 and 98, and the exclusive OR circuit 99, that is, the separated synchronization signals FSYNC and LSYNC, are shown. Similarly to FIG. 9, FIGS. 12A and 12B show an example in which the signals FSYNC and LSYNC are separated from each other, and in which they are continuous or overlap.

As shown in FIG. 10, the synthesizing circuit 83b consists of two known voltage converting circuits 84 that change only the amplitude of the signals LSYNC and FSYNC while keeping their pulse widths the same.
, 85, diodes D1 and D2 connected in the forward direction to the outputs of the voltage conversion circuits 84 and 85, respectively, and a resistor R0 provided between the mutually connected output terminals of the diodes D1 and D2 and the ground. It is composed of.

As shown in FIG. 12, the signal LSYNC with a small amplitude, ie, a low voltage, and the signal FSYNC, which has a large amplitude, ie, a high voltage, output from the voltage conversion circuits 84 and 85, respectively, are connected to diodes D1 and D2, respectively. Because they are connected through the resistor R0, both signals appear independently at the resistor R0 as shown in A of Figure 12, but as shown in B of the same figure, a voltage appears in the overlapped part of the two signals. The higher signal FSYNC appears and they form the composite signal LSYNC
/FSYNC is output from the synthesis circuit 83b.

As shown in FIG. 11, the signal separation circuit 90b includes a voltage divider 96 consisting of resistors R1, R2, and R3, two comparators 97, 98, and
8, and an exclusive OR circuit 99 that takes the exclusive OR of the outputs of 8.

A voltage divider 96 is connected to the negative terminal of the comparator 97.
The signal LS is lower than the signal FSYNC before synthesis from
A reference voltage higher than YNC is applied to the - terminal of the comparator 98, a reference voltage lower than the pre-combined signal FSYNC and higher than "0" is applied to the - terminal of the comparator 98, and a combined signal LSYNC/FSYN is applied to each + terminal of the comparator 98.
C are input, respectively, and separate synchronization signals FSYNC and LSY are input from the comparator 97 and the exclusive OR circuit 99, respectively.
NC is output.

That is, the outputs CP1 and CP2 of the comparators 97 and 98 with respect to the level of the input composite signal,
Table 1 shows a logic table for the output EXOR of the exclusive OR circuit 99. CP1 and EXOR are each separate synchronization signal FSYN
C, LSYNC.

[0064]

[Table 1]

Therefore, as shown in FIG. 12, the composite signal LSYNC/FSYNC is the separated synchronizing signal FSYNC
, LSYNC and output.

In this second embodiment, no phase delay occurs as in the first embodiment. In addition, in the overlapped state as shown in FIG. 12B, the separated horizontal synchronizing signal LSYN
The pulse width of C may be reduced or disappear, but the first
As explained in the embodiment, there is no difference.

As explained above, according to the present invention,
Since the number of signal lines can be reduced by simply adding a simple circuit, costs including connectors can be reduced, and the main device can be made smaller.

Furthermore, in the signal separation circuit 90a of the first embodiment, a circuit using two monostable multis 91, 92, AND circuits 94, 95, and a D-FF 93 has been described; If the processing is performed by software using a CPU (not shown), all parts become unnecessary. Also in the second embodiment, the synthesis circuit 83b
The voltage conversion circuit 84 may be abolished and a voltage divider may be used for the voltage conversion circuit 85, and the signal separation circuit 90b may be replaced by the controller 5.
It is also possible to further reduce costs and save space by processing with a CPU within 0.

[0069]

As described above, the image forming apparatus according to the present invention can reduce the number of signal lines, thereby reducing the size and cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a signal line of a laser printer according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of the signal synthesis circuit shown in FIG. 1;

FIG. 3 is a block diagram showing an example of the signal separation circuit shown in FIG. 1;

FIG. 4 is a schematic configuration diagram showing an example of an internal mechanism of a laser printer that is an embodiment of the present invention.

FIG. 5 is a perspective view of essential parts of an example of the optical writing unit in FIG. 4;

6 is a block diagram showing an example of a control system of the laser printer shown in FIG. 4. FIG.

FIG. 7 is a circuit diagram showing a first embodiment of the synthesis circuit shown in FIG. 2;

FIG. 8 is a circuit diagram showing a first embodiment of the signal separation circuit shown in FIG. 3;

9 is a waveform diagram showing an example of signals of each part of the circuit shown in FIGS. 7 and 8; FIG.

FIG. 10 is a circuit diagram showing a second embodiment of the synthesis circuit shown in FIG. 2;

FIG. 11 is a circuit diagram showing a second embodiment of the signal separation circuit shown in FIG. 3;

12 is a waveform diagram showing an example of signals of each part of the circuit shown in FIGS. 10 and 11. FIG.

FIG. 13 is a block diagram showing a conventional example of the configuration of a signal line of a laser printer.

[Explanation of symbols]

50 Controller (second control means) 60 Engine driver (first control means) 80 Signal synthesis circuit (transmission means) 81 LSYNC generation circuit (first pulse signal generation means) 82 FSYNC generation circuit (second pulse signal generation means) generation means) 83 synthesis circuit 83a synthesis circuit (pulse width modulation signal synthesis means) 83
b Synthesizing circuit (amplitude modulated signal synthesizing means) 90 Signal separating circuit (receiving means) 90a Signal separating circuit (receiving means, signal pulse width determining means)

Claims (6)

[Claims] 1. An image forming apparatus comprising first and second control devices that function by transmitting and receiving a plurality of signals to and from each other, wherein the first control device combines a horizontal synchronization signal and a vertical synchronization signal. What is claimed is: 1. An image forming apparatus comprising a transmitting means for transmitting signals on the same signal line. 2. The transmitting means includes first pulse signal generating means for generating a first pulse signal having a predetermined pulse width in response to the horizontal synchronizing signal, and first pulse signal generating means for generating the first pulse signal having a predetermined pulse width in response to the vertical synchronizing signal. a second pulse signal generating means for generating a second pulse signal having a pulse width different from the pulse width of the pulse signal; and a pulse width modulated signal synthesizing means for synthesizing and outputting the first and second pulse signals. The image forming apparatus according to claim 1, comprising: 3. The transmitting means includes first pulse signal generating means for generating a first pulse signal having a predetermined amplitude in response to the horizontal synchronizing signal, and first pulse signal generating means for generating a first pulse signal having a predetermined amplitude in response to the vertical synchronizing signal. A second pulse signal generating means for generating a second pulse signal having an amplitude different from the amplitude of the pulse signal, and an amplitude modulated signal synthesizing means for synthesizing and outputting the first and second pulse signals. The image forming apparatus according to claim 1. 4. An image forming apparatus comprising first and second control devices that function by transmitting and receiving a plurality of signals to and from each other, wherein signals input from the same signal line to the second control device are separated. An image forming apparatus comprising: receiving means for respectively outputting a horizontal synchronizing signal and a vertical synchronizing signal. 5. The receiving means separates the input signal into first and second pulse signals according to the pulse width of the input signal, and uses the first pulse signal as a horizontal synchronization signal and the second pulse signal as a vertical synchronization signal. 5. The image forming apparatus according to claim 4, further comprising signal pulse width determining means for respectively outputting the synchronizing signals. 6. The receiving means separates the input signal into first and second pulse signals according to the amplitude of the input signal;
5. The image forming apparatus according to claim 4, further comprising signal amplitude determining means for outputting the pulse signal as a horizontal synchronizing signal and the second pulse signal as a vertical synchronizing signal.