JP2006032531A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2006032531A
JP2006032531A JP2004207089A JP2004207089A JP2006032531A JP 2006032531 A JP2006032531 A JP 2006032531A JP 2004207089 A JP2004207089 A JP 2004207089A JP 2004207089 A JP2004207089 A JP 2004207089A JP 2006032531 A JP2006032531 A JP 2006032531A
Authority
JP
Japan
Prior art keywords
wiring board
flexible wiring
semiconductor chip
conductor
base substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004207089A
Other languages
Japanese (ja)
Inventor
Keisuke Furuya
圭介 古谷
Katsumi Otani
克実 大谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2004207089A priority Critical patent/JP2006032531A/en
Publication of JP2006032531A publication Critical patent/JP2006032531A/en
Pending legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to assemble a flexible wiring board responding to the demand of high bonding accuracy in COF structure. <P>SOLUTION: The free region 2a of a base substrate 2 without a wiring part 4 is provided in a junction region 12 where a semiconductor chip 5 is joined to a flexible wiring board 1, and a conductor 9 composed of copper foil in a quadrangular shape is provided between inner leads 4a along the longitudinal direction of the inner leads 4a. In bonding, the base substrate 2 is exposed to high temperature so that it may be softened and spread for transformation in order to carry out eutectic fusion of a metal projection 6 and the inner leads 4a by the junction adding temperature and load. As the temperature of the junction descends to the room temperature after processing, the stress of the elasticity directed to a center arises in the free region 2a since the base substrate 2 tries to return to the original shape. Such a nonconformity point as an inner lead displacement, inner lead peeling, or the like in an assembly process is prevented by providing the conductor 9 for this stress so as to strengthen the free region 2a of the base substrate 2 so that high bonding accuracy may be made possible by inhibiting the elasticity generated in the part of this free region 2a. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置の製造工程、特にチップオンフィルムの構造において半導体チップをフレキシブル配線基板上にフリップチップ実装する技術を用いて製造した半導体装置に関するものである。   The present invention relates to a semiconductor device manufactured using a technique for flip-chip mounting a semiconductor chip on a flexible wiring board in a manufacturing process of the semiconductor device, particularly a chip-on-film structure.

従来のこの種のフレキシブルな基材を利用した配線基板のパッケージは、液晶ディスプレイの駆動用ドライバのパッケージとして主に使用されている。ここでフレキシブルな基材を使用したパッケージモジュールの1つとしてチップオンフィルム(以下、COFという)構造がある。液晶ディスプレイ駆動用ドライバの半導体チップの形状は、その特徴として一般に細長いチップ形状をしている。この場合、半導体チップのボンディング時に加えられる熱により、図4(a)に示す接合領域12に高い値の応力が発生することがわかっている。   A conventional wiring board package using such a flexible base material is mainly used as a driver package for a liquid crystal display. Here, as one of package modules using a flexible substrate, there is a chip-on-film (hereinafter referred to as COF) structure. The shape of the semiconductor chip of the driver for driving the liquid crystal display generally has an elongated chip shape as its feature. In this case, it is known that a high value of stress is generated in the bonding region 12 shown in FIG. 4A due to heat applied during bonding of the semiconductor chip.

この応力発生の原因の1つにインナーリードボンド(以下、ILBという)工程により押し付けたフレキシブル配線基板1の基材2が弾性により復元しようとする応力がある。この基材2の復元力が働き、半導体チップ5の金属突起6とインナーリード4aが引き離されてインナーリードずれや、インナーリード剥がれなどの物理的な異常に加え、電気的に開放状態となる不良が発生するという問題を有している。   One of the causes of this stress generation is a stress that the base material 2 of the flexible wiring board 1 pressed by an inner lead bonding (hereinafter referred to as ILB) process tries to recover due to elasticity. The restoring force of the base material 2 works, and the metal protrusion 6 and the inner lead 4a of the semiconductor chip 5 are pulled apart to cause physical abnormalities such as inner lead displacement and inner lead peeling, as well as an electrical open state defect. Have the problem of

そこでボンディング時の熱応力によるフレキシブル配線基板1の伸縮を緩和する技術が提案されている。以下、特許文献1に示されている方法について説明する。図4(b)に示すフレキシブル配線基板1において、半導体チップ5をフリップチップ実装する実装領域に対応した他方の面側に裏面導体8を一体的に、あるいはメッシュ状や格子状のパターンを設ける。裏面導体8はめっき法などにより、基材2に直接形成されるか、または別工程で成膜されたものを貼り付けてもよい。その領域については、できるだけ広い面にわたって設けられることがのぞましく、これにより配線基板の伸縮を防止するものである。
特開2003−324129号公報
Therefore, a technique for alleviating expansion and contraction of the flexible wiring board 1 due to thermal stress during bonding has been proposed. Hereinafter, the method disclosed in Patent Document 1 will be described. In the flexible wiring board 1 shown in FIG. 4B, the back conductor 8 is provided integrally or in a mesh or lattice pattern on the other surface side corresponding to the mounting region where the semiconductor chip 5 is flip-chip mounted. The back conductor 8 may be formed directly on the base material 2 by a plating method or the like, or a film formed in a separate process may be attached. The region is preferably provided over as wide a surface as possible to prevent expansion and contraction of the wiring board.
JP 2003-324129 A

しかしながら、このように製造する半導体装置の従来技術において、裏面に導体を設ける場合に、導体の張り合わせやめっき法による成膜といった工程が増える。さらに、裏面の導体にパターンを施す場合にはパターンの露光やエッチングといった工程も追加されるため、リードタイムとそのコストが膨らんでしまうという課題がある。   However, in the conventional technology of the semiconductor device manufactured in this way, when a conductor is provided on the back surface, processes such as bonding of conductors and film formation by plating are increased. Further, when a pattern is applied to the conductor on the back surface, a process such as pattern exposure or etching is added, which causes a problem that the lead time and its cost increase.

また、液晶ディスプレイ用のCOF構造の半導体装置は図5に示すように液晶パネルへ折り曲げて実装される。そのため、基材2および配線部4に使用する銅箔を薄くすることにより折り曲げ性をより向上させる必要があるが、裏面に導体を広い領域で設けた場合は折り曲げ性が損なわれるために、配線基板そのものの実装性が悪くなる。さらに、裏面の基材に対しては有効な方法であるが、チップ実装面については完全に基材の伸縮を押さえることができないという課題がある。   Further, a semiconductor device having a COF structure for a liquid crystal display is mounted by being bent on a liquid crystal panel as shown in FIG. For this reason, it is necessary to further improve the bendability by thinning the copper foil used for the base material 2 and the wiring portion 4. The mountability of the board itself is deteriorated. Furthermore, although it is an effective method for the substrate on the back surface, there is a problem that the expansion and contraction of the substrate cannot be completely suppressed for the chip mounting surface.

本発明は、前記従来技術の問題を解決することに指向するものであり、液晶ドライバの技術として、今後さらに高精細化を目指して狭ピッチ化とパッド数が増加していくと予想され、高いボンディング精度の要求に応じて、より効果が高く、低コストな配線基板の組み立てを可能とした半導体装置を提供することを目的とする。   The present invention is directed to solving the problems of the prior art, and as a liquid crystal driver technology, it is expected that the pitch will be narrowed and the number of pads will increase in the future for higher definition. An object of the present invention is to provide a semiconductor device capable of assembling a wiring board with higher effect and lower cost in response to a request for bonding accuracy.

前記の目的を達成するために、本発明に係る半導体装置は、バンプを有する半導体チップを基材と配線層から成るフレキシブル配線基板にフリップチップ実装する半導体装置において、フリップチップ実装する半導体チップとフレキシブル配線基板との間で基材表面上に導体を形成したことを特徴とする。   In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device in which a semiconductor chip having bumps is flip-chip mounted on a flexible wiring substrate composed of a base material and a wiring layer. A conductor is formed on the surface of the base material between the wiring board and the wiring board.

また、導体の外形形状が、フリップチップ実装する半導体チップよりも小さく、かつ半導体チップのバンプと接続する配線層のインナーリードの間に形成されて、インナーリードの長手方向に沿った四角形状であることを特徴とする。   Further, the outer shape of the conductor is smaller than the semiconductor chip to be flip-chip mounted, and is formed between the inner leads of the wiring layer connected to the bumps of the semiconductor chip, and has a rectangular shape along the longitudinal direction of the inner leads. It is characterized by that.

前記構成によれば、バンプを有する半導体チップをフリップチップ実装するフレキシブル配線基板上で配線層のない基材の空き領域に半導体チップよりも小さく、かつインナーリード間でその長手方向に沿った四角形状の銅箔による導体を備え、この導体をフリップチップ実装する接合部分と同じ面の近傍に設けてフレキシブル配線基板の基材を固定し、ボンディング時の熱応力によって生じる伸縮を効果的に低減できる。   According to the said structure, it is smaller than a semiconductor chip in the empty area | region of the base material without a wiring layer on the flexible wiring board which carries out the flip-chip mounting of the semiconductor chip which has bump, and the square shape along the longitudinal direction between inner leads A conductor made of copper foil is provided, and the conductor is provided in the vicinity of the same surface as the joint portion to be flip-chip mounted to fix the base material of the flexible wiring board, so that expansion and contraction caused by thermal stress during bonding can be effectively reduced.

本発明によれば、ボンディング時の熱応力を効果的に低減して、インナーリードずれや、インナーリード剥がれを防止し、物理的な異常による不良を発生させない信頼性の高い半導体装置を提供できるという効果を奏する。   According to the present invention, it is possible to provide a highly reliable semiconductor device that effectively reduces thermal stress during bonding, prevents inner lead displacement and inner lead peeling, and does not cause defects due to physical abnormalities. There is an effect.

以下、図面を参照して本発明における実施の形態を詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図1は本発明の実施の形態における半導体チップを実装するフレキシブル配線基板の正面図(a)と、フレキシブル配線基板に半導体チップを実装した半導体装置の断面図(b)を示す図である。ここで、前記従来例を示す図4(a),(b)において説明した構成部材に対応し実質的に同等の機能を有するものには同一の符号を付して示す。   FIG. 1A is a front view of a flexible wiring board on which a semiconductor chip is mounted according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view of a semiconductor device in which the semiconductor chip is mounted on the flexible wiring board. Here, components having substantially the same functions corresponding to the components described in FIGS. 4A and 4B showing the conventional example are denoted by the same reference numerals.

図1(a),(b)に示すように、本発明の実施の形態におけるフレキシブル配線基板1に半導体チップ5が接合される接合領域12において、配線層である配線部4のない基材2の空き領域2aに設けられ、インナーリード4a間において、このインナーリード4aの長手方向に沿った四角形状の銅箔による導体9を設けたものである。   As shown in FIGS. 1A and 1B, the base material 2 without the wiring portion 4 that is a wiring layer in the bonding region 12 where the semiconductor chip 5 is bonded to the flexible wiring substrate 1 in the embodiment of the present invention. A conductor 9 made of a rectangular copper foil along the longitudinal direction of the inner lead 4a is provided between the inner leads 4a.

図2はCOF構造の半導体装置を組み立てる工程の概要を示す図である。図2(a)に示すように、COF構造のフレキシブル配線基板1は、基材2に配線部4が形成され、入出力の外部端子以外の配線部には、配線保護膜3が塗布されている。このフレキシブル配線基板1に、半導体チップ5をフリップチップ実装した半導体装置の製造方法は、平面上に載置された基材2上の配線部4を有する面に、半導体チップ5のバンプである金属突起6を対向させて熱圧着することによって、配線部4から引き出されたインナーリード4aと金属突起6を接続するILB(インナーリードボンド)工程を有している。   FIG. 2 is a diagram showing an outline of a process for assembling a semiconductor device having a COF structure. As shown in FIG. 2A, a flexible wiring board 1 having a COF structure has a wiring portion 4 formed on a base material 2, and a wiring protective film 3 is applied to wiring portions other than input / output external terminals. Yes. In the method of manufacturing a semiconductor device in which the semiconductor chip 5 is flip-chip mounted on the flexible wiring board 1, a metal which is a bump of the semiconductor chip 5 is provided on the surface having the wiring part 4 on the base 2 placed on a plane. There is an ILB (inner lead bonding) process for connecting the inner lead 4a drawn from the wiring portion 4 and the metal protrusion 6 by thermocompression bonding with the protrusion 6 facing each other.

次に、ILB工程について、図2(b)を用いて説明する。図2(b)に示すように、フレキシブル配線基板1には、半導体チップ5の金属突起6の位置に合わせてインナーリード4aが基材2上の配線部4に形成されている。インナーリード4aの表面には錫や金などによってめっきが施されている。半導体チップ5には、金属突起6が半導体チップ5の外周に沿う形か、または半導体チップ5の表面全体に配置されている。半導体チップ5上の金属突起6とフレキシブル配線基板1のインナーリード4aを所定の位置に合わせて熱圧着方式により接合する。   Next, the ILB process will be described with reference to FIG. As shown in FIG. 2B, the flexible wiring substrate 1 has inner leads 4 a formed on the wiring portions 4 on the base material 2 in accordance with the positions of the metal protrusions 6 of the semiconductor chip 5. The surface of the inner lead 4a is plated with tin or gold. On the semiconductor chip 5, a metal protrusion 6 is arranged along the outer periphery of the semiconductor chip 5 or on the entire surface of the semiconductor chip 5. The metal protrusion 6 on the semiconductor chip 5 and the inner lead 4a of the flexible wiring substrate 1 are aligned with a predetermined position and bonded by a thermocompression bonding method.

熱圧着方式とは金属突起6に施されためっき材と配線部4から引き出されたインナーリード4aを共晶融合させるために必要な温度(300℃〜500℃程度)と荷重を加えながら接合する方式である。基材2側から押さえる冶具をステージ10、半導体チップ5側で支える冶具をボンディングツール11などと呼ぶ。   In the thermocompression bonding method, the plating material applied to the metal protrusion 6 and the inner lead 4a drawn out from the wiring portion 4 are joined while applying a temperature (about 300 ° C. to 500 ° C.) and a load necessary for eutectic fusion. It is a method. A jig to be pressed from the substrate 2 side is referred to as a stage 10, and a jig to be supported on the semiconductor chip 5 side is referred to as a bonding tool 11.

ILB工程のボンディング加圧中にはフレキシブル配線基板1を構成する基材2が高温にさらされて軟化し、広がるように変形する。その後、ボンディングが完了して接合部分が室温へと降下するに従い基材2が元の形状に戻ろうとする。その際、基材2と配線部4を構成する銅箔の熱膨張率の違いにより、図3に示す矢印が示す通り基材2のむき出しの空き領域2aの部分が中心に向かって縮もうとする応力7が発生する。その応力7の影響をうけるのが接合領域12(図1(a)参照)のインナーリード4aの長手方向となる空き領域2aの両端部分であり、そこに前述のインナーリードずれや、インナーリード剥がれといった不具合がもっとも顕著に発生することになる。   During bonding pressurization in the ILB process, the base material 2 constituting the flexible wiring board 1 is exposed to a high temperature and softens and deforms so as to spread. Thereafter, as the bonding is completed and the bonded portion is lowered to room temperature, the base material 2 tries to return to the original shape. At that time, due to the difference in coefficient of thermal expansion between the copper foil constituting the base material 2 and the wiring part 4, the portion of the exposed empty area 2a of the base material 2 tends to shrink toward the center as indicated by the arrow shown in FIG. Stress 7 is generated. The stress 7 is affected by both end portions of the vacant region 2a in the longitudinal direction of the inner lead 4a of the joining region 12 (see FIG. 1A), and the inner lead displacement and inner lead peeling described above are present there. Such a problem occurs most remarkably.

そこで、本実施の形態における図1(a),(b)に示すような導体9を設けることにより、フレキシブル配線基板1の製造工程である露光やエッチングといった工程が1回で済み、低コストでリードタイムにも影響がなく、さらに配線部4側の面に導体9を設けることで折り曲げ性の損失についてもまったく損なうことがない。そして、基材2の空き領域2aの部分に生じる伸縮を防止するという課題に対して、半導体チップ5の接合面と同じ面であること、さらに接合部分にもっとも近い位置で導体9によって、基材2の空き領域2aを固めていることの2点の効果により高精度のボンディングを行うことが可能となる。   Therefore, by providing the conductor 9 as shown in FIGS. 1A and 1B in the present embodiment, the steps such as exposure and etching, which are the manufacturing steps of the flexible wiring board 1, are completed once, and the cost is low. The lead time is not affected, and the conductor 9 is provided on the surface on the wiring portion 4 side, so that there is no loss in bending loss. And with respect to the subject of preventing the expansion-contraction which arises in the part of the empty area | region 2a of the base material 2, it is the same surface as the joining surface of the semiconductor chip 5, and also the base material by the conductor 9 in the position nearest to the joining portion. High-precision bonding can be performed by the two effects of solidifying the two empty areas 2a.

本発明に係る半導体装置は、ボンディング時の熱応力を効果的に低減して、インナーリードずれや、インナーリード剥がれを防止して、物理的な異常による不良を防ぐことができ、半導体装置の製造工程、特に半導体チップをフレキシブル配線基板にフリップチップ実装して半導体装置製造に用いる技術に有用である。   The semiconductor device according to the present invention can effectively reduce thermal stress during bonding, prevent inner lead displacement and inner lead peeling, and prevent defects due to physical abnormalities. This method is useful for processes, particularly for techniques used for manufacturing semiconductor devices by flip-chip mounting a semiconductor chip on a flexible wiring board.

(a)は本発明の実施の形態におけるフレキシブル配線基板の正面図、(b)はフレキシブル配線基板に半導体チップを実装した断面図(A) is the front view of the flexible wiring board in embodiment of this invention, (b) is sectional drawing which mounted the semiconductor chip in the flexible wiring board COF構造の半導体装置を組み立てる工程の概要を示す図The figure which shows the outline | summary of the process of assembling the semiconductor device of a COF structure. フレキシブル配線基板の空き領域部分に生じる応力を説明する図The figure explaining the stress which arises in the empty area part of a flexible wiring board (a)は従来のフレキシブル配線基板の正面図、(b)はフレキシブル配線基板に半導体チップを実装した断面図(A) is the front view of the conventional flexible wiring board, (b) is sectional drawing which mounted the semiconductor chip on the flexible wiring board. 液晶パネルに折り曲げて実装されるフレキシブル配線基板を示す図The figure which shows the flexible wiring board which is bent and mounted on the liquid crystal panel

符号の説明Explanation of symbols

1 フレキシブル配線基板
2 基材
2a 空き領域
3 配線保護膜
4 配線部
4a インナーリード
5 半導体チップ
6 金属突起
7 応力
8 裏面導体
9 導体
10 ステージ
11 ボンディングツール
12 接合領域
DESCRIPTION OF SYMBOLS 1 Flexible wiring board 2 Base material 2a Empty area 3 Wiring protective film 4 Wiring part 4a Inner lead 5 Semiconductor chip 6 Metal protrusion 7 Stress 8 Back surface conductor 9 Conductor 10 Stage 11 Bonding tool 12 Bonding area

Claims (2)

バンプを有する半導体チップを基材と配線層から成るフレキシブル配線基板にフリップチップ実装する半導体装置において、
フリップチップ実装する前記半導体チップと前記フレキシブル配線基板との間で前記基材表面上に導体を形成したことを特徴とする半導体装置。
In a semiconductor device in which a semiconductor chip having bumps is flip-chip mounted on a flexible wiring board composed of a base material and a wiring layer,
A semiconductor device, wherein a conductor is formed on a surface of the base material between the semiconductor chip to be flip-chip mounted and the flexible wiring board.
前記導体の外形形状が、フリップチップ実装する半導体チップよりも小さく、かつ前記半導体チップのバンプと接続する配線層のインナーリードの間に形成されて、前記インナーリードの長手方向に沿った四角形状であることを特徴とする請求項1記載の半導体装置。   The outer shape of the conductor is smaller than the semiconductor chip to be flip-chip mounted, and is formed between the inner leads of the wiring layer connected to the bumps of the semiconductor chip, and has a rectangular shape along the longitudinal direction of the inner leads. The semiconductor device according to claim 1, wherein:
JP2004207089A 2004-07-14 2004-07-14 Semiconductor device Pending JP2006032531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004207089A JP2006032531A (en) 2004-07-14 2004-07-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004207089A JP2006032531A (en) 2004-07-14 2004-07-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2006032531A true JP2006032531A (en) 2006-02-02

Family

ID=35898537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004207089A Pending JP2006032531A (en) 2004-07-14 2004-07-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2006032531A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107277405A (en) * 2017-07-17 2017-10-20 环球智达科技(北京)有限公司 Apparatus and method for assembling liquid crystal TV set display screen
WO2019085016A1 (en) * 2017-10-31 2019-05-09 武汉华星光电技术有限公司 Narrow-frame display panel and manufacturing method therefor, and display apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107277405A (en) * 2017-07-17 2017-10-20 环球智达科技(北京)有限公司 Apparatus and method for assembling liquid crystal TV set display screen
WO2019085016A1 (en) * 2017-10-31 2019-05-09 武汉华星光电技术有限公司 Narrow-frame display panel and manufacturing method therefor, and display apparatus

Similar Documents

Publication Publication Date Title
US8123965B2 (en) Interconnect structure with stress buffering ability and the manufacturing method thereof
JP4686248B2 (en) Optical semiconductor device and optical semiconductor device manufacturing method
JP6043049B2 (en) Semiconductor device mounting structure and semiconductor device mounting method
JP2010506399A (en) Electronic devices and lead frames
JP2005252227A (en) Film substrate, and the manufacturing method and image display substrate
JP2006228932A (en) Semiconductor package
JP2006210566A (en) Semiconductor device
JP2006032531A (en) Semiconductor device
US20180233459A1 (en) Module, module manufacturing method, and package
JP4430062B2 (en) IC chip mounting package manufacturing method
US10211118B2 (en) Semiconductor module
KR102039791B1 (en) Mounting method of semiconductor chip and semiconductor chip package
JP2003133519A (en) Laminated semiconductor device, manufacturing method therefor, and mother board and manufacturing method therefor
JP2006013553A (en) Semiconductor ic device
JP4128722B2 (en) Circuit board and electronic equipment
JP7459610B2 (en) electronic equipment
JP2005109377A (en) Semiconductor device and manufacturing method therefor
JP2006229030A (en) Lead frame and semiconductor device using same
JP4260766B2 (en) Semiconductor device
JP2011108892A (en) Package structure
JP4175339B2 (en) Manufacturing method of semiconductor device
JPH10303251A (en) Semiconductor device
JP2005340678A (en) Semiconductor device
JP2005191335A (en) Film substrate, semiconductor device, and manufacturing method therefor
JP2002334946A (en) Semiconductor package and semiconductor device