JP2006032472A - Solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup device where linearity of signal output can be secured even if a generated amount of photogenerated charges is small and occurrence of fixed pattern noise can be suppressed by deforming a shape of a carrier pocket. <P>SOLUTION: The solid-state image pickup device includes a photoelectric conversion element generating the photogenerated charge corresponding to incident light and a modulation transistor which is arranged in a region adjacent to the photoelectric conversion element and generates a signal corresponding to the amount of the photogenerated charges. The modulation transistor includes an annular gate 4, a source region 5 formed inside the annular gate, a drain region formed outside the annular gate, the carrier pocket 7 formed below the circular gate positioned between the source region and the photoelectric conversion element, holds the photogenerated charges from the photoelectric conversion element and changes a threshold of the modulation transistor and a control pocket 9 arranged below the annular gate where the carrier pocket is not formed through a potential barrier with the carrier pocket. Thus, occurrence of fixed pattern noise can be prevented. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device having high image quality characteristics and low power consumption characteristics.

  As a solid-state imaging device mounted on a cellular phone or the like, there are a CCD (charge coupled device) type image sensor and a CMOS type image sensor. A CCD type image sensor has excellent image quality, and a CMOS type image sensor has low power consumption and low process cost. In recent years, a MOS type solid-state imaging device of a threshold voltage modulation method that has both high image quality and low power consumption has been proposed. A threshold voltage modulation type MOS solid-state imaging device is disclosed in, for example, Patent Document 1.

  The image sensor obtains an image output by arranging sensor cells in a matrix and repeating three states of initialization, accumulation, and readout. In the image sensor disclosed in Patent Document 1, each unit pixel includes a light receiving diode for performing accumulation and a transistor for performing readout.

  In the image sensor of Patent Document 1, a light-receiving diode and an optical signal detection MOS transistor are adjacently arranged for each unit pixel on a substrate. The gate electrode of this transistor is formed in a ring shape, and a source region is formed in the central opening of the gate electrode. A drain region is formed around the gate electrode.

  Charges (photogenerated charges) generated by light incident from the opening region of the light receiving diode are transferred to a P-type well region below the gate electrode and accumulated in a carrier pocket formed in this portion. The threshold voltage of the transistor changes due to the photogenerated charges accumulated in the carrier pocket. Thereby, a signal (pixel signal) corresponding to the incident light can be extracted from the source region of the transistor.

  In the device disclosed in Patent Document 1, the outputs of the unit pixels arranged in the same column are extracted through a common source line. By controlling the voltage applied to the gate of the transistor for each line, selective reading from the unit pixels of a predetermined line among the unit pixels connected to the common source line is enabled. That is, a relatively high gate voltage is applied to the transistor of the unit pixel (selected pixel) that performs reading, and a relatively low gate voltage is applied to the transistor of the unit pixel (non-selected pixel) that does not perform other reading. The output of the transistor to which the high gate voltage is applied is higher than the output of the transistor to which the low gate voltage is applied, and the output of the selected pixel can be obtained from the source line.

Patent Document 2 and the like disclose a technique for forming a modulation transistor in a rod shape. However, when a rod-type modulation transistor is configured, it is necessary to provide isolation by a diffusion layer or isolation region by LOCOS. For this reason, a complicated structure such as a two-layered gate electrode is required, and the drive sequence is complicated.
JP 2002-57315 A Japanese Patent Laid-Open No. 10-65138

  By the way, the carrier pocket is formed at a relatively high concentration, and when the hole potential is used as a reference, the potential becomes a sufficiently low value at the time of initialization. As a result, photogenerated charges generated in the light receiving diode are accumulated in the carrier pocket. However, the potential of the carrier pocket is affected by peripheral potentials such as the drain and the gate. If the carrier pocket concentration is constant, the potential based on holes decreases in proportion to the distance from the periphery.

  By the way, in the apparatus of Patent Document 1, the carrier pocket is formed in a square shape in plan view. Therefore, the width of the carrier pocket is different between the corner and the side of the carrier pocket, and the potential is partially lowered in the corner of the carrier pocket as compared with other portions. In consideration of the mask shape in the diffusion process, it is difficult to form the carrier pocket in a complete circular shape, and a part having a low potential is necessarily generated in the carrier pocket. In addition, due to the non-uniformity of the carrier pocket concentration, there may be a portion having a lower potential than other portions in the carrier pocket.

  The carrier pocket has a higher potential due to the accumulation of photogenerated charges, thereby changing the surface channel potential to facilitate channel current flow. However, when the amount of photogenerated charges generated is relatively small, for example, in the case of low illuminance, the photogenerated charges are likely to be accumulated only in the portion where the potential of the carrier pocket is low.

  That is, at low illuminance, photogenerated charges are accumulated only in a part of the carrier pocket and threshold modulation is performed. However, in most areas of the carrier pocket, photogenerated charge is not accumulated and threshold modulation is performed. I will not.

  For this reason, when the amount of photogenerated charges is relatively small, the signal output rises slowly and the linearity is poor. When such a pixel is arranged one-dimensionally or two-dimensionally to form a screen, for example, at low illuminance, there is a problem that output tends to vary from pixel to pixel, and fixed pattern noise appears. It was.

  The present invention has been made in view of such problems, and by deforming the shape of the carrier pocket, it is possible to ensure linearity of signal output even when the amount of photogenerated charges is small, and fixed pattern noise. An object of the present invention is to provide a solid-state imaging device capable of suppressing the occurrence of the above.

A solid-state imaging device according to the present invention includes:
A photoelectric conversion element that generates a photo-generated charge according to incident light;
A modulation transistor disposed in a region adjacent to the photoelectric conversion element, the modulation transistor generating a signal according to a charge amount of the photogenerated charge;
In a solid-state imaging device including:
The modulation transistor is:
An annular gate,
A source region formed inside the annular gate;
A drain region formed outside the annular gate;
A carrier pocket formed below the annular gate located between the source region and the photoelectric conversion element, and holds a photo-generated charge from the photoelectric conversion element and changes a threshold value of the modulation transistor The carrier pocket;
A control pocket disposed below the annular gate where the carrier pocket is not formed via a potential barrier with the carrier pocket;
including.

  According to the embodiment of the present invention, the photoelectric conversion element generates photogenerated charges corresponding to the incident light. A modulation transistor is disposed adjacent to the photoelectric conversion element, and a source region is formed in a central opening of an annular gate constituting the modulation transistor. A carrier pocket is formed between the source region and the photoelectric conversion element. Photogenerated charges from the photoelectric conversion element are held in the carrier pocket. Thus, the threshold value of the modulation transistor changes, and an output corresponding to the amount of incident light is obtained from the modulation transistor. In addition, a control pocket is disposed around the source region where no carrier pocket is formed via a potential barrier between the source region and the source pocket. The control pocket raises the threshold and suppresses surface channel parasitic currents on the control pocket. This ensures output linearity.

  The carrier pocket is formed to have a linear shape between the source region and the photoelectric conversion element.

  According to the embodiment of the present invention, the carrier pocket has a linear shape, and a uniform current flows through the surface channel on the carrier pocket in any part. Thereby, output linearity is obtained.

  The annular gate has a side facing the photoelectric conversion element in a plan view, and the carrier pocket has a linear shape along the side facing the photoelectric conversion element of the annular gate.

  According to the embodiment of the present invention, since the carrier pocket has a linear shape along the side facing the photoelectric conversion element of the annular gate, the pocket length of the carrier pocket is above the carrier pocket. The potential in the carrier pocket is uniform throughout the entire surface channel width direction. Therefore, even when the amount of photogenerated charges is small, a channel current flows uniformly over the entire surface channel on the carrier pocket. This ensures output linearity.

  The control pocket is set to the same concentration as the carrier pocket.

  According to the embodiment of the present invention, since the concentration of the control pocket is sufficiently high, the parasitic current flowing in the surface channel on the control pocket can be suppressed.

  The control pocket is set at a higher concentration than the carrier pocket.

  According to the embodiment of the present invention, since the concentration of the control pocket is higher than the concentration of the carrier pocket, the parasitic current flowing in the surface channel on the control pocket can be further suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view showing a planar shape of one sensor cell of the solid-state imaging device according to the first embodiment of the present invention, and FIG. 2 is an explanatory diagram showing an example in which the planar shape of the modulation transistor is an octagon. FIG. 3 is an explanatory diagram showing a basic structure for avoiding fixed pattern noise.

  First, the structure of the modulation transistor for avoiding fixed pattern noise will be described with reference to FIG. The solid-state imaging device according to the present embodiment has a sensor cell array in which sensor cells that are unit pixels are arranged in a matrix. Each sensor cell collects and accumulates photogenerated charges generated according to incident light, and outputs a pixel signal at a level based on the accumulated photogenerated charges. An image signal of one screen can be obtained by arranging the sensor cells in a matrix.

  FIG. 3 shows the structure of the sensor cells 31 and 41 that can avoid fixed pattern noise. 3A shows an example in which the modulation transistor has a quadrangular shape, and FIG. 3B shows an example in which the modulation transistor has an octagonal shape. Note that the sensor cells 31 and 41 in FIGS. 3A and 3B only differ in whether the planar shape of the modulation transistor is an octagonal shape that is a quadrangular shape.

  The sensor cells 31 and 41 shown in FIG. 3 are formed on a semiconductor substrate by a semiconductor process. In the sensor cells 31 and 41, photodiodes that generate photogenerated charges in response to incident light are formed in the photodiode formation regions 32 and 42, respectively. In addition, the sensor cells 31 and 41 are provided with modulation transistor formation regions (modulation transistor formation regions) for outputting pixel signals corresponding to photogenerated charges, adjacent to the photodiode formation regions 32 and 42.

  In the photodiode formation regions 32 and 42, photogenerated charges corresponding to incident light are generated. Adjacent to the photodiode formation regions 32 and 42, annular ring gates 34 and 44 constituting modulation transistors are formed. The planar shape of the ring gate 34 is a tetragon, and the planar shape of the ring gate 44 is an octagon. The ring gates 34 and 44 are open at the center, and source regions 35 and 45 are provided in the opening portions, respectively. The source regions 35 and 45 are connected to source lines (data lines) (not shown) via contact portions 36 and 46, respectively.

  A region outside the photodiode formation region 32 and the ring gate 34 of the modulation transistor is a drain region 33, and the drain region 33 is connected to a drain wiring (not shown) via a contact portion 38. A region outside the photodiode forming region 42 and the modulation transistor ring gate 44 is a drain region 43, and the drain region 43 is connected to a drain wiring (not shown) through a contact portion 48. On the substrate surface, drain regions 33 and 43 are also formed on the photodiode formation regions 32 and 42, respectively.

  In the example of FIG. 3A, a carrier pocket 37 in which photogenerated charges are accumulated is formed below the ring gate 34 (inside the substrate). The carrier pocket 37 is configured in a straight line shape having a predetermined width in plan view along one side of the source region 35 facing the photodiode forming region 32. Since the carrier pocket 37 does not have a bent shape, the distance in the formation direction of the surface channel from the drain region 33 to the source region 35 (hereinafter referred to as pocket length) is formed at an equal distance in any part. Is done.

  Therefore, the potential of the carrier pocket 37 is substantially uniform in any part in the direction perpendicular to the surface channel formation direction (direction perpendicular to the pocket length direction). As a result, when the solid-state imaging device is configured using the sensor cell 31 of FIG. 3A, an output corresponding to the amount of light can be generated even at low illuminance, and output from low illuminance to high illuminance. Linearity can be obtained.

  In the example of FIG. 3B, a carrier pocket 47 for storing photogenerated charges is formed below the ring gate 44 (inside the substrate). The carrier pocket 47 is also configured in a straight line shape having a predetermined width in plan view along one side of the source region 45 facing the photodiode formation region 42. Since the carrier pocket 47 does not have a bent shape, the pocket length is formed at an equal distance in any part.

  Accordingly, the potential of the carrier pocket 47 is substantially uniform in any part in the direction perpendicular to the pocket length direction. As a result, when the solid-state imaging device is configured using the sensor cell 41 of FIG. 3B, an output corresponding to the amount of light can be generated even at low illuminance, and output from low illuminance to high illuminance. Linearity can be obtained.

  However, in the example of FIGS. 3A and 3B, the parasitic currents from the drain regions 33 and 43 are channeled in the source regions 35 and 45 in the portions other than the formation regions of the carrier pockets 37 and 47, respectively. It flows as current. This parasitic current actually deteriorates the output linearity.

  Therefore, in the present embodiment, a high-concentration control pocket for suppressing the parasitic current is formed in the substrate below the path of the parasitic current.

  In FIG. 1, the sensor cell 1 has a quadrangular modulation transistor TM, similar to the sensor cell 31 of FIG. Further, the sensor cell 11 of FIG. 2 has an octagonal modulation transistor TM ′, like the sensor cell 41 of FIG. These sensor cells 1 and 11 differ only in the planar shape of the modulation transistor. That is, the photodiode formation region 12, the drain region 13, the ring gate 14, the source region 15, the contact portions 16 and 18, the carrier pocket 17, the control pocket 19 and the potential barrier 20 in FIG. The formation region 2, the drain region 3, the ring gate 4, the source region 5, the contact portions 6 and 8, the carrier pocket 7, the control pocket 9 and the potential barrier 10 have the same functions. Hereinafter, for simplification of description, the sensor cell 1 of FIG. 1 will be mainly described, and only the differences will be described for the sensor cell 11 of FIG. The sensor cell 1 or sensor cell 11 is arranged in a matrix to form a sensor cell array.

<Cross-sectional structure of each sensor cell>
First, the sectional structure of the sensor cells 1 and 11 will be described with reference to FIG. FIG. 4 is a schematic cross-sectional view showing a cross-sectional structure of the sensor cell 1. FIG. 4 shows a cross-sectional structure taken along line AA ′ of FIG. Note that the cross-sectional shape of the sensor cell 11 of FIG. 2 cut along the line AA ′ of FIG. 2 is the same as that of FIG. This embodiment shows an example in which holes are used as photogenerated charges. Even in the case where electrons are used as the photo-generated charges, the same configuration is possible.

  Each cell has a photodiode formation region and a modulation transistor formation region. N-type wells 51 and 52 are formed over the entire area of the P-type substrate 50. A P-type collection well 53 is formed on the N-type well 51 in the photodiode formation region. On the substrate surface side above the collection well 53, an N-type diffusion layer 55, which is a pinning layer, is formed. The N-type well 51 is formed up to a relatively deep position on the substrate.

On the other hand, in the modulation transistor TM formation region, the N-type well 52 is limited to a relatively shallow position of the substrate 50. A P-type modulation well 54 is formed on the N-type well 52. A carrier pocket 7 is formed in the modulation well 54. The carrier pocket 7 is a diffusion layer having a relatively high concentration by P ⁺ diffusion. An annular ring gate 4 is formed in the modulation transistor formation region on the substrate surface. In the example of FIG. 1, the ring gate 4 is formed in a quadrangular shape in plan view. In the example of FIG. 2, the ring gate 14 is formed in an octagonal shape in plan view.

An N ⁺ diffusion layer is formed on the surface of the substrate at the central opening of the ring gate 4 to form the source region 5. Further, an N-type diffusion layer is formed on the substrate surface around the ring gate 4 to constitute the drain region 3. Similarly, the substrate surface of the central opening of the ring gate 14 constituting the source region 15 is formed N ⁺ diffusion layer. Further, an N-type diffusion layer is formed on the substrate surface around the ring gate 14 to form the drain region 13.

  An N type diffusion layer 56 constituting a channel is formed on the surface of the substrate under the ring gate 4, and the N type diffusion layer 56 is electrically connected to the source region 5 and the drain region 3. Similarly, an N type diffusion layer 56 constituting a channel is formed on the substrate surface under the ring gate 14, and the N type diffusion layer 56 is electrically connected to the source region 15 and the drain region 13. Thus, for example, an N-channel depletion MOS transistor is used as the modulation transistor TM.

  The drain region 3, the well 51, the well 52, and the diffusion layer 55 are biased to a positive potential by applying a drain voltage, so that the boundary surface between the diffusion layer 55 and the collection well 53 is formed below the opening region of the photodiode. A depletion layer extends from the interface between the well 51 and the collection well 53 to the entire collection well 53 and its periphery. In the depletion region, photogenerated charges due to light incident through the opening region are generated. As described above, the generated photo-generated charges are collected in the collection well 53, further transferred to the modulation well 54, and held in the carrier pocket 7. As a result, the source potential of the modulation transistor TM becomes in accordance with the amount of charge transferred to the modulation well 54, that is, the incident light to the photodiode PD.

  The other configuration of the sensor cell 11 in FIG. 2 in which the ring gate 14 in the modulation transistor formation region is formed in an octagonal shape has the cross-sectional structure shown in FIG. 4 as in the sensor cell 1 in FIG.

<Circuit configuration of the entire device>
FIG. 5 is a circuit block diagram showing an entire circuit configuration of the solid-state imaging device using the sensor cell array configured by arranging the sensor cells 1 in a matrix by an equivalent circuit.

  As shown in FIG. 5, the sensor cell array 62 is configured by arranging the sensor cells 1 of FIG. 1 in a matrix. The solid-state imaging device 61 in the present embodiment includes a sensor cell array 62 and circuits 63 to 65 that drive each sensor cell 1 in the sensor cell array 62. The sensor cell array 62 includes, for example, a 640 × 480 cell 1 and an optical black (OB) region (OB region). When the OB region is included, the sensor cell array 62 is composed of, for example, 712 × 500 cells 1. Note that the solid-state imaging device 61 of the present embodiment can be similarly configured by using the sensor cell 11 of FIG. 2 instead of the sensor cell 1.

  The photodiode configured in the photodiode formation region 2 in FIG. 1 or the photodiode formation region 12 in FIG. 2 corresponds to the photodiode PD in FIG. The modulation transistor configured in the modulation transistor formation region (see FIG. 4) of the sensor cells 1 and 11 is indicated by the modulation transistor TM in FIG.

  As described above, each sensor cell 1 includes the photodiode PD that performs photoelectric conversion and the modulation transistor TM for detecting and reading out an optical signal. The photodiode PD generates a charge (photogenerated charge) corresponding to the incident light, and the generated charge passes through the collection well 53 (corresponding to the connection point PDW in FIG. 5), and a modulation well for threshold modulation of the modulation transistor TM. It is transferred to and held in the carrier pocket 7 in 54 (corresponding to the connection point TMW in FIG. 5).

  The modulation transistor TM is equivalent to a change in the back gate bias due to the photogenerated charge held in the carrier pocket 7, and the channel threshold voltage changes according to the amount of charge in the carrier pocket 7. As a result, the source voltage of the modulation transistor TM corresponds to the charge in the carrier pocket 7, that is, corresponds to the brightness of the incident light of the photodiode PD.

  In this manner, each cell 1 exhibits operations such as accumulation, transfer, reading, and clearing by applying drive signals to the ring gate 4, the source region 5, and the drain region 3 of the modulation transistor TM. Signals are supplied to each part of the cell 1 from a vertical drive scanning circuit 63, a drain drive circuit 64, and a horizontal drive scanning circuit 65, as shown in FIG. The vertical drive scanning circuit 63 supplies a scanning signal to the gate line 67 of each row, and the drain drive circuit 64 applies a drain voltage to the drain region 3 of each column. The horizontal drive scanning circuit 65 supplies a drive signal to the switch 68 connected to each source line 66.

  Each cell 1 is provided corresponding to an intersection of a plurality of source lines 66 arranged in the horizontal direction and a plurality of gate lines 67 arranged in the vertical direction in the sensor cell array 62. In each cell 1 of each line arranged in the horizontal direction, the ring gate 4 of the modulation transistor TM is connected to a common gate line 67, and each cell 1 in each column arranged in the vertical direction is the source of the modulation transistor TM. Region 5 is connected to a common source line 66.

  By supplying an ON signal (selection gate voltage) to one of the plurality of gate lines 67, the cells commonly connected to the gate line 67 to which the ON signal is supplied are simultaneously selected, and these selected cells are selected. A pixel signal is output from each source region 5 through each source line 66. The vertical drive scanning circuit 63 supplies an ON signal to the gate line 67 while sequentially shifting it in one frame period. Pixel signals from each cell of the line to which the ON signal is supplied are simultaneously read from each source line 66 for one line and supplied to each switch 68. The pixel signals for one line are sequentially output (line output) for each pixel from the switch 68 by the horizontal drive scanning circuit 65.

  The switch 68 connected to each source line 66 is connected to the video signal output terminal 70 via a common constant current source (load circuit) 69. The source region 5 of the modulation transistor TM of each sensor cell 1 is connected to the constant current source 69, and the source follower circuit of the sensor cell 1 is configured.

<Planar shape of sensor cell>
FIG. 1 shows an example in which the ring gate 4 of the modulation transistor has a quadrangular shape, and FIG. 2 shows an example in which the ring gate 14 of the modulation transistor has an octagonal shape.

  As shown in the plan view of FIG. 1, a photodiode formation region 2 and a modulation transistor TM formation region are provided adjacent to each other in a sensor cell 1 which is a unit pixel. As described above, for example, an N-channel depletion MOS transistor is used as the modulation transistor TM.

  In the photodiode PD formation region, an opening region that transmits light is formed in the step of forming a wiring layer on the surface of the substrate 50. At a relatively shallow position on the surface of the substrate 50, a P-type well is formed in a region wider than the opening region, and a collection well 53 for collecting photogenerated charges generated by the photoelectric conversion element is formed. The photodiode formation region 2 is configured by the N-type well 51 and the collection well 53 below the opening region.

  A quadrangular ring gate 4 is disposed adjacent to the photodiode formation region 2. A modulation well 54 is formed at a relatively shallow position of the substrate below the ring gate 4. The modulation well 54 is formed substantially continuously with the collection well 53, and the photogenerated charges collected in the collection well 53 are transferred to the modulation well 54. In the example of FIG. 4, the collection well 53 and the modulation well 54 are integrally formed, but may be formed separately.

A source region 5, which is a high-concentration N-type region, is formed in a region near the surface of the substrate 50 in the central opening of the ring gate 4. An N-type drain region 3 is formed around the ring gate 4. An N ⁺ layer contact portion 8 is formed in the vicinity of the surface of the substrate 50 at a predetermined position of the drain region 3.

  The modulation well 54 controls the threshold voltage of the channel of the modulation transistor. In the modulation well 54, a carrier pocket 7, which is a P-type high concentration region, is formed below the ring gate 4. The carrier pocket 7 is formed linearly along the side of the ring gate 4 facing the photodiode formation region 2. The pocket length of the carrier pocket 7 is equidistant at any position.

  The modulation transistor TM is constituted by the modulation well 54, the ring gate 4, the source region 5 and the drain region 3, and the threshold voltage of the channel changes according to the electric charge accumulated in the carrier pocket 7.

  In the present embodiment, in the region where the carrier pocket 7 below the ring gate 4 is not formed, at each side of the ring gate 4 (three sides of the source region 5) at the same substrate depth as the carrier pocket 7. A U-shaped control pocket 9 is formed. That is, in plan view, the control pocket 9 is formed so as to substantially surround the source region 5 in a portion excluding the carrier pocket 7 formation region. Further, in the vicinity of the two corners of the source region 5 between the carrier pocket 7 and the control pocket 9, a high concentration diffusion layer is not formed, and this portion has a relatively low concentration potential barrier region 10. Configure.

  The control pocket 9 is set to a sufficiently high concentration, and the potential based on the hole is sufficiently low at the time of clearing. Therefore, the threshold value in the formation region of the control pocket 9 is sufficiently high, and the surface channel current (parasitic current) in this region is sufficiently suppressed.

  The sensor cell 11 of FIG. 2 has the same configuration as that of the sensor cell 1 of FIG. 1 except that the ring gate 14 is octagonal and that each part has a shape that follows the shape of the ring gate 14. .

<Operation>
Next, the operation of the embodiment configured as described above will be described with reference to FIGS. FIG. 6 is an explanatory diagram showing the potential based on the hole at the position of the line BB ′ in FIG. 4. FIG. 7 shows the incident light with the horizontal axis indicating the light intensity and the vertical axis indicating the pixel signal level. It is a graph which shows the relationship between the light intensity of this, and an output.

  A low gate voltage is applied to the ring gate 4 of the modulation transistor TM, and a voltage (VDD) of about 0 to 2 V, for example, necessary for the operation of the transistor is applied to the drain region 3. As a result, the collection well 53 and its surroundings are depleted. An electric field is generated between the drain region 3 and the source region 5.

  The light incident on the photodiode formation region 2 is incident on the depleted N-type well 51 to generate electron-hole pairs (photogenerated charges). The P-type collection well 53 has a low potential due to the introduction of high-concentration P-type impurities, and the photogenerated charges generated in the depletion layer formed by the collection well 53 and the N-type well 51 enter the collection well 53. Collected. Further, the photo-generated charges are transferred from the collection well 53 to the modulation well 54 in the modulation transistor formation region and accumulated in the carrier pocket 7.

  In the transistor formation region, a carrier pocket 7 and a control pocket 9 which are high concentration diffusion layers are formed. However, the carrier pocket 7 is formed in a portion facing the photodiode formation region, and the photo-generated charges transferred from the collection well 53 to the modulation well 54 are first accumulated in the carrier pocket 7.

  As shown in FIG. 6, the carrier pocket 7 has a sufficiently low potential in the substrate depth direction compared to the high potential of the N-type well 52, and the holes transferred from the collection well 53 (the black circles in FIG. 6). ). Further, a sufficiently high potential barrier 10 is provided between the control pocket 9 and the carrier pocket 7 having a sufficiently low potential, and the photogenerated charges transferred to the carrier pocket 7 also in the horizontal direction of the substrate. However, it does not flow out to the control pocket 9 side.

  Accordingly, no photogenerated charge is accumulated in the control pocket 9 other than the overflowed photogenerated charge from the carrier pocket 7. That is, the potential of the control pocket 9 remains low at a normal incident light amount.

  Thereby, the threshold value based on the potential of the control pocket 9 is sufficiently high, and it is reliably prevented that a parasitic current flows in the surface channel on the control pocket 9.

  On the other hand, the carrier pocket 7 is formed in a linear shape, and the pocket length is uniform. That is, photogenerated charges are uniformly accumulated throughout the carrier pocket 7. The threshold voltage of the modulation transistor TM changes due to the photogenerated charges accumulated in the carrier pocket 7. In this state, a gate voltage (selection gate voltage) of about 2 to 4 V, for example, is applied to the ring gate 4 of the selected pixel, and a voltage VDD of about 2 to 4 V, for example, is applied to the drain region 3. Further, a constant current is passed through the source region 5 of the modulation transistor TM by the constant current source 69. As a result, the modulation transistor TM forms a source follower circuit, and the source potential changes following the change in the threshold voltage of the modulation transistor TM due to the photo-generated charges, so that the output voltage changes. That is, an output corresponding to the incident light can be obtained.

  In this case, since the photo-generated charges are uniformly accumulated in the entire area of the carrier pocket 7, the current easily flows through the surface channel at any position, and the channel current flows uniformly. Therefore, as shown in FIG. 7, an output (source potential) excellent in linearity according to the amount of incident light can be obtained even at low illuminance. Thereby, even when the amount of photogenerated charges is small as in low illuminance, the generation of fixed pattern noise can be prevented.

  In addition, the three sides of the source region 5 other than the side facing the carrier pocket 7 are surrounded by a control pocket 9 formed in a U-shape, so that a parasitic current can be prevented from flowing into the source region 5. . Therefore, the linearity of the output of each sensor cell 1 can be obtained according to the amount of incident light.

  When the photogenerated charge accumulated in the carrier pocket 7 overflows and flows into the control pocket 9, a modulated output based on the photogenerated charge accumulated in the control pocket 9 is obtained. That is, when strong incident light that overflows the photogenerated charge is generated from the carrier pocket 7, the source potential is changed based on the substrate modulation of the control pocket 9, as shown in the characteristic change of FIG. Linearity is lost. Therefore, it is necessary to set the light intensity range in which the linearity of FIG.

  At the time of initialization, charges remaining in the carrier pocket 7, the control pocket 9, the collection well 53, and the modulation well 54 are discharged. For example, a positive voltage of 5 V or more is applied to the drain region 3 and the ring gate 4 of the modulation transistor TM. The N-type well 52 below the modulation well 54 is thin, and the voltage applied to the ring gate 4 acts only on the modulation well 54 and its adjacent region. That is, a sudden potential change occurs in the modulation well 54, and a strong electric field that sweeps the photogenerated charge toward the substrate 50 is mainly applied to the modulation well 54, and the remaining photogenerated charge has a relatively low reset voltage. Thus, the substrate 50 is more reliably discharged.

  After initialization, a non-selection gate voltage having a relatively low voltage value is applied to the ring gate 4 of the non-selection pixel, and a selection gate voltage having a relatively high voltage value is applied to the ring gate 4 of the selection pixel. . Then, a signal output after initialization of the selected pixel is obtained from the commonly connected source line 66.

  Thus, in the present embodiment, a linear carrier pocket is formed facing the photodiode formation region, and a high-concentration control pocket is formed along the three sides of the source region where the carrier pocket is not formed. Forming and dividing both in terms of potential. In this way, an output with excellent linearity is obtained by accumulating photogenerated charges in a carrier pocket having a uniform potential and modulating the substrate. In addition, no photo-generated charge flows into the control pocket, and the high-concentration control pocket maintains a low potential and obtains a sufficiently high threshold. This prevents the channel current from flowing in the surface channel on the control pocket and suppresses the parasitic current. Thereby, the linearity of the output can be ensured. Therefore, by adopting this embodiment, it is possible to obtain a high-quality image that does not cause fixed pattern noise.

  In addition, although the example which uses the quadrangular ring gate 4 was demonstrated in FIG. 1, it is clear that even if it is the octagonal shape of FIG. 2, it can be comprised similarly. Furthermore, any polygonal shape can be adopted if it is annular.

  8 and 9 relate to a second embodiment of the present invention, FIG. 8 is a plan view showing a planar shape of one sensor cell of a solid-state imaging device according to the second embodiment, and FIG. It is typical sectional drawing which shows the cross-sectional shape of this sensor cell. FIG. 9 shows a cross section taken along line A-A 'of FIG. In FIG. 8 and FIG. 9, the same components as those in FIG. 2 and FIG.

  This embodiment differs from the first embodiment of FIG. 2 in the planar shape of the ring gate. As described above, no parasitic current flows on the control pocket 19. That is, the ring gate on the control pocket 19 does not contribute to the channel current. Therefore, this part of the ring gate is unnecessary.

  In the present embodiment, a portion on the control pocket 19 that does not contribute to the channel current is removed from the ring gate 14 (broken line in FIG. 8) in the first embodiment to form a ring gate 14 ′. Yes.

  According to such a configuration, a part of the ring gate that does not contribute to the channel current is removed without affecting the substrate modulation. Thereby, refinement | miniaturization can be accelerated | stimulated.

  Other configurations and operations are the same as those in the first embodiment.

  In the present embodiment, it is obvious that an arbitrary polygonal shape such as a quadrangular shape can be adopted as the shape of the modulation transistor including the ring gate.

  10 to 13 relate to a third embodiment of the present invention. FIG. 10 is a plan view showing a planar shape of one sensor cell of a solid-state imaging device according to the third embodiment. FIG. It is typical sectional drawing which shows the cross-sectional shape of this sensor cell. FIG. 11 shows a cross section taken along line A-A 'of FIG. 10 and FIG. 11, the same components as those in FIG. 2 and FIG.

  This embodiment differs from the first embodiment of FIG. 2 in the control pocket concentration. In the present embodiment, the density of the control pocket 19 ′ is set higher than the density of the carrier pocket 17.

  The operation of the embodiment configured as described above will be described with reference to FIGS. FIG. 12 is an explanatory diagram showing the potential based on the hole at the position of the line BB ′ in FIG. 11. FIG. 13 shows the incident light with the horizontal axis representing the light intensity and the vertical axis representing the pixel signal level. It is a graph which shows the relationship between the light intensity of this, and an output.

  Photogenerated charges are generated by the light incident on the photodiode formation region 2, transferred to the modulation well 54 through the collection well 53, and stored in the carrier pocket 17.

  A carrier pocket 17 and a control pocket 19 'are formed in the transistor formation region. However, a carrier pocket 17 is formed in a portion facing the photodiode formation region, and photogenerated charges are accumulated in the carrier pocket 17.

  The black circles in FIG. 12 indicate holes transferred from the collection well 53 and accumulated in the carrier pocket 17. The holes accumulated in the carrier pocket 17 are blocked by the sufficiently high potential barrier 10 and do not flow out to the control pocket 19 'side.

  In addition, the potential of the control pocket 19 'is lower than the potential of the carrier pocket 17, as shown in FIG. That is, the threshold value based on the potential of the control pocket 19 'is sufficiently high, and it is reliably prevented that a parasitic current flows in the surface channel on the control pocket 19'.

  In FIG. 13, the one-dot chain line shows the characteristic of the first embodiment, and the two-dot chain line shows the characteristic of the present embodiment. As is apparent from FIG. 13, in the present embodiment, the parasitic current can be further suppressed.

  As described above, in this embodiment, the potential of the control pocket is set lower than the potential of the carrier pocket, and the threshold by the control pocket is set higher than that of the first embodiment to further increase the generation of parasitic current. It can be reliably prevented.

The top view which shows the planar shape of 1 sensor cell of the solid-state imaging device which concerns on the 1st Embodiment of this invention. Explanatory drawing which shows the example whose planar shape of a modulation transistor is an octagon. Explanatory drawing which shows the basic structure for avoiding fixed pattern noise. 2 is a schematic cross-sectional view showing a cross-sectional structure of the sensor cell 1. FIG. FIG. 2 is a circuit block diagram showing an overall circuit configuration of a solid-state imaging device using a sensor cell array configured by arranging sensor cells 1 in a matrix by an equivalent circuit. Explanatory drawing which shows the potential on the basis of the hole in the position of the B-B 'line of FIG. The graph which shows the relationship between the light intensity and output of incident light, with light intensity on the horizontal axis and pixel signal level on the vertical axis. The top view which shows the planar shape of 1 sensor cell of the solid-state imaging device which concerns on 2nd Embodiment. The typical sectional view showing the section shape of a sensor cell. The top view which shows the planar shape of 1 sensor cell of the solid-state imaging device which concerns on 3rd Embodiment. FIG. 11 is a schematic cross-sectional view showing a cross-sectional shape of the sensor cell of FIG. 10. Explanatory drawing which shows the potential on the basis of the hole in the position of the B-B 'line | wire of FIG. The graph which shows the relationship between the light intensity and output of incident light, with light intensity on the horizontal axis and pixel signal level on the vertical axis.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Sensor cell, 2 ... Photodiode formation area, 3 ... Drain area | region, 4 ... Ring gate, 5 ... Source area | region, 7 ... Carrier pocket, 9 ... Control pocket.

Claims (5)

A photoelectric conversion element that generates a photo-generated charge according to incident light;
A modulation transistor disposed in a region adjacent to the photoelectric conversion element, the modulation transistor generating a signal according to a charge amount of the photogenerated charge;
In a solid-state imaging device including:
The modulation transistor is:
An annular gate,
A source region formed inside the annular gate;
A drain region formed outside the annular gate;
A carrier pocket formed below the annular gate located between the source region and the photoelectric conversion element, and holds a photo-generated charge from the photoelectric conversion element and changes a threshold value of the modulation transistor The carrier pocket;
A control pocket disposed below the annular gate where the carrier pocket is not formed via a potential barrier with the carrier pocket;
A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the carrier pocket is formed to have a linear shape between the source region and the photoelectric conversion element. The annular gate has a side facing the photoelectric conversion element in plan view,
The solid-state imaging device according to claim 1, wherein the carrier pocket has a linear shape along a side of the annular gate facing the photoelectric conversion element.   The solid-state imaging device according to claim 1, wherein the control pocket is set to have the same density as the carrier pocket.   The solid-state imaging device according to claim 1, wherein the control pocket is set at a higher density than the carrier pocket.

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