JP2006024778A - Submount chip applied sheet and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for efficiently manufacturing a submount chip applied sheet to which a plurality of submount chips are applied with a substantially continuous surface forming one end surface of a substrate and one end surface of a solder pattern. <P>SOLUTION: A metallic layer formed as an element bonding electrode is formed on the surface of a substrate, a submount chip material substrate is prepared as an insulating substrate having a plurality of solder patterns arranged and formed on the metallic layer, and a glass plate is bonded to one surface of the submount chip material substrate having the solder patterns. Thereafter, parts of the glass plate, the solder patterns, the metallic layer, and the insulating substrate are sequentially ground to form a cut guide groove; and then the glass plate is removed. Next, an adhesive sheet is applied to one surface of the obtained substrate having the solder patterns and to the opposing surface of the substrate, and then the substrate is cut into submount chips without fully cutting the adhesive sheet. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a submount chip attaching sheet on which a large number of chips that can be used as a submount are attached, and a method for manufacturing the same.

  The submount has a function as a substrate on which an element such as a semiconductor laser element is mounted, and also has a function to efficiently propagate heat generated from the element to the heat sink side by joining with a heat sink (a metal block such as copper). It is what you have. Such a submount generally has an electrode electrically connected to the element on one surface of an insulating substrate such as ceramics, and the other surface is electrically connected to the electrode via a via hole or the like as necessary. (Refer to Patent Document 1).

  Such submounts are generally very small ones having a length of about 1 mm, a width of about 1 mm, and a thickness of about 0.3 mm. For example, the submount has a size of about 50.8 mm square (2 inch square). A large number of submount patterns {a set of conductor patterns corresponding to one submount, that is, an electrode pattern on an element mounting surface and a solder pattern formed thereon; and a via hole and a backside conductor pattern formed as necessary } Are arranged in a matrix to form a “submount chip material substrate”, and the “submount chip material substrate” is formed on the adhesive sheet so that the solder layer serves as an adhesive surface while also protecting the solder layer. ”Is applied (without completely cutting the sheet), and the substrate is cut into a grid to divide each submount pattern. It has been prepared me. By adopting such a manufacturing method, small submount chips can be efficiently manufactured without being separated. The submount chip sticking sheet (also referred to as a submount chip sticking sheet) obtained in this way does not drop off during the distribution process, and each chip can be easily removed from the sheet during use. It is shipped after processing to adjust the adhesive force of the adhesive layer by means of ultraviolet irradiation or the like so that it can be peeled off (can be easily picked up) with a suitable strength (see Patent Document 2). .

Japanese Patent No. 316579 JP 2003-249464 A

  By the way, in recent semiconductor laser elements, there is a demand to make the light emitting surface of the element as close as possible to the end of the submount in order to improve the optical characteristics. For this reason, a solder pattern for joining the elements is required. Therefore, it is necessary to align the end with the end of the submount chip. In the case of manufacturing a submount that satisfies such requirements by the above-described method, it is considered that it is only necessary to cut one end portion of the solder layer when cutting the substrate.

  However, when the present inventors tried such a method, the solder layer is probably made of a soft metal, but there is a problem that many “burrs” or “burrs” are generated by cutting. It became clear that this occurred. Such occurrence of “burr” is not preferable because not only a process of removing “burr” is required, but also a decrease in product yield is caused. Therefore, the present invention has developed a method in which “burr” is unlikely to occur when cutting a solder pattern, so that one end surface of the substrate and one end surface of the solder pattern constitute a substantially continuous surface. An object of the present invention is to provide a submount chip sticking sheet in which a plurality of mount chips are stuck (attached), and to provide a method capable of efficiently producing such a submount chip sticking sheet.

  The present inventors have intensively studied to solve the above problems. As a result, when the glass plate is bonded to the surface having the solder pattern of the submount chip material substrate and then cut, the knowledge that the occurrence of “burrs” when the solder layer is cut is greatly reduced, The present invention has been completed.

  That is, the first aspect of the present invention comprises an insulating substrate having an element bonding electrode having a solder pattern formed on a surface thereof, one end surface of the insulating substrate, one end surface of the element bonding electrode, and the solder. A plurality of submount chips constituting a substantially continuous surface with one end surface of the pattern are pasted on the adhesive sheet with the surface opposite to the surface having the solder pattern as a bonding surface. It is a submount chip sticking (sticking) sheet characterized by becoming.

  Moreover, 2nd this invention is the manufacturing method of the submount chip | tip sticking sheet | seat of the said invention characterized by including the following process A, B, and C.

Step A: A step of preparing a submount chip material substrate made of an insulating substrate in which a metal layer to be an element bonding electrode is formed on the surface and a plurality of solder patterns are arrayed on the metal layer;
Step B: (B1) After joining the flash generation prevention plate to the surface of the submount chip material substrate having the solder pattern, (B2) from the flash generation prevention plate side, the flash generation prevention plate, the solder pattern, A submount chip having a cutting guide groove by sequentially grinding a part of the metal layer and the insulating substrate to form a cutting guide groove, and then (B3) removing the burr generation preventing plate from the submount chip material substrate. Step of obtaining material substrate and Step C: (C1) Submount chip material substrate having cutting guide groove obtained in step B above is bonded to the adhesive surface of the adhesive sheet and the surface opposite to the surface having the solder pattern (C2) A step of cutting the submount chip material substrate along the cutting guide groove without cutting the adhesive sheet after being attached as

  In order to provide a semiconductor laser device with good optical characteristics, chip pasting with a plurality of submounts on which the element can be mounted so that the light emitting surface of the element forms substantially the same surface as the end face of the submount (attachment) Pasting) Sheet is not known so far. The submount chip sticking sheet of the present invention is easy to handle such an excellent submount chip, specifically, it is affixed to the sheet in a state where it can be easily peeled off for easy transportation and management, According to the present invention, it is possible to obtain the same convenience as the conventional submount chip for the special submount chip. In addition, according to the manufacturing method of the present invention, it is possible to efficiently manufacture a new and highly convenient submount chip and a chip pasting (pasting) sheet on which the submount chip is pasted (pasted). Can do.

  Hereinafter, the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a perspective view of a representative submount chip attaching sheet 1 of the present invention, a cross-sectional view along the X-X ′ axis, and a partially enlarged view thereof. As shown in FIG. 1, in the submount chip attaching sheet 1, a plurality of submount chips 2 are formed on an adhesive sheet 3, a solder pattern 4 formed on the surface of the submount chip 2, and a base of the solder pattern 4. A plurality of elements are arranged and pasted with the surface opposite to the surface having the element bonding electrodes 5 as a bonding surface. The submount chip 2 is used as a submount for mounting a light emitting element such as a semiconductor laser element. Like the conventional submount, the submount chip 2 is electrically connected to one surface of an insulating substrate 6 such as ceramics. The element bonding electrode 5 is connected to the element bonding electrode 5, and a solder pattern 4 for reflow soldering the element is formed on the element bonding electrode 5. In the submount chip 2, the solder pattern 4 is formed in the vicinity of the end of the element mounting surface of the substrate, and at least one end surface s 1 of the insulating substrate 6 and at least one end surface of the element bonding electrode 5. s2 and at least one end surface s3 of the solder pattern constitute a substantially continuous surface (in other words, substantially located on the same surface).

  As the insulating substrate 6 used in the submount chip, a ceramic sintered body such as aluminum nitride, beryllium oxide, silicon carbide, alumina, mullite, boron nitride, silicon nitride, zirconia is preferably used. Among these, aluminum nitride is particularly suitable because it has a high thermal conductivity and efficiently releases the heat generated from the semiconductor laser element to the heat sink and is close in thermal expansion coefficient to Si, which is a typical material of the semiconductor laser element. Is done. In that case, it is preferable that the thermal conductivity of the substrate is high because the reliability of the semiconductor laser element is high, and those having a thermal conductivity of 170 W / mK or more, more preferably 200 W / mK or more are preferably used. In addition, although the thickness of a board | substrate is not specifically limited, The thickness of the board | substrate in a general submount is about 0.1-2 mm normally.

  The element bonding electrode 5 in the submount chip is connected to an element such as a semiconductor laser element (not shown) (specifically, an electrode surface of the element) via the solder pattern 4 to supply power to the element. . As a material of the element bonding electrode 5, a metal is usually used. The element bonding electrode may be composed of a single layer, but has good adhesion to the ceramic material because it has good adhesion to the ceramic substrate and is chemically stable and has high electrical conductivity. A base layer made of at least one material selected from the group consisting of titanium, chromium, molybdenum, tungsten, tungsten titanium, aluminum, nickel chromium, tantalum and tantalum nitride, and copper having high electrical conductivity formed thereon It is preferable to have a multilayer structure of a coating layer made of at least one metal selected from the group consisting of nickel, palladium, platinum and gold. The coating layer may be a single layer or a multilayer composed of different metals.

  The material of the solder pattern 4 formed on the element joining electrode 5 is a conventional submount such as lead / tin solder, gold / tin solder, gold / silicon solder, gold / germanium solder, etc. Any known solder material can be used without particular limitation. Further, a diffusion preventing layer for preventing the solder material from diffusing into the electrode layer may be provided between the element bonding electrode and the solder pattern. As the diffusion preventing layer, platinum, tungsten, tungsten titanium, and molybdenum having high diffusion preventing ability are preferably used. The thickness of the solder layer (solder pattern) is generally from 0.01 to 10 μm. However, the thickness of the solder layer is from 0.01 to 0.6 μm because “burrs” hardly occur. Is preferred. Also, the shape of the solder pattern is not particularly limited, but it is usually formed in substantially the same shape as the electrode of the element to be joined.

  The method of forming the element bonding electrode layer 5 and the solder pattern 4 is not particularly different from that in the case of manufacturing a conventional submount, and known metal thin film pattern forming techniques such as sputtering, vapor deposition, and ion plating are used. Can be adopted. Although not shown in FIG. 1, the submount chip 2 may be formed with a metal layer or an electrode on the surface opposite to the element mounting surface as in the conventional general submount. Further, a via hole penetrating the substrate may be formed to electrically connect the metal layers (electrodes) on both sides of the substrate.

  As the pressure-sensitive adhesive sheet 3, a pressure-sensitive adhesive sheet used in a conventional chip sticking sheet can be used without any particular limitation. It is preferable to use an adhesive sheet having an adhesive layer made of a material on the surface. Such sheets are commercially available and are commercially available. These sheets are generally a single-layer or multi-layer base made of a synthetic resin such as PVC (polyvinyl chloride), PET (polyethylene terephthalate), PO (polyolefin), or EVA (ethylene vinyl alcohol) having a thickness of about 10 to 200 μm. The material sheet has a structure in which a carboxylate-based pressure-sensitive adhesive layer that is cured by irradiating ultraviolet rays is applied in a thickness of 5 to 50 μm. In the present invention, since there is a possibility that a part of the pressure-sensitive adhesive sheet may be shaved in step C in the production method of the present invention described later, it is preferable to use a pressure-sensitive adhesive sheet having a thickness of 100 to 200 μm. .

  In the submount chip sticking sheet 1, a plurality of submount chips 2 are arranged and attached to the adhesive sheet 3, but the number of submount chips to be attached is not particularly limited as long as the number is two or more. The number is usually 50 to 5000, preferably 250 to 2500. The arrangement method is not particularly limited, but usually in a grid pattern, in other words, a line formed by connecting specific points (for example, center points) on each submount chip 2 forms a lattice. Thus, it is preferable to arrange them regularly at predetermined intervals in the vertical and horizontal directions. At this time, the distance between the submount chips 2 is preferably 0.05 to 1.0 mm, particularly 0.1 to 0.3 mm.

  Next, the manufacturing method of the submount chip | tip sticking sheet of this invention is demonstrated with reference to FIG. FIG. 2 is a view showing a manufacturing method flow of the present invention, and shows sectional views of materials, intermediates, and products in each step.

  As shown in FIG. 2A, in the manufacturing method of the present invention, first, as a process A, a submount chip material substrate 7 is prepared. The submount chip material substrate 7 is composed of an insulating substrate 6 ′ on which a metal layer 5 ′ to be an element bonding electrode 5 is formed and a plurality of solder patterns 4 are arranged on the metal layer 5 ′. Is. The submount chip material substrate 7 may be provided with a via layer (not shown) or a metal layer that will be the back electrode of the submount chip. Here, the metal layer 5 ′ may cover the entire surface of the insulating substrate 6 ′ according to the shape of the element bonding electrode 5 in the finally obtained submount chip 2 (in this case, element bonding). The electrode 5 covers the entire surface of the insulating substrate of the submount chip 2), and may be a plurality of independent (separated) metal layers each having a solder pattern on the surface. For convenience of the following description, a set of conductor patterns possessed by one submount chip 2, that is, a metal layer 5 ′ (in some cases, a metal layer 5 ′ that becomes an element bonding electrode 5 formed on the element mounting surface) A part) and a combination of the solder pattern 4 formed thereon and a via hole and a back conductor pattern formed as necessary are also referred to as a submount pattern unit.

  In short, the submount chip material substrate 7 is formed such that a plurality of submount pattern units are regularly arranged in, for example, a lattice shape or a grid pattern on the insulating substrate 6 ′, and each submount pattern unit is divided. The plurality of submount chips 2 can be obtained by cutting the insulating substrate 6 ′ as described above. Therefore, the insulating substrate 6 ′ constituting the submount chip material substrate 7 is made of the same material as the insulating substrate 6 of the submount chip 2, and the thickness thereof is the same as the thickness of the insulating substrate 6. The area is at least twice the main surface area of the insulating substrate 6, preferably 10 times or more. When the size of the submount chip 2 is about 0.5 to 5 mm in length, about 0.5 to 5 mm in width, and about 0.1 to 2 mm in thickness, the size of the submount chip material substrate 7 is 30 Generally, it is ˜300 mm square, particularly 50 to 150 mm square and the thickness is 0.1 to 2 mm.

  In the manufacturing method of the present invention, in step B, after (B1) bonding the flash generation prevention plate 8 to the surface of the submount chip material substrate 7 having the solder pattern, (B2) from the flash generation prevention plate 8 side, The burr generation preventing plate 8, the solder pattern 4, the metal layer 5 ′ and the insulating substrate 6 ′ are sequentially ground to form a cutting guide groove 9 which does not reach the opposite side of the insulating substrate 6 ′. B3) By removing the burr generation preventing plate 8 from the submount chip material substrate 7, a submount chip material substrate 7 ′ having a cutting guide groove is obtained. At this time, when cutting a place where the solder pattern 4 does not exist at all, “burr” hardly occurs or is small even if it occurs, so that other cutting points necessary for cutting out the submount chip 2 can be used. There is no particular need to provide a cutting groove, and when the substrate is cut along the cutting guide groove 9 in step C, the portion may be cut directly. It should be noted that before removing the flash generation prevention plate 8 from the submount chip material substrate 7 in the above (B3), such a place (for example, a line orthogonal to the cutting guide groove 9 and solder on the line) In the same manner, a groove serving as a cutting guide may be formed.

  The “flash generation preventing plate 8” used in the above (B1) presses the solder pattern in order to prevent the generation of “flash” made of a solder material when the cutting guide groove 9 is formed using a blade or the like. It has a function. The flash occurrence prevention plate 8 is a plate-shaped body of one or more, covers at least a portion where the cutting guide groove 9 is formed, and has a size in which a part thereof remains even after the cutting guide groove 9 is formed, It is not particularly limited as long as it does not substantially deform at the time of cutting. It is preferably made of a hard material, specifically glass or resin. The thickness of the flash generation preventing plate 8 is not particularly limited, but is preferably 100 μm to 5 mm, particularly 150 μm to 2 mm.

  An adhesive is used for bonding the flash prevention plate 8 to the surface of the submount chip material substrate 7 having the solder pattern. In this case, the adhesive is not particularly limited as long as the adhesive layer is not substantially deformed at the time of cutting and the solder layer and the electrode layer are not deteriorated, and cyanoacrylate adhesive, wax adhesive, and the like can be used. It can be used suitably. In joining (adhesion), the adhesive fills the gap 10 formed between the submount chip material substrate and the generation prevention plate (in other words, an adhesive layer is formed on the part). Is preferably performed). In this way, when the cutting guide groove 9 is formed or when the cutting guide groove is formed on a line orthogonal to the cutting guide groove 9 as described above, the solder pattern 4 is present on the upper part. It is possible to more reliably suppress the occurrence of “flash” derived from the portion of the metal layer 5 ′ that is not.

  In (B2), in order to form the cutting guide groove 9, at least one of the flash generation prevention plate 8, the solder pattern 4, the metal layer 5 ′ and the insulating substrate 6 ′ from the flash generation prevention plate 8 side. The parts need to be ground sequentially. By grinding in this way, the side surface of the cutting guide groove 9 on the side that becomes the submount chip 2 has one end surface s1 of the insulating substrate 6 ′ (of the portion that becomes the insulating substrate 6 of the submount chip 2), One end surface s2 of the element bonding electrode 5 and one end surface s3 of the solder pattern constitute a substantially continuous surface. The depth of the cutting guide groove is not particularly limited, but is preferably 1 to 70%, particularly 10 to 50% of the thickness of the insulating substrate 6 '.

  In (B3), the cutting guide groove 9 is formed, and after the "other cutting guide groove" is formed as necessary, the flash generation preventing plate 8 is removed from the submount chip material substrate 7, and the cutting guide is formed. A submount chip material substrate 7 ′ having grooves is obtained. At this time, in order to remove the flash generation prevention plate 8 from the submount chip material substrate 7, it is preferable to use an organic solvent. The organic solvent used at this time is not particularly limited as long as it dissolves the adhesive or swells the adhesive and acts to lose or weaken the adhesive force, and can be appropriately selected according to the adhesive used. Good. Examples of organic solvents that can be suitably used include acetone, ethanol, dichloromethane and the like. By immersing the submount chip material substrate 7 to which the flash prevention plate 8 is bonded in such an organic solvent, and applying ultrasonic vibration as necessary, the two can be easily separated.

  In the production method of the present invention, as the C process, (C1) the pressure-sensitive adhesive surface of the pressure-sensitive adhesive sheet comprising at least one surface of the submount chip material substrate 7 ′ having at least the cutting guide groove 9 obtained in the process B. After the surface opposite to the surface having the solder pattern is pasted as a bonding surface, (C2) the submount chip material substrate is cut along the cutting guide groove without cutting the adhesive sheet. The pressure-sensitive adhesive sheet is not particularly limited as long as it has a size that covers the entire substrate and has a pressure-sensitive adhesive force that does not cause peeling or displacement during cutting, and will be described in the submount chip attaching sheet of the present invention. The made adhesive sheet is used suitably. The cutting in (C2) is usually performed using a blade. Without completely cutting the adhesive sheet layer, (i) when cutting guide grooves are provided in advance at all the planned cutting positions, the substrate is cut along these cutting guide grooves, and (ii) If the cutting guide groove is provided at the planned cutting location of the part and the cutting guide groove is not provided at the other cutting planned location, the cutting is performed along the cutting guide groove and the predetermined location without the cutting guide groove is directly cut. Thus, the submount chip material substrate 7 ′ having the cutting guide groove can be divided to obtain the submount chip sticking sheet of the present invention. In cutting, the cutting depth of the pressure-sensitive adhesive sheet is preferably 50% or less, particularly 5% or less of the thickness. In addition, the above-mentioned scheduled cutting location means a cutting location where one submount pattern unit is included in all the fractions and the fraction becomes the submount chip 2 when divided.

  In the submount chip sticking sheet of the present invention thus manufactured, the surface of the submount chip having the solder pattern is exposed. Therefore, for the purpose of protecting the solder pattern (solder layer), it is preferable to cover the surface of the submount chip on which the solder pattern is formed with a protective film.

  EXAMPLES Hereinafter, although an Example and a comparative example are given and this invention is demonstrated in more detail, this invention is not limited to these Examples.

Production Example 1
A submount chip material substrate 7 shown in FIG. 2A was produced as follows. The submount chip material substrate 7 includes a metal layer 5 ′ in which a first base layer mainly composed of Ti and a platinum electrode layer 2 are laminated in this order on an insulating substrate 6 ′ made of an aluminum nitride sintered body; The diffusion preventing layer mainly composed of Ag and the solder pattern 4 (solder layer) mainly composed of Sn are stacked in this order.

  That is, first, Ti having a thickness of 0.06 μm is mainly formed on the entire surface of a sintered aluminum nitride substrate {50.8 mm × 50.8 mm × 0.20 mmt manufactured by Tokuyama Co., Ltd.} by sputtering using a sputtering apparatus. A first underlayer as a component and a platinum electrode layer having a thickness of 0.6 μm were sequentially formed. Next, a diffusion prevention layer pattern made of silver and a solder pattern with a thickness of 6.5 μm made of Sn are formed on the platinum electrode layer by a vacuum evaporation method using a metal mask, and a submount chip material is formed. A substrate 7 was produced. The diffusion prevention layer pattern and the solder pattern are both 0.9 × 0.17 rectangles, and the vertical and horizontal rows of the aluminum nitride sintered substrate are 43 rows and 50 rows (2150 in total). Arranged regularly in a grid pattern.

Example 1
First, a cover glass {52 mm × 52 mm × 0.15 mm manufactured by Matsunami Glass Industry Co., Ltd.} is applied to the surface of the submount chip material substrate 7 obtained in Production Example 1 on which the solder layer is formed. A cyanoacrylate adhesive {Aron Alpha 401X Bonded by Toagosei Co., Ltd.}. Next, a cover glass, a solder layer, a diffusion prevention layer, a metal layer, and a part of the insulating substrate were cut from the cover glass side by a dicing machine using a 0.1 mm thick blade obtained by sintering diamond powder (the bottom surface of the insulating substrate). To 0.15 mm), a cutting guide groove 9 was formed. Thereafter, the cover glass is peeled off from the substrate by immersing the substrate in acetone, and a carboxylic acid ester-based UV curable adhesive sheet {GD-30 manufactured by Toyo Adtec Co., Ltd. is provided on the surface opposite to the surface on which the solder layer is formed. } Was pasted, and the insulating substrate was completely cut along the cutting guide groove 9 by a dicing machine using a blade having a thickness of 0.05 mm. At this time, the pressure-sensitive adhesive sheet layer was cut leaving 0.06 mm. Next, by leaving the adhesive sheet layer at 0.06 mm and cutting other portions to be cut (lines perpendicular to the cutting guideline) in the same manner, a submount sticking sheet is produced, and the end face of the submount chip and the end face of the solder part The number of occurrences of metallization burrs on the continuous surface constituted by was examined. As a result, the number of metallized burrs having a width of 20 μm or more was 37 chips out of 2150 chips.

Comparative Example 1
Using the submount chip material substrate 7 obtained in Production Example 1 as it is, a carboxylic acid ester-based UV curable adhesive sheet {GD-30 manufactured by Toyo Adtec Co., Ltd.} on the surface opposite to the surface on which the solder layer is formed. And a substrate material layer is completely cut with a dicing machine using a blade having a thickness of 0.05 mm, leaving 0.06 mm of the adhesive sheet layer, and a submount affixing sheet is produced. The number of occurrences of metallization burrs on the continuous surface formed by the end face of the solder part was inspected. As a result, metallized burrs having a width of 20 μm or more were generated on all 2150 chips.

This figure is a perspective view of a representative submount chip sticking sheet 1 of the present invention, a cross-sectional view along the X-X ′ axis, and a partially enlarged view thereof. This figure is a figure which shows the manufacturing flow of this invention.

Explanation of symbols

1: Submount chip sticking sheet 2: Submount chip 3: Adhesive sheet 4: Solder pattern 5: Electrode bonding electrode 5 ': Metal layers 6, 6': Insulating substrate 7: Submount chip material substrate 7 ': Cutting guide Submount chip material substrate 8 having a groove: Burr generation prevention plate 9: Cutting guide groove 10: Gap portion s1: End surface s2 of insulating substrate 6: End surface s3 of element bonding electrode 5: End surface of solder pattern 4

Claims (5)

An element bonding electrode having a solder pattern is formed of an insulating substrate formed on the surface, and one end face of the insulating substrate, one end face of the element bonding electrode, and one end face of the solder pattern are substantially formed. A submount chip sticking sheet, wherein a plurality of submount chips constituting a continuous surface are affixed to an adhesive sheet with a surface opposite to the surface having the solder pattern as a bonding surface. The manufacturing method of the submount chip | tip sticking sheet | seat of Claim 1 characterized by including the following process A, B, and C.
Step A: A step of preparing a submount chip material substrate made of an insulating substrate in which a metal layer to be an element bonding electrode is formed on the surface and a plurality of solder patterns are arrayed on the metal layer;
Step B: After bonding a flash generation prevention plate to the surface having the solder pattern of the submount chip material substrate, the flash generation prevention plate, the solder pattern, the metal layer, and the insulating substrate from the flash generation prevention plate side. A step of sequentially grinding a part of the substrate to form a cutting guide groove, and then removing the burr generation preventing plate from the submount chip material substrate to obtain a submount chip material substrate having a cutting guide groove; and Step C: Affixing the submount chip material substrate having the cutting guide groove obtained in the above step B to the adhesive surface of the adhesive sheet with the surface opposite to the surface having the solder pattern being bonded, and then cutting the adhesive sheet Cutting the submount chip material substrate along the cutting guide groove without cutting In the step B, the submount chip material substrate and the flash generation prevention plate are joined using an adhesive so that the adhesive fills a gap formed between the submount chip material substrate and the generation prevention plate. The method according to claim 2, wherein the method is performed as follows. The method according to claim 2 or 3, further comprising the following step D.
Process D: The process of coat | covering the surface in which the solder pattern of the submount chip | tip stuck on the chip | tip sticking sheet obtained by the said process C is formed with a protective film The method includes the following steps A, B, and C, and an element bonding electrode having a solder pattern formed of an insulating substrate formed on the surface, at least one end surface of the insulating substrate, and the element bonding electrode A method for manufacturing a submount chip, wherein at least one end surface and at least one end surface of the solder pattern constitute a substantially continuous surface.
Step A: A step of preparing a submount chip material substrate made of an insulating substrate in which a metal layer to be an element bonding electrode is formed on the surface and a plurality of solder patterns are arrayed on the metal layer;
Step B: After bonding a flash generation prevention plate to the surface having the solder pattern of the submount chip material substrate, the flash generation prevention plate, the solder pattern, the metal layer, and the insulating substrate from the flash generation prevention plate side. To form a cutting guide groove that does not reach the opposite side of the insulating substrate, and then removes the burr generation prevention plate from the submount chip material substrate to obtain a submount chip material substrate having a cutting guide groove And Step C: After the submount chip material substrate having the cutting guide groove obtained in Step B is pasted on the pressure-sensitive adhesive surface of the pressure-sensitive adhesive sheet with the surface opposite to the surface having the solder pattern as a bonding surface, A step of cutting the submount chip material substrate along the cutting guide groove without cutting the adhesive sheet

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