JP2006023829A - Data fetching device and data fetching method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make processing more efficient by reducing a control signal line between a FIFO memory and a CPU. <P>SOLUTION: This data fetching device is configured to fetch the data of a FIFO memory through a data bus in a CPU. Information showing the various status change of the FIFO memory is stored by a register, and when the various status change of the FIFO memory is generated, an interrupting signal is supplied to the CPU, and the storage contents of the register are supplied through the data bus to the CPU, and the various status change of the FIFO memory is judged, and the data to be supplied from the FIFO memory through the data bus are fetched in the CPU based on the judged various status change of the FIFO memory. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data capturing device and a data capturing method for capturing data in a FIFO memory into a CPU.

  2. Description of the Related Art Conventionally, in a data fetching device that fetches data from a FIFO (First In First Out) memory into a CPU, the CPU monitors the state by a control signal from the FIFO memory. These control signals include full (FULL), empty (EMPTY), and half (HALF FULL), and the FIFO memory and the CPU are directly connected to each other by separate signal lines.

Also, when fetching data from the FIFO memory into the CPU, DMA transfer is often used for high-speed transfer, but it is fixed size transfer. (Patent Document 1)
Therefore, since it is necessary to connect a plurality of control signal lines to the CPU for monitoring the FIFO memory state, there is a problem because there are restrictions on the number of I / O and the number of interrupts depending on the CPU.

When the DMA transfer has a fixed length, it becomes inefficient because it is necessary to devise a method such as filling in dummy data where variable length data is insufficient.
JP-A-5-257867

  According to the present invention, when the data is transferred from the FIFO memory to the CPU, the control signal line can be reduced and the processing efficiency can be improved by switching the FIFO memory and the register.

  The data fetching apparatus according to the present invention fetches data from a FIFO memory into a CPU via a multi-bit data bus. A register for storing information indicating various state changes of the FIFO memory; When various state changes occur, the CPU supplies an interrupt signal to the CPU, supplies the stored contents of the register to the CPU via the data bus, and an interrupt supplied by the supply means. A determination means for determining various state changes of the FIFO memory based on the data signal and information indicating various state changes of the FIFO memory supplied via the data bus, and the FIFO determined by the determination means Data supplied from the FIFO memory via the data bus to the CPU based on various state changes of the memory And a writing capturing means.

  The data capturing device of the present invention is configured by data type, data length, and data string supplied from an external device when data or commands from a FIFO memory are captured by a CPU via a multi-bit data bus. Or a receiving means for receiving a command composed of data type, data type, data length, and command string, and a data string or a command string accepted by the receiving means are sequentially stored in the FIFO memory, and input from the FIFO memory first. Output means for outputting data or commands in order, and outputting signals indicating various state changes, and storing the information by signals indicating various state changes by the output means, and the data type received by the receiving means And a register that stores the data length, and supplied from an external device When a signal indicating the data or command supply status is supplied, or when various status changes of the FIFO memory occur, an interrupt signal is supplied to the CPU, and the stored contents of the register are changed to the data Based on the supply means supplied via the bus, the interrupt signal supplied by the supply means, and the stored contents of the register supplied via the data bus, various state changes of the FIFO memory are determined. Based on various state changes of the FIFO memory determined by the determination means, a determination means for acquiring data or commands supplied from the FIFO memory via the data bus to the CPU, and the acquisition The data or command fetched into the CPU by the fetching means is changed to the data type and data length supplied by the feeding means. And a storage means for storing in memory Zui.

  According to the present invention, when the data from the FIFO memory is taken into the CPU via the data bus, the control signal line between the FIFO memory and the CPU can be reduced, and the processing efficiency can be improved.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a data fetching apparatus and its peripheral circuit configuration according to the present invention.

  That is, the imaging unit 1 configured by a CCD sensor supplies analog data in pixel units as read data to the A / D converter 2. The A / D converter 2 converts the supplied analog data into digital serial data, and supplies the digital data to a data capturing device 3 having a FIFO memory described later.

  The data capture device 3 captures the supplied digital serial data and transfers it to the CPU 4. In addition, a CPU 5 that monitors sensor abnormality based on the output of the A / D converter 2 is provided.

  As a result, the CPU 4 is supplied with the content captured by the imaging unit 1.

  As shown in FIG. 2, the data fetching apparatus 3 includes a FIFO memory 101, a register 102, an OR circuit 103, a selector 104, and buffers 105 and 106.

  The FIFO (first-in first-out) memory 101 outputs data in order from the first stored in the first-in first-out method.

  Next, in the configuration as described above, the data fetching operation will be described with reference to the flowchart shown in FIG.

  For example, now serial data from the A / D converter 2 is supplied to the data input terminal DI of the FIFO memory 101.

  As a result, the FIFO memory 101 sequentially stores the supplied data, and outputs an HF state signal when the FIFO memory 101 enters the HF (half full) state. The HF state signal is supplied to the register 102 and also supplied to the selector 104 and the INT terminal of the CPU 4 as an interrupt signal via the OR circuit 103 (ST201). The selector 104 outputs an enable signal to the buffer 105 when this interrupt signal is supplied. As a result, the HF state signal (information indicating the HF state) stored in the register 102 is supplied to the DB terminal of the CPU 4 via the buffer 105 (ST202).

  At this time, the CPU 4 reads the HF state signal (information indicating the HF state) as information of the register 102 supplied to the DB terminal only once by the interrupt signal to the INT terminal (ST203).

  When the reading is completed, the CPU 4 supplies a read signal from the OE terminal to the selector 104 and also to the OE terminal of the FIFO memory 101. When this read signal is supplied (selector 104 confirms that there is a CPU read) (ST204), selector 104 outputs an enable signal to buffer 106. As a result, the selector 104 switches the data bus to the FIFO memory 101 side, and data from the data output terminal DO of the FIFO memory 101 is supplied to the DB terminal of the CPU 4 via the buffer 106 (ST205).

  That is, the selector 104 monitors the read (OE) signal, and when it is confirmed that the CPU 4 has read the register 102 (ST204), the data bus is switched to the FIFO memory 101 (ST205).

  The CPU 4 confirms that an HF signal has been generated based on information indicating the HF state as information in the register 102 (ST206), and starts taking in data supplied to the OE terminal (ST209, ST211).

  Further, when the CPU 4 confirms the information indicating the full state as the register information in step 206, the CPU 4 starts taking in the data supplied to the OE terminal (ST209, ST211).

  Further, when the CPU 4 confirms empty (empty) as the register information in step 206, the CPU 4 stops taking in data (ST207, ST210).

  Further, when the CPU 4 confirms the stop signal as the register information in step 206, the CPU 4 stops taking in data (ST208, ST210).

  Further, when nothing is confirmed as the register information in step 206, the CPU 4 generates an error without an interrupt condition (ST207 to ST209, ST212).

  Next, an embodiment when the present invention is applied to DMA transfer will be described.

  In other words, processing is performed from the A / D converter 2 to the data capturing device 3 using a message including a data length, a data type, and data (command).

  As the above-mentioned message, when reading data from the CCD sensor 1 is described, when an abnormality is described by the CPU 5, a command indicating an abnormality is described, and when a stop is determined by the CPU 5 In some cases, a command indicating a stop is described.

  When the message is data, as shown in FIG. 4, it is composed of a start code STX, a data length N, a data type DATA, data 0, 1,..., An end code ETX.

  When the message is a command (stop or abnormality information), as shown in FIG. 5, it is composed of a start code STX, a data length N, a data type COM, commands 0, 1,.

  Also, as shown in FIG. 6, a DMA memory 6 having a command area and a data area is connected to the CPU 4.

  Further, as shown in FIG. 6, the data fetching device 3 receives a message from the A / D converter 2, analyzes the message, and outputs a data type and a data length to the register 102. An input unit 107 that outputs commands to the FIFO memory 101 is provided.

  In addition, data capture and DMA transfer may be stopped by a stop signal supplied from the outside. In this case, the stop signal is supplied to the register 102 and the OR circuit 103 as shown in FIG.

  Next, with reference to the flowchart shown in FIG. 7 in the configuration as described above, the data fetching operation will be described.

  For example, a message as shown in FIG. 4 is supplied from the A / D converter 2 to the input unit 107. The input unit 107 analyzes the message, discriminates the data length N and the data type DATA following the start code STX into the register 102, and until the end code ETX determines the data 0, 1,... Following the data type. The data is supplied to the data input terminal DI of the FIFO memory 101.

  As a result, the FIFO memory 101 sequentially stores the supplied data, and outputs an HF state signal when the FIFO memory 101 enters the HF (half full) state. This HF state signal is supplied to the register 102 and also supplied to the selector 104 and the INT terminal of the CPU 4 as an interrupt signal via the OR circuit 103 (ST301). The selector 104 outputs an enable signal to the buffer 105 when this interrupt signal is supplied. As a result, the HF status signal, data type, and data length stored in the register 102 are supplied to the DB terminal of the CPU 4 via the buffer 105 (ST302).

  At this time, the CPU 4 reads the HF state signal, the data type, and the data length as information of the register 102 supplied to the DB terminal only once by the interrupt signal to the INT terminal (ST303).

  When the reading is completed, the CPU 4 supplies a read signal from the OE terminal to the selector 104 and also to the OE terminal of the FIFO memory 101. When this read signal is supplied (selector 104 confirms that there is a CPU read) (ST304), selector 104 outputs an enable signal to buffer 106. As a result, the selector 104 switches the data bus to the FIFO memory 101 side, and data from the data output terminal DO of the FIFO memory 101 is supplied to the DB terminal of the CPU 4 via the buffer 106 (ST305).

  That is, the selector 104 monitors the read (OE) signal, and when it is confirmed that the CPU 4 has read the register 102 (ST304), the data bus is switched to the FIFO memory 101 (ST305).

  The CPU 4 confirms the HF state signal, the data type, and the data length as information of the register 102 (ST306), starts taking in the data supplied to the OE terminal, and sets the taken data according to the data type. The data is transferred to the DMA transfer destination, and data corresponding to the DMA transfer amount set according to the data length is transferred (ST309 to ST312).

  Further, when the CPU 4 confirms the information indicating the full state as the register information in step 306, the CPU 4 starts taking in data supplied to the OE terminal and DMA transfer (ST309 to ST312).

  Further, when the CPU 4 confirms empty (empty) as the register information in step 306, the CPU 4 stops the DMA (ST307, ST313).

  Further, when the CPU 4 confirms the stop signal as the register information in step 306, the CPU 4 stops the DMA (ST308, ST313).

  Further, when nothing is confirmed as the register information in step 306, the CPU 4 generates an error without an interrupt condition (ST307 to ST309, ST314).

  Thus, DMA transfer can be efficiently performed by putting the data type, data length, and the like in the register information.

  Further, the CPU 4 can switch the write destination of the external memory 6 and divide the memory arrangement from the data type in the register information, for example, from information such as whether the data is a command or data. Further, the CPU 4 determines the DMA transfer amount based on the data length information, and can perform transfer according to the data length.

  Also, information for stopping DMA transfer, which is used when the transfer is forcibly stopped from outside, can be added. By describing the stop command as the CMD in the command message, the DMA transfer is stopped when the CMD (stop command) is analyzed by the CPU 4.

  As described above, the interrupt signal is used to switch the data bus from the FIFO memory to the register, and after confirming that the CPU has read the register, the CPU returns to the FIFO memory to transmit control information to the CPU.

  Also, by providing the register information with the data length, data type, etc., DMA transfer is controlled and performed efficiently.

  Thereby, the control signal line between the FIFO memory and the CPU can be reduced.

  In addition, when applied to DMA transfer, data can be acquired quickly and efficiently.

  Furthermore, the data transfer destination can be changed depending on the data, and the memory management becomes easy.

  Next, an example of an embodiment using the above invention will be described with reference to a configuration example shown in FIG.

  In this case, the extreme end point of the paper sheet is detected by image processing on the binarized image obtained based on the imaging content obtained by imaging the paper sheet P.

  For example, as shown in FIG. 8, a data receiving unit 201, a data compression unit 202, a selection unit 203, and a data storage unit 204 are provided between the A / D converter 2 and the data capturing device 3 shown in FIG. It is the provided configuration.

  The data receiving unit 201 takes in digital serial data supplied from the A / D converter 2 and supplies the digital serial data to the data compression unit 202, the selection unit 203, and the data storage unit 204. The data compression unit 202 compresses the supplied data and supplies the compressed data to the selection unit 203. The selection unit 203 selectively supplies data from the data reception unit 201 or data from the data compression unit 202 to the data capturing device 7. The data storage unit 204 stores data supplied from the data reception unit 201.

  As a result, the CPU 8 is supplied with the compressed image captured by the image capturing unit 1 as it is, and the CPU 8 detects the extreme end of the paper sheet by image processing on the binarized image obtained based on the captured image. It is supposed to be.

BRIEF DESCRIPTION OF THE DRAWINGS The block diagram which shows schematic structure of the data acquisition device for describing one Embodiment of this invention, and its peripheral circuit. The block diagram which shows schematic structure of a data taking-in apparatus. The flowchart for demonstrating the operation | movement of taking in data. The figure for demonstrating the structural example in case a message | telegram is data. The figure for demonstrating the structural example in case a message is a command. The block diagram which shows schematic structure of a data taking-in apparatus. The flowchart for demonstrating the operation | movement of taking in data. The block diagram which shows schematic structure of a data capture device and its peripheral circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Imaging part 2 ... A / D converter 3 ... Data capture device 4, 5 ... CPU 101 ... FIFO memory 102 ... Register 104 ... Selector 105, 106 ... Buffer

Claims (5)

In a data capturing device that captures data in a FIFO memory into a CPU via a multi-bit data bus,
A register for storing information indicating various state changes of the FIFO memory;
Supply means for supplying an interrupt signal to the CPU when various state changes of the FIFO memory occur, and supplying the stored contents of the register to the CPU via the data bus;
Determining means for determining various state changes of the FIFO memory based on an interrupt signal supplied by the supplying means and information indicating various state changes of the FIFO memory supplied via a data bus;
Fetching means for fetching data supplied from the FIFO memory via the data bus to the CPU based on various state changes of the FIFO memory judged by the judging means;
A data capture device comprising: In a data capturing method for capturing data in a FIFO memory into a CPU via a multi-bit data bus,
Information indicating various state changes of the FIFO memory is stored in a register;
When various state changes of the FIFO memory occur, an interrupt signal is supplied to the CPU, and the stored contents of the register are supplied to the CPU via the data bus,
Based on the supplied interrupt signal and information indicating various state changes of the FIFO memory supplied via the data bus, various state changes of the FIFO memory are determined,
Based on the determined various state changes of the FIFO memory, the data supplied from the FIFO memory via the data bus is taken into the CPU.
A data capturing method characterized by that. In a data capture device that captures data or commands from a FIFO memory into a CPU via a multi-bit data bus,
An accepting means for receiving data configured from a data type, a data length, and a data sequence, or a command configured from a data type, a data length, and a command sequence supplied from an external device;
An output means for sequentially storing the data string or command string received by the receiving means in the FIFO memory, outputting the data or command in order from the FIFO memory, and outputting signals indicating various state changes;
A register that stores the information by signals indicating various state changes by the output means, and stores the data type and data length received by the receiving means,
When a signal representing the supply status of data or commands supplied from an external device is supplied, or when various status changes of the FIFO memory occur, an interrupt signal is supplied to the CPU, and Supply means for supplying stored contents via the data bus;
Judging means for judging various state changes of the FIFO memory based on the interrupt signal supplied by the supplying means and the stored contents of the register supplied via the data bus;
Fetching means for fetching data or commands supplied from the FIFO memory via the data bus to the CPU based on various state changes of the FIFO memory judged by the judging means;
Storage means for storing the data or command fetched by the fetch means into the CPU based on the data type and data length supplied by the supply means;
A data capture device comprising: In a data capture method for capturing data or commands from a FIFO memory into a CPU via a multi-bit data bus,
Accepts data supplied from an external device, consisting of data type, data length and data string, or command consisting of data type, data length and command string,
The received data sequence or command sequence is sequentially stored in the FIFO memory, and sequentially output from the data or command previously input from the FIFO memory, and signals indicating various state changes are output,
Information by signals indicating various state changes due to this output, the received data type and data length are stored in a register having the same number of bits as the data bus,
When a signal indicating the supply status of data or commands supplied from an external device is supplied, or when various status changes of the FIFO memory occur, an interrupt signal is supplied to the CPU, and The stored contents are supplied via the data bus,
Based on the supplied interrupt signal and the stored contents of the register supplied via the data bus, various state changes of the FIFO memory are determined,
Based on the determined state changes of the FIFO memory, data or commands supplied from the FIFO memory via the data bus are taken into the CPU.
The data or command taken into the CPU is stored in the memory based on the supplied data type and data length.
A data capturing method characterized by that. In a data capture device that captures data or commands from a FIFO memory into a CPU via a multi-bit data bus,
An accepting means for receiving data configured from a data type, a data length, and a data sequence, or a command configured from a data type, a data length, and a command sequence supplied from an external device;
An output means for sequentially storing the data string or command string received by the receiving means in the FIFO memory, outputting the data or command in order from the FIFO memory, and outputting signals indicating various state changes;
A register that stores the information by signals indicating various state changes by the output means, and stores the data type and data length received by the receiving means,
Supply means for supplying an interrupt signal to the CPU and supplying the stored contents of the register via the data bus when a signal representing a supply state of data or a command supplied from an external device is supplied; ,
Determination means for determining various state changes of the FIFO memory based on the interrupt signal supplied by the supply means and the stored contents of the register supplied via the data bus;
Fetching means for fetching data or commands supplied from the FIFO memory via the data bus to the CPU based on various state changes of the FIFO memory judged by the judging means;
Storage means for storing the data or command fetched by the fetch means into the CPU based on the data type and data length supplied by the supply means;
A data capture device comprising:

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