JP2006014211A - Network control unit, image processor, and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent receiving buffers from being overflowed by a hardware when packet processing of CPU is slower than receiving speed, and receiving buffers configured on a memory are short. <P>SOLUTION: This device is provided with a network interface 600 including MAC 140, an interface 160 between CPU 400 which prepares receiving buffers per packet and manages them, and a memory controller 170 which is connected to memory 500. The network interface 600 has a register to record the number of receiving packet buffers prepared on the memory 500 by a software, the number of actual receiving buffers. The number of receiving packets processed by the software; and performs automatic flow control to prevent the receiving buffers from being overflowed when the number of packets processed by the software is subtracted from the number of the received packets. The substrated value exceeds the preset upper limit value of total number of the receiving buffers prepared on the memory by the software. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a network control apparatus that automatically performs a flow control operation of a network interface such as a printer, a copy, and an MFP (multifunction peripheral), an image processing apparatus including the network control apparatus, and an image forming apparatus.

  In many cases, the received packet processing in the network interface is executed by generating an interrupt to the CPU every time one packet is received. However, with the recent increase in network speed, the overhead of processing time due to the occurrence of interrupt processing for each packet increases, and there is a high possibility that the amount of packets processed by the CPU cannot keep up with the amount of packets received. I came.

  For this reason, instead of processing every packet, a method of starting packet processing by receiving a certain number of packets or elapse of a certain time has started. As a result, the number of interrupt processing occurrences can be reduced, and the total processing time can be shortened. The reception buffer size is also increased, and there is a movement to cope with the efficiency improvement by the concentration of processing.

  On the other hand, the inventions described in Patent Documents 1 to 3 are known as this type of technology. Among them, Patent Document 1 stores a received packet and received information in a local memory and a local memory for the purpose of providing a communication device that can greatly improve the processing capability of the system. Based on received information, packet reception result determination and processing at the time of resource release, detection of local memory storage amount, determination of whether or not the detected storage amount has reached the setting condition, and the storage amount as the setting condition A communication device is described that includes a local CPU that issues a packet reception notification to the host CPU when it reaches the target CPU, shortens the processing time per packet, and improves the processing capacity of the system.

  In Patent Document 2, the FIFO temporarily holds data from the decoder for the purpose of easily realizing flow control and reducing quantization error in data transfer via the IEEE 1394 serial bus. At this time, the counter counts the number of packets transmitted from the FIFO onto the IEEE bus, and when the data transfer amount is increased according to the register transmission instruction, transfer of empty packets is performed. When data packets are sometimes transmitted to reduce the amount of data transfer, empty packets are transmitted at the transmission timing of the data packets, and the data amount monitoring unit causes the FIFO to overflow or become empty due to flow control. Request / stop data to the decoder via the data input controller. Unishi out data transfer apparatus is described.

Further, Patent Document 3 aims to provide a packet buffer whose configuration can be simplified, and a buffer control unit is provided in a buffer memory based on an input data synchronization clock, an input packet synchronization signal, and an input packet strobe signal. The buffer write signal is supplied, the input packet data is stored, the packet length counter obtains the packet length of the input packet data and sequentially supplied to the packet length buffer memory, and the buffer control unit outputs the output data synchronization clock and the output packet synchronization signal. There is described a packet buffer that sequentially reads packet lengths from a packet length buffer memory and supplies a buffer read signal corresponding to the packet length to the buffer memory to control reading of output packet data.
JP 2001-0777847 A JP 2002-354051 A Japanese Patent Laid-Open No. 9-247213

  However, regardless of the CPU having a high processing capacity, even in the case of a CPU having a low processing capacity, the packet processing is not always in time for these countermeasures. A CPU with a high processing capability increases in cost, and it is not a perfect measure for printers and MFPs (multifunction peripherals) that are becoming lower in price as the reception buffer size is increased. In addition, the CPU often performs not only packet processing but also image drawing and other interface processing.

  In addition, when other processes are started in parallel, the network packet processing speed is also reduced, and even if the above countermeasures are taken, the reception buffer may overflow. If overflow occurs, the packet that should have been received is lost, and packet retransmission processing is required. This means that communication time is longer than necessary.

  In addition, in the techniques described in Patent Documents 1 to 3, techniques for shortening the processing time per packet are disclosed, but since both are configurations using software, when trying to shorten the processing time, Accordingly, a CPU having a high processing capacity must be used, and the cost must be increased.

  The present invention has been made in view of such a technical background. When the packet processing of the CPU falls below the reception speed and the reception buffer configured on the memory is about to be exhausted, the reception buffer is executed by hardware. The purpose is to prevent overflow.

  To achieve the above object, a network control apparatus according to a first means includes a network interface unit including a MAC, an interface unit with a CPU that prepares and manages a reception buffer in packet units, and a memory controller connected to a memory. The network interface unit has a register for recording the number of received packet buffers prepared on the memory by the software, the actual number of received packets, and the number of received packets processed by the software. The number of packets processed by the software is subtracted from the number of received packets, and when the value exceeds the preset upper limit of the total number of receive buffers prepared in the memory, flow control is automatically performed and the receive buffer To prevent it from overflowing And butterflies.

  The network control apparatus according to the second means includes a network interface unit including a MAC, an interface unit with a CPU that collectively prepares reception buffers and manages them in packet units, and a memory controller unit connected to a memory, The network interface unit has a register for recording the number of received packet buffers prepared by the software in the memory, the actual number of received packets, and the number of received packets processed by the software. If the number of bytes processed by the software is subtracted from the number of bytes, and the value exceeds the preset upper limit of the total number of bytes in the receive buffer prepared in the memory, flow control is automatically performed and received. Special features to prevent the buffer from overflowing To.

  A third means is characterized in that, in the first or second means, the network interface unit includes a physical layer device and a DMA controller in addition to the MAC.

  According to a fourth means, in the network control device according to the first to third means, the MAC of the network interface unit, the DMA controller, the interface unit, and the memory controller unit are configured by an ASIC. And

  A fifth means is the fourth means, characterized in that the ASIC includes a memory arbiter between a memory and / or a mass storage device as a connected common resource.

  The sixth means has a plurality of application functions, each of the application functions uses at least a memory as a shared resource, and images the network control apparatus according to the first to fifth means that operate according to an operation command from a client computer. A processing apparatus is provided.

  The seventh means is characterized in that the image forming apparatus includes the image processing apparatus according to the sixth means.

  According to the present invention, when the reception buffer configured on the memory is about to be exhausted, the hardware detects it and prevents the reception buffer from overflowing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing an example of the configuration of an ASIC as a hardware configuration according to the first embodiment of the present invention.

  The ASIC 100 has a function as a network control device including a network interface. A hard disk device (HDD), a physical layer device 300, a CPU 400, and a memory 500 are connected to the memory arbiter 110. The ASIC 100 includes an HDD interface 120 for connecting to the HDD 200, a USB interface 130 to which a USB terminal is connected, a MAC (Media Access Controller) 140 connected to the physical layer device 300, an SD card interface 150 to which an SD card is connected, A CPU interface 160 to which the CPU 400 is connected, a memory controller 170 to which the memory 500 is connected, a printer engine interface 180 to which the printer engine is connected, and an IEEE1284 interface 190 to which an IEEE1284 terminal is connected are further provided. 130, MAC 140 and SD card interface 150 and memory arbiter 11 DMA controllers 121, 131, 141, and 151 are provided between 0 and 0, respectively. In this embodiment, the network interface includes a physical layer device 300, a MAC 140, and a DMA controller 141.

  Then, the software (CPU 400) sets a buffer for storing received packets on the memory 500 connected to the memory controller 170 of the ASIC 100. Although there is an upper limit on the size of the buffer, there is an upper limit not only on the total memory size of the buffer but also on the number of packets that can be stored.

  A packet received by the MAC from the physical layer device 300 is transferred to the memory 500 by the DMA controller 141. The MAC 140 unit includes a register A for recording the total number of packets transferred to the memory 500, a register B for writing the number of packets processed by the software every predetermined time, and a register C for accumulating the values written in the register B. There is. Register C indicates the total number of packets that the software has processed so far.

  FIG. 2 is a diagram for explaining the operation of the present embodiment. In the figure, the total number of received packets is indicated by SP, the total number of packets processed by software is indicated by DP, and the number of packets in the reception packet buffer set on the memory 500 is indicated by BP. As can be seen from this figure, the network interface performs flow control when the total number of received packets DP increases, the software process cannot catch up, and the number of packets in the received packet buffer exceeds a certain level (point A in the figure). Run automatically. Then, when the software processing catches up with the total number of received packets SP, the number of packets BP in the received packet buffer becomes smaller than a predetermined value, and the free area of the received packet buffer becomes larger than a certain level (point B in the figure). Automatic flow control for resuming reception.

FIG. 3 is a flowchart showing a control procedure of the flow control at this time.
The register A provided in the MAC 140 is not constant but increases with time. The register C is also increased at regular intervals. The network interface monitors the difference X between the values of the registers A and C (step S1), and when the processing of the CPU 400 cannot keep up with the reception speed, the value of X = register A−register C increases. When this value X exceeds the number TH of received packet buffers (TH is the upper limit value of packet data in the buffer for preventing overflow), the received packet buffer prepared in the memory overflows, so that the values X and TH When the value X exceeds TH (step S2-Yes), flow control for preventing overflow is executed (step S3), and the inflow of received packets is suppressed. Since the software continues processing, the value X of (register A-register C) becomes smaller in this state. Then, when a sufficient free space can be secured in the reception packet buffer, that is, when X <TL (TL is the upper limit value of the number of packets in the buffer that can be permitted to resume reception) (step S4-Yes). The hardware automatically performs flow control and permits the inflow of received packets (step S5). The CPU 400 prepares and manages the reception buffer in units of packets.

  Note that the values of the registers A, B, and C may be the number of bytes instead of the number of packets. At that time, the CPU 400 prepares reception buffers in a batch and manages them in packet units.

FIG. 4 is a diagram showing an example of the system configuration of the network system according to the embodiment of the present invention.
In this system, two PCs, an MFP, and a printer are connected to Ethernet (registered trademark) via a cable, and one node PC and a printer are connected via a wireless LAN. The ASIC 100 is mounted on an MFP and a printer, and is configured to efficiently receive and output data from a PC.

  The MFP is called a multi function peripheral, and is an image forming apparatus having a function of printing digital data as a visible image on a recording sheet, and has a plurality of functions such as a copy function, a printer function, and a facsimile function. Among these, in the printer function, since the image data sent from the PC is subjected to image processing by the printer driver, the transferred image data is output as it is.

  On the other hand, the copy function needs to convert RGB image data obtained by reading a document into YMCK image data for printing, and thus known image processing such as γ correction and MTF processing is performed. In the facsimile function, image processing such as printer γ correction and dither processing is performed when the transmitted image data is printed out.

  Therefore, when processing the image transferred from the scanner, the ASIC 100 is provided in the image processing apparatus. An image forming apparatus having a copy function includes a scanner and thus includes an image processing apparatus.

<Second Embodiment>
FIG. 5 is a diagram illustrating a second embodiment of the configuration of the ASIC when the network interface 600 is connected to the expansion PCI bus 700. Note that the same reference numerals are given to the same components as those in the first embodiment, and redundant descriptions are omitted as appropriate.

  In the figure, the software sets a buffer for storing received packets on the memory 500 connected to the memory controller 170 of the ASIC 1 (100). Although there is an upper limit on the size of the buffer, there is an upper limit not only on the total memory size of the buffer but also on the number of packets that can be stored.

  A packet received by the MAC 111-1 incorporated in the ASIC 2 (111) is transferred to the memory 500 by the DMA controller 111-2 via the PCI bus 700, the PCI interface 110-2, and the DMA computer 110-1. In the MAC 111-1 unit, a register A that records the total number of packets transferred to the memory 500, a register B that writes the number of packets processed by the software every predetermined time, and a value written in the register B are accumulated. There is a register C. Other parts that are not particularly described are configured in the same manner as in the first embodiment and function in the same manner.

  As described above, according to the first and second embodiments, the MAC units 140 and 111-1 generate and transmit the flow control packet, temporarily stop the communication operation, and prevent the reception buffer from overflowing. Can do.

  With flow control, even a CPU with low processing capability can prevent lost packets and prevent unnecessary packet retransmission time.

  When the CPU 400 performs packet processing and a margin is generated in the reception buffer, the MAC units 140 and 111-1 resume communication using the flow control packet again. Thereby, it is possible to prevent the communication stop state from continuing more than necessary.

  The overflow of the reception buffer prepared on the memory 500 can be prevented without worrying about the processing capacity of the CPU 400, and unnecessary packet retransmission processing can be prevented.

  Furthermore, even low-priced printers and MFPs that do not readily employ high-performance CPUs and large-capacity memories can be connected to a high-speed network environment with peace of mind.

It is a block diagram which shows an example of a structure of ASIC as a hardware structure concerning the 1st Embodiment of this invention. It is a figure for demonstrating the operation | movement of 1st Embodiment. It is a flowchart which shows the control procedure of the flow control of 1st Embodiment. It is a figure which shows an example of the system configuration | structure of the network system which concerns on 1st Embodiment. It is a block diagram which shows an example of a structure of ASIC as a hardware structure which concerns on 2nd Embodiment.

Explanation of symbols

100 ASIC, ASIC1
110 Memory Arbiter 111 ASIC2
111-1,140 MAC
111-2, 141 DMA controller 300 Physical layer device 400 CPU
500 memory 600 network interface

Claims (7)

A network interface unit including a MAC, an interface unit with a CPU that prepares and manages a reception buffer in packet units, and a memory controller unit connected to a memory,
The network interface unit has a register for recording the number of received packet buffers prepared by the software on the memory, the actual number of received packets, and the number of received packets processed by the software. Subtract the number of processed packets, and when the value exceeds the preset upper limit of the total number of receive buffers prepared in the memory, the flow control is automatically performed and the receive buffer overflows. A network control device characterized by preventing. A network interface unit including a MAC, an interface unit with a CPU that collectively prepares reception buffers and manages them in packet units, and a memory controller unit connected to a memory,
The network interface unit has a register for recording the number of received packet buffers prepared by the software in the memory, the actual number of received packets, and the number of received packets processed by the software. If the number of bytes processed by the software is subtracted from the number of bytes, and the value exceeds the preset upper limit of the total number of bytes in the receive buffer prepared in the memory, flow control is automatically performed and received. A network control device for preventing a buffer from overflowing.   3. The network control apparatus according to claim 1, wherein the network interface unit includes a physical layer device and a DMA controller in addition to the MAC.   4. The network control device according to claim 1, wherein the MAC, the DMA controller, the interface unit, and the memory controller unit of the network interface unit are configured by an ASIC. 5.   5. The network control device according to claim 4, wherein the ASIC includes a memory arbiter between a memory and / or a mass storage device which are connected common resources. ,   6. The network control device according to claim 1, comprising a plurality of application functions, wherein each application function uses at least a memory as a shared resource and operates according to an operation command from a client computer. An image processing apparatus. An image forming apparatus comprising the image processing apparatus according to claim 6.

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