JP4671357B2 - Image transfer method, apparatus, and image forming apparatus - Google Patents

Description

  The present invention relates to an image transfer and image forming apparatus using a general-purpose bus such as a PCI bus adopted in many computers.

JP 2003-229985, Japanese Patent Application Laid-Open No. 2002-278917.

  For example, in a multi-function apparatus that generates a plurality of print jobs such as simultaneous duplex printing and single-page printing of a plurality of originals, each application (application program; application processing program) such as a copy application, a printer application, and a FAX application has been conventionally used as an image scanner. Image read / write requests are made directly to engines such as printers and image data processing circuits. For this reason, each application considers multiple print jobs such as double-sided printing within each application, and replaces the requests so that the productivity within each application is high. It was supposed to be executed, and it was supposed to reduce productivity.

  In order to solve this problem, Patent Document 1 provides an image processing apparatus and a print control method that can obtain high productivity in a multi-function machine in which a plurality of print jobs are generated. However, when the controller and engine transfer data via the PCI bus, which is a general-purpose bus, which is adopted as the standard for expansion buses in many computers, the amount of data planned by the controller is not transferred Until the notification from the engine comes, the controller will be in a waiting state, which may reduce productivity, but this is not a solution.

  According to the image data transfer system described in Patent Document 2, an image data storage block and an image processing block are connected by a PCI bus, and after the image processing block inputs one line of data from the image data storage block, Since the PCI access indicating the end of the line data transfer is performed each time for the image data storage block, the image data storage block side grasps the progress of the image processing block by the PCI access indicating the end of the line data transfer. can do. As a result, even if the image processing block cannot communicate an abnormal state to the image data storage block for some reason, the image data storage block can promptly wait for an abnormality notification from the image processing block or a transfer end notification. Then, the next process can be started.

  However, this technique is based on the premise that PCI access indicating the end of line data transfer is executed every time line data transfer ends. For this reason, it cannot be applied to a block that does not have such a promise unless the specification is changed. In addition, since the PCI bus is used for PCI access indicating the end of line data transfer, there is a possibility that the PCI bus bandwidth cannot be satisfied when there is not enough space in the PCI bus.

  In a digital copying machine in which a controller and an engine part are configured via a PCI bus, the controller becomes a PCI bus target via the PCI bus in response to a data transfer request from a plotter on the engine side. When the image data in the memory is transferred to the plotter and the image is output to the plotter, the number of transfer lines assumed by the controller may not match the number of lines on which the engine side actually performs read access. For example, there are cases where accurate line information cannot be delivered to the controller in advance due to mixed size or undefined size. In this case, the number of lines of larger size is set on the controller side, so the engine side However, since the transfer for the number of lines set is not performed on the controller side even though the transfer has been completed, it is considered that the transfer is still in progress, and a waiting state occurs in the controller. Finally, an end notification is received from the engine side and the end is recognized. In this case, since a waiting state occurs, productivity is lowered, and a method for improving productivity has been desired.

  An object of the present invention is to eliminate the waiting state.

(1) The transfer source (8) generates an image transfer start signal to the transfer destination and transfers the image data from the specific address area of the transfer source to the transfer destination (13) via the general-purpose bus (9). In the image transfer method,
After the transfer of image data from the transfer source (8) to the transfer destination (13) is started, the image data transfer on the general-purpose bus is performed during a period in which the general-purpose bus has no access (VideoOut) to the specific address area. thereby initializing the count when there is the access counts clock, the start signal is cleared in response to the end signal to generate a termination signal when the count matches the first set value that is set And determining whether to end the transfer of the image data in the specific address area .

  In addition, in order to facilitate understanding, in parentheses, the correspondence of the examples shown in the drawings and described later, or the symbols or corresponding matters of corresponding elements are added for reference. The same applies to the following.

  Transfer completion can be quickly recognized based on the end signal without waiting for transfer completion notification from the transfer destination (13). For this reason, high productivity of image processing can be obtained.

  (2) The image transfer method according to (1), wherein the first set value is a value set in the register. Since an arbitrary value can be set in the register by software, an image transfer speed can be set from the low speed specification to the high speed specification so that the transfer speed can be set to the shortest without erroneous detection according to the specification.

(3) The number of transfer lines related to the transfer is counted based on the set second set value in accordance with the generation of the activation signal, and the count for the second set value is counted after the transfer is performed . The image transfer method according to the above (1) or (2), wherein the end determination is started when the determination is finished .

  According to this, high output of image processing is achieved even for the configuration of the transfer destination (13) that reads a plurality of lines at a time and then performs a new transfer whenever the memory for one line becomes available. It is possible to maintain sex.

  (4) The image transfer method according to (3), wherein the second set value is a value set in the register. According to this, it is possible to flexibly cope with various characteristics of the transfer destination (13), such as only the first two lines come to read access continuously, and only the first four lines come to read access continuously. Become.

(5) There are a plurality of specific address areas, and after starting transfer of image data from the transfer source (8) to the transfer destination (13) in each specific address area, The image transfer method according to any one of (1) to (4), wherein the end determination is performed . According to this, suitability for color image transfer and double-sided image transfer for transferring different color information or monochrome images for each region is enhanced.

  (6) After the end signal is generated, the count start condition is set to start transfer of image data from the transfer source (8) to the transfer destination (13) in an address area different from the specific address area. The image transfer method according to any one of (1) to (5) above. According to this, control of image transfer can be appropriately performed by software processing without illegally generating a plurality of end signals (interrupt factors) for image transfer of the same specific address area.

(7) The image transfer method according to any one of (1) to (6), wherein the transfer of the image data in the specific address area is ended by an interrupt process in response to the end signal. According to this, it can be recognized that it is not necessary to continuously enable the image transfer start signal (H), so it can be disabled (L) and quickly prepared for the next image transfer.

  (8) The image transfer method according to any one of (1) to (7), wherein the general-purpose bus (9) is a PCI bus.

(9) an image transferring image data via a general purpose bus (9) to the destination (13) from a specific address area of the transfer destination generates the image transfer start signal (VEN) relative to the transfer source (8) In the transfer device,
First counting means for counting clocks on the general-purpose bus (9);
After the image transfer start signal (VEN) is generated, when there is no access to the specific address area on the general-purpose bus (9), the first counting means can be counted, and if there is an access, the first counting means Count control means (303) for initializing the count;
Terminate the transfer of the image data of the particular address region by clearing the activation signal in response to said end signal to generate a termination signal when the count matches the first set value is first counting means is set An end determination means for performing an end determination (303 comparator); and
A termination control means (2) for clearing the activation signal in response to the termination signal and terminating the transfer of the image data in the specific address area;
An image transfer apparatus comprising:

  (10) The image transfer apparatus according to (9), wherein the count control unit (303) includes a register to which a first set value is written.

(11) The count control means (303) counts the number of transfer lines related to the transfer on the basis of the set second setting value in accordance with the generation of the activation signal , and determines the end determination means (comparison of 303). vessel), the transfer is said count control means since been conducted to initiate the termination determination when the count of said set value content, image transfer apparatus according to (9) or (10).

  (12) The image transfer apparatus according to (11), wherein the count control unit (303) includes a register in which a second set value is written.

  (13) The unit according to any one of (9) to (12), wherein the first counting unit, the count control unit (303), and the end determination unit (comparator of 303) include a plurality of assemblies. Image transfer device.

(14) the end control means (2) is an interrupt process responsive to the end signal, it terminates the image transfer of the specific address region, according to any one of (9) to (13) Image transfer device.

  (15) The image transfer device according to any one of (9) to (14), wherein the general-purpose bus is a PCI bus.

  (16) An image forming apparatus including the image transfer apparatus according to any one of (9) to (15), wherein the transfer destination (13) is a plotter that forms an image represented by image data on a sheet.

  FIG. 1 shows a digital copying machine according to an embodiment of the present invention. Reference numeral 1 denotes a controller. Reference numeral 2 denotes a CPU, which executes processing while using the RAM 4 in accordance with a program stored in the ROM 3. The ASIC (Application Specific IC) 6 performs this control, and also controls the HDD 7 and image processing RAM (semiconductor memory module) 8, the interface of the network 5, and the PCI bus 9. The controller 1 is connected to the engine 11 via the PCI bus 9. In this embodiment, the engine 11 includes a scanner 12 that reads a document image and outputs image data, and a plotter (printer) 13 that forms an image represented by the image data on a sheet.

  An operation board 14 is connected to the controller 1, and the user can input settings and execution (start) of copying and facsimile communication by operating keys on the operation board 14. A network (LAN) is connected to the controller 1, and printing can be instructed to the controller 1 from a personal computer PC connected to the network. When the copy instruction is given and the number of copies is one monochrome, the image data obtained by the scanner 12 reading the document is transferred to the plotter 13. However, at the time of copying or printing a plurality of sheets or color copying or printing, the image data is written in the RAM 8, read out from the RAM 8, and transferred to the plotter 13.

  The PCI bus 9 can be connected to the engine 11 and can interface with the option 10. The option 10 is for function expansion. For example, by connecting an IEEE 1394 option controller, it is possible to provide a hardware environment for connecting to other devices via the IEEE 1394.

  FIG. 2 shows a partial configuration of the inside of the ASIC 6. It should be noted that the components of the text data processing system for converting the print document data from the personal computer PC into the image data and writing it to the RAM 8 in the controller 1 and the ASIC, the interface with the operation board 14, the components of the facsimile communication, etc. Omitted.

  The ASIC 6 is a CPU interface CPU I / F 201, a memory controller MEMC 202, a hard disk controller HDDC 203, a PCI controller PCIC 204, a network controller NETC 205, a video controller VIDEOOC 206 for controlling scanner data and plotter data, and a DMA controller. It has a DMAC1 207, a DMAC2 208, and a DMAC3 209, and an arbiter ARB 210 for arbitrating memory access. Note that the image transfer start signal is generated by the video controller VIDEO OC 206 and also supplied to the PCI controller PCIC 204.

  Reference numeral 211 denotes an internal register controller IREQ, which controls writing and reading of a control register built in the ASIC in accordance with a command from the CPU 2. An interrupt controller INTC 212 receives each interrupt factor in the ASIC, performs interrupt factor holding, mask processing, etc., and performs processing for notifying the CPU 2 of an interrupt.

  FIG. 3 shows an internal configuration of the PCI controller PCIC 204. In FIG. 3, reference numeral 301 denotes a bus interface BUS IF that directly controls data exchange with the PCI bus 9. A control register CONT REG 302 controls the entire PCI controller 204. The control register CONT REG 302 is subjected to read / write access control from the CPU 2 via the internal bus 306 via the internal register controller IREQ 211, and performs setting of various registers in the ASIC 6, status reading, and the like. 303 is a first timing means including a decoder 1, a count control register 1, a counter 1, a comparator 1 and a control register 1, and 304 is similarly a decoder 2, a count control register 2, a counter 2, a comparator 2 and Second timing means including a control register 2.

The function of each element of the first timing means 303 is as follows, and the function of each element of the second timing means 304 is the same:
Decoder 1: Monitors the address accessed and executed by the ASIC 6 via the PCI bus 9 to determine whether it is a target area (a specific address area for image transfer);
Count control register 1: a second set value indicating from which line the interrupt target (transfer end determination target) is set, and a period during which access (VideoOut) to the target area is interrupted on the PCI bus 9 (PCI Each register for setting a first setting value with software as a threshold for determining whether or not the number of clocks on the bus is regarded as the end of transfer of the target area.

  Counter 1: There are two counters: a line counter indicating a transfer line and a clock counter for counting the number of clocks.

  The line counter starts counting with the image transfer start signal, and the number of lines of data transferred from the set main scanning data amount (data amount transferred in one line) and the actually transferred data amount Count the number of transfer lines. The count control register 1 has a register for writing a second set value for the line counter. The second set value of the register is preset in the line counter when an image transfer start signal (H level) is generated. The counter counts down the number of transfer lines of the image data from the preset value, and when the number of transfer lines corresponding to the preset value is counted, a counter over signal is generated and the clock counter can be counted. Therefore, the second set value determines the count start timing of the clock counter. The clock counter does not operate from when the image transfer start signal (H level) is generated until the line counter finishes counting the number of transfer lines corresponding to the second set value (period t1 in FIG. 4).

  The clock counter counts the number of set lines and generates a count over signal. After that, if there is no access (VideoOut) to a specific address area for image transfer on the PCI bus 9, that is, an image is displayed on the PCI bus 9. When there is no transfer, counting of the clock (transfer synchronization pulse) of the PCI bus 9 is started, and whenever an access (VideoOut) to a specific address area for image transfer occurs on the PCI bus 9, that is, on the PCI bus 9. Every time there is an image transfer, the count value is initialized (cleared). When there is no image transfer on the PCI bus 9, the count is started again, and this is performed while the image transfer start signal is asserted, that is, the image. Repeat while maintaining the transfer designation level (H).

  Comparator 1: The first set value, which is the clock number set value of the register of the count control register 1, is compared with the count value of the clock counter. When the count value reaches the clock number set value (first set value), the count is over. A signal (end signal) is generated. This signal means the occurrence of an interrupt factor.

  Control register 1: When an interrupt factor (count over signal indicating completion of counting of clocks corresponding to the first set value: end signal) is generated from the comparator 1, the counter 1 and the counter 1 are activated until the next image transfer start signal becomes valid. The entire first timing unit 303 is controlled, for example, the state of the comparator 1 is initialized.

  The second setting value preset in the line counter determines the timing at which the end determination operation for determining whether or not an interrupt factor is generated by the clock counter and the comparator 1 (transfer end) can be started. The determination operation can be started as soon as an image transfer start signal is generated, but the determination operation is repeated for a long time. A minimum size can be substantially determined for a specific area to be transferred, and it is not necessary to perform the determination operation substantially during a period during which image transfer for the minimum size is being performed. Rather, in order to reduce the possibility of erroneous determination (error occurrence of interrupt factor) due to malfunction of the clock counter and / or the comparator 1 due to some trouble such as noise during the determination operation, image transfer for the minimum size is performed. It is preferable not to execute the determination operation during the period during From this point of view, in this embodiment, the line counter and the second set value are used to preset the second set value in the line counter via the register in the CONT REG 302, and the second set value corresponding to the minimum size is set. The above-described determination operation is started after the image transfer of minutes is completed. Since the second set value is written to the register in the CONT REG 302 by software, the second set value can be adjusted and changed.

  The first set value is a threshold value for determining whether image transfer has been completed on the PCI bus 9. In the case of image transfer of a specific area, there is an upper limit for the transfer interval of image data blocks being transferred on the PCI bus 9 depending on the hardware and software settings, and image transfer appears for a period exceeding the upper limit. Otherwise, it can be considered that the image transfer of the specific area is completed. The threshold value for the end determination is the first set value, which is written into the register in the CONT REG 302 by software. The first set value is also adjustable and can be changed.

  Reference numeral 307 denotes a transmission line for the main scanning data amount and image transfer start signal from the video controller VIDEOOC 206 to the PCI bus controller PCIC 204. Reference numeral 308 denotes an address / write data bus for target access from the PCI bus 9 to the ASIC 6. Reference numeral 309 denotes a data bus for transferring read data when target access is made from the PCI bus 9 to the ASIC 6. When transferring the image data of the RAM 8 to the plotter 13, when transferring the image data from the RAM 8 to the plotter 13 via the ASIC 6, the image data read from the RAM 8 flows to the BUS IF 301 via the data bus 309, and The data is transferred from the BUS IF 301 to the plotter 13 via the PCI bus 9. Transfer of the image data from the RAM 8 to the plotter 13 is sequentially performed in small area sections so as to cut out one part on the one-page image. This small area section is expressed as “specific access area”.

  Reference numeral 310 denotes a line for outputting an interrupt request signal 1 which is a pulse of 1 clock width for notifying the interrupt controller INTC 212 when the first timing means 303 generates an interrupt factor (end signal). Similarly, reference numeral 311 denotes a line for outputting an interrupt request signal 2 which is a pulse of one clock width for notifying the interrupt controller INTC 212 when the second timing means 304 generates an interrupt factor.

  FIG. 4 shows the counting operation of the first timing means 303 and the generation of an interrupt factor (end signal generation) when it is assumed that image data corresponding to the first 16 lines of one page image in the RAM 8 has been transferred from the RAM 8 to the plotter 13. ). VEN is an “image transfer start signal” generated by the video controller VIDEO OC 206, and this signal is enabled at the first clock of image transfer, and image transfer is performed on the PCI bus 9. Here, the preset value of the line counter is set so as not to cause an interrupt factor for 16 lines (second set value), so the count data of the line counter in the counter 1 indicates 0-15. During a period t1 until the count value 16 is reached, the clock counter in the counter 1 does not operate. When the period t1 has passed, the image transfer of 16 lines up to the PCI controller PCIC 204 (the bus interface BUS IF 301) of the ASIC 6 is completed, and the count value of the line counter becomes 16 (= second set value). The clock counter starts counting the clock on the PCI bus 9 during a period when there is no image transfer (VideoOut) on the PCI bus 9. Since the image transfer (VideoOut) on the PCI bus 9 is detected at the end of the period t2, the clock counter is cleared, and when the image transfer is completed, the count for each clock is restarted (period t3). However, since the image transfer (VideoOut) on the PCI bus 9 is detected again, the clock counter is cleared, and when the image transfer is stopped, the count for each clock is resumed (period t4).

  Thereafter, at the end of the period t4, the clock counter has reached 6, so that it matches the preset value 6 (first set value), the comparator 1 generates a count over signal (end signal), and the interrupt signal Is asserted High (H) for one clock. That is, an interrupt signal is generated. This interrupt signal (signal asserted for one clock) is held by the interrupt controller INTC 212. The interrupt controller INTC 212 causes the CPU 2 to generate an interrupt if the interrupt signal is not masked (interrupt prohibited). That is, an interrupt signal is given to the CPU 2.

  When the CPU 2 receives the interrupt signal, the duration (VIDEO OC 206) of the image transfer start signal (VEN = H level) scheduled (set) by the video controller VIDEO OC 206 (based on the instruction from the CPU 2) (VIDEO OC 206 receives the image transfer start signal). It is recognized that the image transfer is completed in a shorter time (early timing) than the timing for switching to the unintentional L level, that is, the image transfer is performed with a size shorter than the set scheduled size. Since the video controller VIDEO OC 206) does not automatically clear (erase) the image transfer start signal at the set timing, the CPU 2 recognizes that it must be cleared by software, and the CPU 2 recognizes the video controller VIDEO OC 206). Instruct the image transfer start signal To clear the EN (H). Then, the pending bit of the interrupt controller INTC 212 for this interrupt signal, that is, a signal indicating the necessity of interrupt is cleared. With this processing, the image transfer start signal can be quickly cleared without receiving a transfer completion notification from the plotter 13 of the engine 11.

  The transfer amount of the image data to the PCI controller PCIC 204 (the bus interface BUS IF 301) of the ASIC 6 is set on the condition that the image transfer start signal VEN rises from the insignificant level L to the significant level H. 16 lines), the clock count for counting the clock during the period of no image transfer on the PCI bus is enabled, and when the clock count value reaches the first set value 6, the image transfer start signal is deleted. The above counting is not started until an image transfer start signal is generated again, that is, after detecting a factor for generating and notifying an interrupt, a new interrupt is generated and notified. It seems to be a condition that a new image transfer start signal is received to detect the factor for Since the construction, for the same factor (activation signal for a single image transfer), it does not occur a plurality of times of interrupt factors illegally.

  In addition, first, image data for a plurality of lines is read from the RAM 8 at a time, and then a transfer destination (a transfer destination to which a new transfer is performed every time one line of memory is available in the buffer memory on the transfer destination side for storing the transfer data ( This can also be applied to the configuration of 13). In this case, when transferring image data for a plurality of lines for the first time, the second set value is a value for the plurality of lines, and when transferring for each line, the second set value is a value for one line, or , 0.

  In the above embodiment, the timing of image transfer in each address area can be individually controlled using the first timing means 303 and the second timing means 304. That is, for each of the two specific address areas, after the transfer of the image data from the transfer source, for example, the RAM 8 to the transfer destination, for example, the plotter 13 is started, When there is no transfer access (VideoOut) to the address area, the image data transfer clock on the general-purpose bus 9 is counted. When there is a transfer access, the count is initialized. When the first set value is counted, the count is An image transfer end signal is generated for a specific address area.

  In addition, for example, in a tandem color plotter in which Y, M, C, and Bk color image forming units are arranged in tandem and there is a time difference in the image transfer timing for each color, there are four timing units (303 in total, one for each color). Etc., it is possible to cope with a tandem color plotter engine in which there is a time difference in image transfer timing.

1 is a block diagram showing an outline of the configuration of a digital copying machine equipped with an image transfer apparatus that implements an image transfer method of the present invention. It is a block diagram which shows the component mainly concerned with image data transfer of ASIC6 shown in FIG. FIG. 3 is a block diagram showing an outline of some functional elements of the PCI bus controller PCIC 204 shown in FIG. 2. It is a time chart which shows the generation timing of the input / output signal and internal signal of the 1st timing means 303 shown in FIG.

9: PCI bus 201: CPU interface CPU I / F
202: Memory controller MEMC
203: Hard disk controller HDDC
204: PCI controller PCIC
205: Network controller NETC
206: Video controller VIDEOOC
207: DMA controller DMAC1
208: DMA controller DMAC2
209: DMA controller DMAC3
210: Arbiter ARB
211: Internal register controller IREQ
212: Interrupt controller INTC
301: Bus interface BUS IF
302: Control register CONT REG
303: First timing means 304: Second timing means 306: Internal bus 307 for CPU 2 to control read / write access: Image transfer start signal transmission line 308: Address / write data bus 309: Data bus 310: Interrupt Request signal output line 311: Interrupt request signal output line VEN: Image transfer start signal

Claims (16)

An image transfer method for transferring image data via the universal bus and generates a start signal of the image transfer to the transfer destination to the transfer destination from a specific address area of the transfer source by the source,
After starting the transfer of the image data to the transfer destination from the transfer source, the period access is not for the particular address region in the general purpose bus is counts clock of the image data transfer on the general-purpose bus the access and thereby initializing the count, the set image of the specific address area by clearing the activation signal in response to said end signal to generate a termination signal when the count matches the first set value An image transfer method, comprising: performing an end determination to end data transfer .   The image transfer method according to claim 1, wherein the first set value is a value set in a register. With the generation of the activation signal, the number of transfer lines related to the transfer is counted based on the set second set value, and the end when the count for the second set value is counted after the transfer is performed . The image transfer method according to claim 1, wherein the determination is started .   The image transfer method according to claim 3, wherein the second set value is a value set in a register. The specific address area is plural, and after the start of transfer of image data from the transfer source to the transfer destination of each specific address area, the end determination is performed for each specific address area. Item 5. The image transfer method according to any one of Items 1 to 4.   6. The count start condition according to claim 1, wherein after the end signal is generated, the count start condition is a transfer start of image data from the transfer source to the transfer destination in an address area different from the specific address area. The image transfer method according to any one of the above. The image transfer method according to claim 1, wherein the transfer of the image data in the specific address area is ended by an interrupt process in response to the end signal.   The image transfer method according to claim 1, wherein the general-purpose bus is a PCI bus. In an image transfer apparatus that generates an image transfer start signal to a transfer destination and transfers image data from a specific address area of the transfer source to the transfer destination via a general-purpose bus.
First counting means for counting clocks on the general-purpose bus;
After the image transfer start signal is generated, the first count means can be counted when there is no access to the specific address area on the general-purpose bus, and the count of the first count means is initialized when there is the access. Control means;
The transfer of the image data of the specific address area by clearing the activation signal in response to said end signal to generate a termination signal when the count matches the first set value is first counting means is set An end determination means for determining an end to end ; and
End control means for clearing the activation signal in response to the end signal and ending the transfer of the image data in the specific address area ;
An image transfer apparatus comprising:   The image transfer apparatus according to claim 9, wherein the count control unit includes a register to which a first set value is written. Said count control means, based on said second set value that is set with the generation of the start signal, counting the number of transfer lines according to the transfer, the end determining unit, the count from said transfer is carried out The image transfer apparatus according to claim 9 or 10, wherein the end determination is started when the control unit counts the second set value .   The image transfer apparatus according to claim 11, wherein the count control unit includes a register to which a second set value is written.   The image transfer apparatus according to claim 9, wherein the first count unit, the count control unit, and the end determination unit include a plurality of assemblies. It said termination control means, the interrupt process responsive to the end signal, terminates the image transfer of the specific address region, the image transfer apparatus according to any one of claims 9 to 13.   The image transfer device according to claim 9, wherein the general-purpose bus is a PCI bus.   The image forming apparatus including the image transfer apparatus according to claim 9, wherein the transfer destination is a plotter that forms an image represented by image data on a sheet.

Images