JP2005182156A - Image transferring device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent concentration of access to a bus in the transfer of image data. <P>SOLUTION: An access interval to image data is set, and access to a bus is controlled. Also, a signal being a transfer reference for one line may be the trigger of access to the image data. This image transferring device is provided with a means which decides which of the set access interval and the signal being the transfer reference for one line should be given priority so that it is possible to meticulously manage the access to the bus. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image transfer apparatus and an image transfer method for controlling image data transfer.

As a similar technique, Patent Document 1 has been filed by Ricoh.
This is an image data transfer device that improves transfer efficiency by avoiding bus congestion by intentionally widening the interval between transfers in a range that can be transferred within one line, and avoiding unnecessary access. It is to provide.

  That is, when data is transferred between devices using a bus, in DMA (Direct Memory Access) transfer in which image data is transferred in units of lines, DMA transfer of a predetermined number of data is performed using a 1-line synchronization signal as a trigger. Therefore, data transfer is concentrated after the input of the one-line synchronization signal. This bus is also used by other devices for transfer, and when data transfer is concentrated, if another device requests data transfer, it becomes very congested. In such a state, a state requiring redoing occurs, frequent interruptions occur, and the overhead bus efficiency is wasted. Also, even if transfer requests are issued one after another, if the other party is not ready, it will be waited and useless time will be wasted.

Therefore, Patent Document 1 provides an image data transfer apparatus that avoids bus congestion and intentionally increases the transfer efficiency by intentionally increasing the transfer interval within a range that can be transferred within one line.
JP 2002-278915 A

  In Patent Document 1, for example, image data for a plurality of lines may be read in advance in order to generate image data to be output in synchronization with a one-line synchronization signal. Image data for a plurality of lines is read in the absence of a signal.

  In this case, if the read request is issued one after another, the bus is congested. In addition, this congestion period is also the time to complete transfer for a plurality of lines. The same applies to the case of writing. For example, when image data is received in synchronization with a 1-line synchronization signal and is written via the bus, the image data received in synchronization with the 1-line synchronization signal When the image data generated by the user is added before and writing is performed via the bus, the image data is written without synchronizing with the one-line synchronization signal, thereby causing bus congestion. become.

  On the other hand, the present invention has an object of avoiding congested buses by issuing transfer requests one after another when there is no one-line synchronization signal. That is, it is an object of the present invention to provide means for avoiding concentration of bus access.

  In order to solve the above-described problems, the present invention provides an access for setting an image data access start interval corresponding to one line in an image data transfer apparatus that accesses image data via a PCI (Peripheral Component Interconnect) bus. It has an interval setting means.

  The present invention is further characterized by further comprising means for invalidating the start interval setting means for accessing image data corresponding to one line.

  Further, according to the present invention, transfer is started according to the set value set by the access interval setting means. When input of a signal serving as a transfer reference for one line from the outside is started, the transfer reference for one line is set. It is further characterized by further comprising means for starting access to image data corresponding to one line via the PCI bus with reference to the above signal.

  Further, the present invention is characterized in that, in an image data transfer apparatus that accesses image data via a PCI bus, an access start interval corresponding to one line is set.

  Further, the present invention is characterized in that it is determined whether or not to start access to image data based on an access start interval to image data corresponding to one line.

  Further, the present invention is characterized in that in addition to the access start interval for image data corresponding to one line, a signal serving as a transfer reference for one line is used as a signal for starting access to image data.

  The present invention is characterized in that it determines which of the access start intervals to the image data corresponding to the one line and the signal serving as the transfer reference for the one line is prioritized.

  According to the present invention, the image data transfer apparatus that accesses the image data via the PCI bus has means for setting the start interval for accessing the image data corresponding to one line, so that bus access is concentrated. Can be avoided.

  Also, the present invention is characterized by having means for invalidating the start interval setting means for accessing image data corresponding to one line, so that it is known in advance that other devices do not use the bus. This function can shorten the processing time.

  Further, according to the present invention, there is means for setting an access start interval of image data corresponding to one line, and transfer is started in accordance with this set value, but it becomes a transfer reference for one line from the outside. When the input of the signal is started, access to the image data corresponding to one line via the PCI bus is started using this signal as a reference, so there is no input of a signal serving as a transfer reference for one line. Only the period can be set by means for setting an access start interval of image data corresponding to one line.

FIG. 1 shows an embodiment of the present invention.
In FIG. 1, reference numeral 101 denotes a printer apparatus. The printer apparatus 101 includes a computer 102 that generates data to be printed, a printer controller 103 that generates a print image, an image processing unit 104, an image output unit 105, and an expansion unit C107 and an expansion unit D108 for performing function expansion. .

  The printer controller 103 operates using the RAM 111 in accordance with a program recorded in the ROM 110 by the CPU 109. The control circuit 112 serves as a response to a request from the CPU, a process for generating an image, and an interface with the PCI bus 106.

  The PCI bus 106 is a PCI bus that is generally used in a personal computer or the like. A function expansion unit C107, a function expansion unit D108, and an image processing unit 104 are connected to the PCI bus.

  The image processing unit 104 is connected to the PCI bus 106 via the bus I / F 113 and writes the image data read via the PCI bus 106 to the line buffer A 115 or the line buffer B 116 via the selector 114. Image data for a line is read from the line buffer A 115 or the line buffer B 116 through the selector 117.

  The image processing apparatus 118 has a buffer for a plurality of lines, accumulates image data for a plurality of lines in the buffer, and defines with the image output unit 105 via the video I / F 119 based on the data. The image data is output according to the I / F specification. Since the configuration is as described above, in this embodiment, before outputting image data to the image output unit 105, image data for a plurality of lines is read out via the PCI bus 106.

  The unit B control unit 120 controls the image processing unit 104, and there is an interval setting unit 121 as a register for determining the operation of the control unit, and access of image data corresponding to one line is performed. Set the start interval.

  FIG. 2 shows the structure of the interval setting means 121. As shown in FIG. 2, the interval setting means 121 is composed of a 32-bit register. However, 16 bits are unused. The interval time is written to this register by performing write access from the CPU 109 via the PCI bus 106 and further via the Bus I / F 113.

  The control register 122 not only sets activation for image transfer, but also whether or not to operate according to the value set in the interval setting means 121, and input of a signal serving as a transfer reference for one line from the image output unit 105 is started. If this happens, it is also used to set whether to use it as a trigger for starting access from the PCI bus.

  The structure of the control register 122 is as shown in FIG. When 1 is written to VEN, image transfer is started. When the predetermined operation is completed, it is automatically cleared to zero. If 0 is written with VEN = 1, the process is forcibly terminated.

  When CEN is 1, the access start interval is controlled using the value set in the interval setting value register. If 0, the access start interval is not controlled.

  WEXT is valid only when CEN = 1. When CEN = 1, when the falling edge of LGATE_N is detected, the access is started every time the falling edge of LGATE_N is detected instead of the interval setting value. When CEN = 0, access is started with an interval setting value that is irrelevant to the detection of the falling edge of LGATE_N.

  Next, the relationship between the I / F signal to and from the image output unit 105 and the transfer via the PCI bus 106 will be described with reference to FIG. First, each signal in FIG. 4 will be described. VEN is a signal indicating the start of image transfer, and the CPU 109 sets 1 to VEN of the control register 122. FGATE_N is a negative logic frame gate signal, LGATE_N is a negative logic line gate signal, VD is image data, PCI is a signal on the PCI bus, Count is a counter in the UnitB control unit 120, and if High, one line Indicates the start of transfer from the PCI bus.

The operation will be described below.
By setting VEN = 1, the image processing unit 104 reads out image data via the PCI bus 106. Thereafter, every time Count = 1, one line of data is read from the PCI bus. When four lines of data are read from the PCI bus, the PCI bus is counted despite the fact that Count = 1. Reading from is not done. This is because the line buffer including the image processing unit 118 of the image processing unit 104 is full. In this example, when input of a signal serving as a transfer reference for one line from the image output unit 105 is started, it is set to be used as a trigger for starting access from the PCI bus 106. Therefore, after that, Count = 1 remains, and line data reading from the PCI bus 106 is started each time the assertion of LGATE_N is detected.

  The present invention can be applied to an image-related device using a PCI bus.

It is a block diagram showing the structure of this invention. 3 is a diagram illustrating a structure of an interval setting unit 121. FIG. 3 is a diagram illustrating a structure of a control register 122. FIG. It is a time chart showing operation | movement of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Printer apparatus 103 Printer controller 104 Image processing part 105 Image output part 106 PCI bus 120 UnitB control part 121 Space | interval setting means 122 Control register

Claims (7)

  An image data transfer apparatus for accessing image data via a PCI (Peripheral Component Interconnect) bus, comprising an access interval setting means for setting an access start interval of image data corresponding to one line apparatus.   2. The image transfer apparatus according to claim 1, further comprising means for invalidating an access start interval setting means for image data corresponding to one line.   Transfer is started according to the set value set by the access interval setting. When the input of a signal serving as a transfer reference for one line is started from the outside, the signal serving as the transfer reference for one line is used as a reference. 2. The image transfer apparatus according to claim 1, further comprising means for starting access to image data corresponding to one line via the PCI bus.   An image transfer method for accessing image data via a PCI bus, wherein an interval for starting access to image data corresponding to one line is set.   5. The image transfer method according to claim 4, wherein whether to start the access to the image data is determined based on an access start interval to the image data corresponding to the one line.   5. The signal according to claim 4, wherein, in addition to an access start interval for image data corresponding to one line, a signal serving as a transfer reference for one line is used as a signal for starting access to image data. Image transfer method.   7. The image transfer method according to claim 6, wherein a priority is given to an access start interval to image data corresponding to the one line or a signal serving as a transfer reference for the one line. .

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