JP2007299304A - Data transfer control method and device, and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce delay of data transfer when an communication error occurs. <P>SOLUTION: When transferring all data of an amount transferable in a required time X within an allocated time Y, image data of one plane is divided and the data is transferred to a band equal to or below a data amount transferable within a timing margin determined from X, Y and overhead time Z required for communication restarting during a communication error, and when a communication error occurs, a band being transferred during the communication error or the preceding band is started to be transferred. When a communication error occurrence allowable set value is defined as N, the data is divided into bands equal to or below a data amount transferable within a timing margin A/N to be transferred. The image data of one plane is divided by the image data amount in which a code data amount is equal to or below a data amount transferable within a timing margin A and is subjected to compressive coding for each band and transferred to an HDD. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to data transfer control, and more particularly to a data transfer control method, apparatus, and image forming apparatus for transferring serial communication data to a memory by DMA (Direct Memory Access) such as SATA (Serial AT Attachment). The present invention can be used for, for example, a copying machine, a printer, a PC (Personal Computer), a hard disk recorder, and other devices using SATA.

JP 2000-298640 A.

  Cited Document 1 describes a basic configuration and operation of a direct memory access controller (DMAC). A method of transferring image data divided into a plurality of bands while being chained by DMAC is well known from Patent Document 1 and other patent documents. Further, Patent Document 1 describes a method of generating a continuation interrupt when transfer for each band is completed and starting transfer of the next band.

  By the way, the serial data communication can increase the transmission speed as compared with the parallel data communication, but a communication error in the transmission path is likely to occur. Therefore, retransmission control when an error occurs is essential. In particular, in serial ATA (Serial AT Attachment: SATA), when a communication error occurs, it is necessary to reissue a command instead of retransmitting only data, so that retransmission control is generally performed through software.

FIG. 15 shows a conventional image data transfer path during printing in the multi-function color copying system shown in FIG. Here, “code” is compressed data obtained by compression-coding image data. Data transfer when printing data sent from the personal computer PC as the host is printed out by the printer 14 is as follows:
1. Network I / F 109, ASIC (Application Specific IC) 102 and CPU 101 store print data (PDL: Page Description Language) input by the host PC in memory 105;
2. The CPU 101 converts the print data into image pixel data (image data) using the ASIC 102 (image conversion) and writes the image data in the memory 105;
3. The DMAC in the controller ASIC 102 compresses (encodes) the image data in the memory 105 and stores it in the HDD 111. In the case of a color image, each plane (each color) is stored in the HDD;
4). The compressed data (code) stored in the HDD is transferred to the memory 105 without change by the DMAC in the ASIC 102. The transfer is done sequentially for each plane;
5a. After all the planes are transferred to the memory 105, they are output to the printer 14 while being decompressed (decoded compressed data into image data) by the DMAC in the ASIC 102. In the case of a low-speed aircraft, there is no problem in safety because the above procedure is followed. However, in order to increase the productivity of the equipment, that is, the image processing speed (pages / minute) in the high speed machine,
5b. When each plane is transferred to the memory 105, there is a case where control is performed for each plane to decompress the code into image data by DMAC and output it to the printer. By performing this control, it is possible to reduce the sheet interval (paper conveyance pitch) in the case of first copy and multi-page. On the other hand, there is a possibility that the output image becomes abnormal due to retransmission when a serial communication error of the HDD 111 occurs. FIG. 16 shows the operation. Refer to FIG.

-Normal (when no serial communication error occurs): (a) in FIG.
1. When there is a print request, the data of each plane is transferred from the HDD 111 to the memory 105 using the DMAC in the ASIC 102;
2. Each time the transfer of each plane is completed, video output (VOUT and output to the printer 14 while expanding the code into image data) is started. In FIG. 16A, C color (cyan), M color (magenta), Y color (yellow), and K color (black) are sequentially transferred to the memory, and immediately after the transfer to the memory is completed, the video of the plane is displayed. Starting output.

-Abnormal (when a serial communication error occurs): (b) of FIG.
1. When there is a print request, the data of each plane is transferred from the HDD 111 to the memory 105 using the DMAC in the ASIC 102;
2. C color as described above. Trigger C-color video output when transfer is complete;
3. As an example, if a serial communication error of the HDD 111 occurs during M color transfer;
4). Interrupt the transfer of M color and retransmit (re-transfer) from the beginning of M color;
5). The printer 14 starts taking out the C color data and starting printing, but the M color data does not come, so an abnormal image is obtained. Depending on the system, printing will be canceled due to an error.

The explanation so far assumes the following:
-The printer 14 does not have enough memory to store the image of each plane;
DMA transfer from the HDD 111 to the memory 105 is in units of one plane. This is because a communication error is not assumed in the HDD 111 using the conventional parallel ATA.

  In conventional data transfer control by SATA of a copier or printer, when data transfer between SATA and memory is performed by DMA, image data for one page is handled as one continuous code. In this case, it takes two pages to transfer one page, and the productivity of the device is lowered. Further, for example, in the case of a color image, as shown in FIG. 15, it is necessary to transfer data of 4 planes (4 colors) per page within a predetermined time. In order to increase the productivity of the device, when control is performed to start outputting the image to the printer in advance without waiting for the transfer of the data for 4 planes to the memory, the memory of the subsequent plane is generated due to retransmission. If the transfer is delayed, the transfer to the printer is not completed within a predetermined time, and an abnormal image is caused. Therefore, there is a need for a system that can be expected safely and with high productivity even if retransmission occurs.

  An object of the present invention is to reduce a delay in data transfer when a communication error occurs.

(1) When all the data that can be transferred in the required time (X) within the allocated time (Y) is transferred by the DMAC,
Transfer data by dividing it into bands that are less than or equal to the amount of data that can be transferred within the timing margin (A) determined from the allocated time (Y), required time (X), and overhead time (z) required for communication restart in case of communication error Then, when a communication error occurs, the data transfer control method is characterized in that the transfer is resumed from the band being transferred at that time or the band immediately before the band.

  In addition, in order to make an understanding easy, the code | symbol of the corresponding element or the corresponding matter of the Example which is shown in drawing and mentions later in a parenthesis was added as an example for reference. The same applies to the following.

  By dividing the band, retransmission is performed for each band, and transfer is started when a communication error occurs or starts from the band immediately before the transmission error, so that time loss during retransmission is reduced.

  (2) If the allowable setting value for the number of occurrences of communication errors in all data transfer is N, the data is transferred in a band less than the amount of data that can be transferred within the timing margin (A) / N. The data transfer control method according to (1), wherein when it occurs, the transfer is restarted from the band that is being transferred at that time or the band immediately before that.

  Even when any of the divided data is retransmitted N times, the total transfer time is Y or less, so that productivity / real-time performance can be maintained.

  (3) The data transfer control method according to (1) or (2), wherein the all data is one plane image data, and the transfer by the DMAC is communication using serial ATA.

(4) When transferring all the encoded data of the amount that can be transferred in the required time (X) within the allocated time (Y) by compressing and encoding the image data of one plane by DMAC,
An image in which the amount of code data is less than or equal to the amount of data that can be transferred within the timing margin (A) determined from the allocation time (Y), the required time (X), and the overhead time (z) required for restarting communication in the event of a communication error By the amount of data, one plane of image data is divided into bands, compressed and encoded into code data for each band, the code data band generated thereby is transferred, and when a communication error occurs, the band of the code data being transferred at that time Alternatively, the data transfer control method is characterized in that the transfer is resumed from the band immediately before.

  (5) If the allowable setting value of the number of occurrences of communication errors in all code data transfer is N, the image data amount of one plane is less than the data amount that can be transferred within the timing margin (A) / N. The data is compressed and encoded into code data for each band, and the generated code data band is transferred. When a communication error occurs, transfer is resumed from the code data band being transferred at that time or the band immediately preceding it. The data transfer control method according to (4) above.

  (6) The data transfer control method according to (4) or (5), wherein the transfer by the DMAC is communication using serial ATA.

  (7) The data transfer control method according to any one of (1) to (6), wherein the data transfer destination or transfer source is an HDD.

  (8) The data transfer control method according to any one of (1) to (7), wherein the band from which retransmission is started is a band immediately before a band in which a communication error is detected. According to this, the DMAC that reads the HDD has started to read the next descriptor, but the DMAC that writes the memory is safe even if the memory is congested and the previous band is still being transferred. You can resend.

(9) Less than the amount of data that can be transferred within the timing margin (A) determined from the allocated time (Y), required time (X), and overhead time (z) required for restarting communication in the event of a communication error Management information generating means (101) for configuring a descriptor chain on the memory for delimiting the transfer target data group in
A DMAC that transfers a transfer target data group for each of the band sections based on the descriptor chain, and resumes transfer from the band that is being transferred at that time or the band immediately before it when a communication error occurs during the transfer;
A data transfer control device comprising:

  (10) The management information generating means (101) is less than or equal to the amount of data that can be transferred within the timing margin (A) / N, where N is the allowable setting value of the number of occurrences of communication errors in the transfer target data group transfer. The data transfer control device according to (9), wherein a descriptor chain for dividing the transfer target data group is configured on a memory in a band.

  (11) The data transfer control device according to (9) or (10), wherein the transfer target data group is image data of one plane, and the DMAC transfers using serial ATA.

(12) The amount of code data is less than the amount of data that can be transferred within the timing margin (A) determined from the allocation time (Y), the required time (X), and the overhead time (z) required for restarting communication when a communication error occurs. Means for dividing one plane of image data into bands and compressing and coding into code data for each band with an image data amount of
Management information generating means (101) for configuring on the memory a descriptor chain for transferring the band of the code data; and
DMAC which transfers the band of the code data based on the descriptor chain and resumes transfer from the band being transferred at that time or the band immediately before it when a communication error occurs during the transfer;
A data transfer control device comprising:

  (13) The unit that compresses and encodes the image data of one plane into bands and compresses the encoded data into code data for each band, where N is an allowable setting value of the number of occurrences of communication errors during the completion of the transfer of all bands. The code data band is compressed and encoded into code data for each band by dividing the image data of one plane into bands with an image data amount that is equal to or less than a data amount that can be transferred within a timing margin (A) / N. The data transfer control device according to (12).

  (14) The data transfer control device according to (12) or (13), wherein the DMAC transfers data by communication using serial ATA.

  (15) The data transfer control device according to any one of (9) to (14), wherein a band from which the DMAC starts retransmission is a band immediately before a band in which a communication error is detected.

  (16) The DMAC has a register for holding information on the descriptor immediately preceding the descriptor being transferred. When a communication error occurs, the DMAC responds to a retransfer instruction from the management information generating means (101). The data transfer control device according to any one of (9) to (15), wherein band transfer is resumed based on the previous descriptor.

  According to this, when an error occurs, it is not necessary to read out the management information for each band necessary for the transfer from the memory again, so that the retransmission time loss can be minimized. When an error occurs, it is not necessary to read out the management information for each band necessary for transfer from the memory again, so that a retransmission time loss can be minimized.

  (17) The DMAC has a register for holding information on the descriptor immediately preceding the descriptor being transferred. When a communication error occurs, the DMAC automatically transfers a band based on the preceding descriptor. The data transfer control device according to any one of (9) to (15), wherein the data transfer control device is resumed.

  According to this, retransmission time efficiency is good and convenience is enhanced. Automatic retransmission by hardware improves the time efficiency of retransmission and increases convenience.

(18) Primary storage means (105) capable of storing image data of one or more planes;
Secondary storage means (111) capable of storing image data of one or more planes;
Image output means (14);
The data transfer control device according to any one of claims 9 to 11, wherein the image data of the primary storage means (105) is transferred to the secondary storage means (111);
Means (101, 102) for transferring the image data of the band section transferred to the secondary storage means (111) to the image output means (14) via the primary storage means (105);
An image forming apparatus comprising:

(19) Primary storage means (105) capable of storing image data of one or more planes;
Secondary storage means (111) capable of storing code data of image data of one or more planes;
The data transfer control device according to any one of claims 12 to 14, wherein the image data of the primary storage means (105) is encoded by band division and stored in the secondary storage means (111);
The band division code data transferred to the secondary storage means (111) is transferred to the primary storage means (105), read out from the primary storage means (105), decoded into image data, and the image output means (14). ) Means for forwarding to (101,102);
An image forming apparatus comprising:

  (20) The image forming apparatus according to (18) or (19), wherein the secondary storage unit is an HDD (111).

  Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

  FIG. 1 shows a system configuration of an image processing system of a digital color copying machine according to an embodiment of the present invention. The printer controller 100 includes a main CPU (Central Processing Unit) 101, an ASIC 102, an I / C card I / F 103, a ROM (Read Only Memory) 104, a RAM (Random Access Memory) 105, and the like. And various programs such as an image information management program and various data necessary for executing these programs, system data, and the like are stored. Based on the program in the ROM 104, the main CPU 101 uses the RAM 105 as a work memory to control each part of the copying machine, read an image, store an image, send / receive a document with a PC (personal computer), send / receive a facsimile, and copy. , Printing (printout as a printer), management of stored information, usage management, etc. The RAM 105 is also a primary storage device for storing images and codes after compression.

  The operation display board 20 includes various operation keys such as a numeric keypad, a start key, a stop key, and a function key, and also includes a display (liquid crystal display). A user instruction can be input by each operation key and displayed on the display. it can. The display also displays the status of the copier and notifications from the PC or facsimile.

  The facsimile control unit FCU is connected to a telephone line PN, exchanges facsimile control signals with a partner facsimile machine, executes a facsimile communication procedure, and includes a network control unit, a modem, and the like. Thus, automatic outgoing / incoming call processing is performed, and transmission / reception signal modulation / demodulation processing is performed by the modem. As described above, the facsimile control unit FCU performs facsimile communication procedures by exchanging facsimile control signals with the other facsimile apparatus during facsimile communication. The fact that the printer 14 is provided with various functions such as encoding and decoding is added to the facsimile control signal notified to the (transmission side facsimile apparatus) and transmitted to the other party. An information processing apparatus such as a PC (Personal Computer) is connected to the network interface (network I / F) 109 via a LAN (Local Area Network), and the network I / F 109 communicates with the PC etc. In particular, the document information stored in the HDD 111 is transferred to the PC so that the PC can use the image information. The PC outputs a print command and takes scanner data to the copying machine shown in FIG. The HDD 111 is a secondary storage device for storing images and codes after compression.

  The ASIC 102 reads / writes data from / to the HDD 111, and includes a compression / decompression unit and a DMAC, and controls CPU transfer and DMA transfer.

  FIG. 2 shows an outline of functional elements configured in the ASIC 102. The ASIC 102 compresses (encodes) the image data stored in the RAM 105 by the compression / decompression unit 123 and stores it in the HDD 111, and decompresses the code (compressed data) stored in the HDD 111 into image data by the compression / decompression unit. Thus, it can be expanded in the RAM 105. The HDD 111 can store not only the compressed code but also the uncompressed image data itself, and the ASIC 102 bypasses the compression / decompression of the compression / decompression unit 123 and keeps the image data between the RAM 105 and the HDD 111. Data transfer between the engine (scanner 10 and printer 14) / HDD 111 can also be performed.

  The system control unit 120 includes a memory controller that controls access from the main CPU 101 to the modules (121 to 127) inside the ASIC, the RAM 105 outside the ASIC 102, and the HDD 111. The system control unit 120 decodes the command of the main CPU 101 and supplies a control signal and control data for executing the command to the modules (121 to 127) in the ASIC and the RAM 105 and HDD 111 outside the ASIC 102. When storing image data in the HDD 111, the image data DMAC 124 accesses the RAM 105 via the RAM I / F 125, reads the image data in the RAM 105, and transfers it to the compression / decompression unit 123 via the I / F circuit 127 by DMA transfer. Forward. The compression / decompression unit 123 compresses the received image data, and the code data DMAC 122 transfers the compressed data to the HDD I / F 121 and stores it in the HDD 111 via the I / F 121. The image data DMAC 124 is a DMA controller for image transfer, handles an image as a two-dimensional image, and transfers the image in main scanning units. When reading compressed data from the HDD 111, the code data DMAC 122 accesses the HDD 111 via the HDD I / F 121, reads the compressed data of the HDD 111, and transfers it to the compression / decompression unit 123 by DMA transfer. The compression / decompression unit 123 decompresses the received compressed data into image data, transfers it to the image DMAC 124 via the I / F circuit 127, and the image DMAC 124 accesses the RAM 105 via the RAM I / F 125 and writes it to the RAM 105. .

There is also a DMAC in the compression / decompression unit 123 that performs the above-described data transfer by the compression / decompression unit 123 (FIG. 8). A line memory 126 is connected to the compression / decompression unit 123. Generally, a line memory is used to store image data for one line or several lines. There are several reasons for using line memory:
1) When the compression / decompression method is a two-dimensional compression method referring to the previous line,
2) When the compression / decompression device scans one line of image and selects the optimal compression method or internal parameters,
3) Eliminate speed bottlenecks with external I / F.

  Before performing the DMA, the CPU 101 prepares a descriptor destined for each DMAC in the RAM 105. FIG. 3 shows a mode in which two descriptors 610 and 620 addressed to the DMAC 31 are generated on the RAM 105. If two descriptors are generated as shown in FIG. 3, the next descriptor pointer register 611 (one area of the memory: one register) of the first descriptor 610 stores the start address of the second descriptor 620. ing.

  The data in the transfer source address register 612 of the second descriptor 620 indicates the head address of the buffer memory 630. The buffer memory 630 stores data to be transferred. The transfer byte count register 613 of the first descriptor 610 stores the number of bytes to be transferred among the data stored in the buffer memory 630. In the mode word register 614 of the first descriptor 610, the least significant bit, that is, the bit No. At 0, when the transfer indicated by the first descriptor 610 is completed, there is flag data CONT for determining whether or not to generate an interrupt. When this is “1”, the DMAC 31 generates an interrupt signal.

  Similarly, the next descriptor pointer register 621 shown in the second descriptor 620 stores the start address of the third descriptor, if any, but in the illustrated example, the second descriptor 620 is the last descriptor. In order to tell the DMAC 31 that it is the end, “0” is stored. A transfer source address register 622 of the second descriptor 620 indicates the head address of the buffer memory 640, and data to be transferred is stored in the buffer memory 640. The transfer byte count register 623 of the second descriptor 620 stores the number of bytes to be transferred among the data stored in the buffer memory 640. Nothing is set in the mode word register 624 of the second descriptor 620.

  There is an interrupt enable bit “CONT” in the descriptor 610 before the final descriptor, and an interrupt can be generated in units of descriptors using this bit. Descriptor size can be any number of words. The next descriptor address register 611 stores the address of the descriptor 620 to be executed next so that the descriptors 610 and 620 can be linked in a chain structure. The data in the transfer source address register 612 indicates the head address of transfer data (630) secured on the RAM memory 600, assuming that the descriptor 610 transfers data from the buffer memory 630 to the I / O device 500. . Data in the transfer byte number register 613 indicates the length (number of bytes) to be transferred. The mode word register 614 stores a word for setting an operation mode in units of descriptors. The mode word register 614 has a length of 32 bits in this embodiment. The least significant bit, bit No. The data CONT of 0 can take two states “0” and “1”, and this bit data CONT functions as an interrupt enable bit. The interrupt enable bit indicates that it is permitted to generate an interrupt when the transfer indicated by the descriptor whose bit is set to “1” is completed.

  FIG. 4A shows the configuration of the DMAC 31. The descriptor pointer register 401 is a register for storing the head address of the descriptor (610/620) stored on the RAM memory 600. The control register 402 is a register for receiving an instruction to start DMA operation from the CPU 101. The address register 403 stores the transfer source address held by the descriptor, and the transfer counter 409 is a counter that counts the actual number of transfer bytes. The transfer byte number register 410 is a register for storing the transfer byte number indicated by the descriptor.

  The DMA transfer control circuit 404 is a circuit that accesses the memory at the address indicated by the sum of the transfer source address of the address register 403 and the count value (number of transferred bytes) of the transfer counter 409 and performs the actual transfer. The mode register 406 is a register for storing data of the mode word registers 614 and 624 of the descriptor. The descriptor control circuit 405 is a circuit that reads the descriptors 610 and 620. The data (“1” or “0”) of the interrupt instruction bit CONT of the mode register 406 is supplied to the DMA transfer control circuit 404 via the interrupt enable signal line 407. This is a signal notifying whether or not to generate an interrupt when the transfer is completed. When the transfer indicated by the descriptor is completed, the DMA transfer control circuit 404 (DMAC 31) gives a signal notifying the CPU 101 of the interrupt via the interrupt signal line 408.

  The CPU 101 sets the transfer data and descriptor on the RAM 105, writes the leading address of the first descriptor in the descriptor pointer register 401 of the DMAC 31, and writes it to the bit EXEC shown in FIG. 4C in the control register 402. , “1” is written, the DMAC 31 starts a transfer operation in response to this, and the DMAC 31 first proceeds to read descriptor 702. That is, the descriptor on the memory is read. Specifically, the DMAC 31 reads the contents of the address (descriptor 610) indicated by the data in the descriptor pointer register 401, and the first word (next descriptor address) is the next descriptor shown in FIG. Stored in the pointer register 411, the second word (transfer source address) is stored in the address register 403, the third word (transfer byte number) is stored in the transfer byte number register 410, and the fourth word (mode) Is stored in the mode register 406 and the control register 402.

  Next, the DMAC 31 starts the DMA transfer specified by the data in the registers 411, 403, 410, and 406, and checks whether the transfer of the block designated by one descriptor (first descriptor 610) is completed. . If the block transfer is not complete, the address is updated for the next transfer. Repeat the transfer until the block transfer is complete. When the block transfer is completed, the DMAC 31 checks whether the chain of the descriptor itself is completed, that is, whether the entire transfer is completed.

  As described above, in the illustrated example, since the second descriptor 620 is the last descriptor, “0” is written in the next descriptor pointer 621 in order to inform the DMAC 31 that it is the end, and the transfer is now executed. Assuming that this descriptor is the last descriptor (second descriptor 620), data “0” is written in the next descriptor pointer register 411 of the DMAC 31. Based on this data, It is determined that the entire transfer has been completed.

  However, if the transfer that has just been completed is based on the data of the first descriptor 610, the data of the next descriptor pointer 611 of the first descriptor 610 (the start address of the second descriptor 620) is stored in the next descriptor pointer register 411. Since the next descriptor (620) is valid, the DMAC 31 reads the bit CONT stored in the mode register 406, which was originally in the mode word register 614, via the line 407. Is set to “1”, the timer variable (data originally stored in the mode word register 614) written in the control register 402 is set as the time timer, and time measurement is started. When elapses, a continuation interrupt is generated. That is, the DMAC 31 clears the bit EXEC of the control register 402 to “0” and gives an interrupt signal to the interrupt request line 408 to the CPU 101. In response to this, the CPU 101 waits for the bit EXEC of the control register 402 to be set to “1”. When “1” is set, the data of the second descriptor 620 is read and written to the registers 411, 403, 410, 406, 402 and transferred. When “1” is not set in CONT, the continuous interrupt processing is not performed, the data of the second descriptor 620 is read, written to the registers 411, 403, 410, 406, 402 and transferred. Do.

  When the transfer based on the data of the second descriptor 620 is completed, since the data of the next descriptor pointer register 411 is “0”, the DMAC 31 generates a completion interrupt signal and completes the entire processing. To do. The continuous interrupt is valid when the CONT bit of the control register of the DMAC 31 is “1” (first descriptor 610), but does not occur when it is “0” (second descriptor 620). The bit corresponding to the CONT bit also exists in the mode word (624) in the final descriptor (620), but it is set to “0”, and the CONT bit of the control register 402 is set to “0”. Does not occur, but generates a completion interrupt signal.

  In the above example, as shown in FIG. 4B, a timer variable is prepared in the mode word register 614 of the descriptor, and after waiting for the time specified by the timer variable after completion of one block transfer, a continuation interrupt is issued. appear. With this timer variable, the time from the completion of one block transfer to the occurrence of a continuous interrupt can be set. A timer variable is also included in the mode word register (624) of the final descriptor (620) so that a completion interrupt signal is generated after a delay corresponding to the time from the completion of the transfer of the final block. It becomes possible to set.

  As shown in FIG. 4C, the “unused” bit irrelevant to the transfer control by the descriptor is prepared in the mode word register 614 of the descriptor so that the DMAC 31 does not use it. Can read from and write to the “unused” bit, and can be used to manage descriptors by software.

  The other DMAC configurations and functions of the ASIC 102 are the same as the above-described configuration and functions of the DMAC 31.

  FIG. 5 shows an overview of data transfer control of the CPU 101 when print data of the personal computer PC is printed out by the printer 14. The CPU 101 stores the PDL sent from the personal computer PC via the network LAN in the RAM 105 (step 1). In the following, the word “step” is omitted in parentheses, and step no. Write only numbers or symbols. The transfer from the network I / F 109 (or NIC) to the RAM 105 is a DMA transfer using a DMAC or a CPU I / O transfer.

  The CPU 101 converts the PDL into image data (drawing data: image data) using font conversion data (font ROM) in the ROM 104. That is, when a page image is developed (drawn) in the RAM 104 (2) and full-color image recording is performed, an image (plane) of each color (C, M, Y, K) is generated and transferred to the HDD 111 for each plane. (3). In the case of monochrome recording (for example, monochrome recording), a monochrome image (only one plane) is generated and transferred to the HDD 111 (3).

  In the case of facsimile reception data, the data is received by the RAM 105, decompressed to image data, expanded into the RAM 105, and then transferred to the HDD 111 (3). In the case of copying, the original read image data is converted by the ASIC 102 into image data to be printed by the printer 14, read into the RAM 105, and transferred to the HDD 111 (3). Transfer to HDD 111 (3) The following processing is common to all image forming modes of printing, facsimile reception output, and copying. In the following, the process after transfer (3) to the HDD 111 will be described by taking the case of full color image recording as an example.

  In this transfer, the CPU 101 first generates band division information (4). That is, band division information of image data of each plane is generated. Here, band division will be described. See FIG.

-Normal transfer: (a) in FIG.
The time for transferring one plane from the HDD 111 to the memory 105 is indicated by the length of the arrow in FIG. Let X be the time. The amount of data of one plane referred to here varies depending on the compression rate when compressed data that has been compressed and encoded is transferred to the memory 105 as compressed data. A case where image data is stored in the HDD 111, read from the HDD 111, and transferred to the memory 105 will be described.

-Transfer when retransmission occurs in the conventional method: (b) of Fig. 6-
When a transfer error occurs near the end of transfer of one plane and retransmission is performed, transfer of two planes is required. Furthermore, in the case of error interrupt processing or retransmission by DMAC, overhead (dead time or error handling processing time) such as reloading of the descriptor information of DMAC occurs. Let Z be the overhead or overhead time. Since the time required for interrupt control has a large fluctuation range, it is necessary to determine Z longer in consideration of a certain worst case.

-Transfer when error-adaptive retransmission occurs in this embodiment: (c), (d) in FIG.
Let Y be the time that can actually be transferred, that is, the allocated time. Y is longer than the actual transfer time, that is, the required time X. In addition, since the overhead time Z is required when retransmitting, (YX-Z) is an actual timing margin. Let A be the time. “Generation of band division information” (4) is performed as follows:
1. Calculate “Y−X−Z = A (s)”,
2. Amount of data that can be transferred in A (s) Calculate “HDD transfer speed (bps) × A (s)”
3. The division information for dividing the data on the RAM 105 is generated below the amount of data that can be transferred. A group of image data (unit of division) divided by the division information is called “band”.

The band division method differs depending on the timing margin A, but the above method is a division method when it is assumed that retransmission occurs only once during one plane transfer. This is based on the fact that the frequency of occurrence of serial communication errors is low (in the SATA standard, the bit error rate is 1/10 ¹² or less). This division is adapted to each plane. If retransmission does not occur in the previous plane, the timing margin of the subsequent plane actually increases, but it is not known at the stage of band division, so band division is performed assuming that there is one retransmission for each plane. .

  Next, the CPU 101 reads out each band generated by the plane division based on the band division information generated from the RAM 105 and sends it to the SATA for each DMA chain to be sent to the SATA, and to the SATA. A chain of descriptors addressed to the write DMAC 34 for DMA for writing each band to the HDD 111 is generated in the RAM 105 (5). That is, the descriptor having the mode shown in FIG. 3 is generated. In this embodiment, the CONT of each descriptor is “0”. That is, a continuous interrupt is not generated every time one block (band) transfer is completed.

  Next, the CPU 101 writes the transfer control data in the various registers (FIG. 4) of the DMACs 31 and 34 (6), and writes 1 in the EXEC of the control registers of the DMACs 31 and 34 (7). As a result, the DMACs 31 and 34 are activated, and image data is transferred from the RAM 105 to the HDD 111 and written to the HDD 111. A plurality of descriptors are transferred while being chained, whereby the image data of each plane on the RAM 105 is divided into bands for each descriptor (8). When the transfer is completed, a COMPLETE interrupt enters the CPU 101 (9), and in response to this, the CPU 101 performs a transfer end process (10).

  Next, the CPU 101 is a descriptor chain for each DMAC for transferring each band of each plane stored in the HDD 111 to the RAM 105 and transferring each band of each plane transferred to the RAM 105 to the printer 14. As shown in FIG. 7, each band is alternately written from the HDD 111 to two different storage areas of the RAM 105, and during that time, the band is read from the storage area where writing has not been performed and transferred to the printer 14. A descriptor chain for performing read / write band transfer is generated on the RAM 105, and based on the descriptor chain, each image data of each plane of the HDD 111 is transferred to the printer 14 via the RAM 105 (11, 12).

  FIG. 7 shows a transfer path in the transfer (11, 12). FIG. 7 shows an example in which the C color is divided into 8 groups and stored. Each group of divided compressed data is called a “band”. In FIG. 7, only the C color is described, but the same applies to the M, Y, and K colors.

The control when a serial communication error occurs by detecting a CRC error, protocol violation, etc. on the data receiving side while transferring the image data Sdr in band units from the HDD 111 to the RAM 105 is as follows:
1. An error occurs and an error interrupt from the DMAC (or hard disk controller HDC, etc.) is generated in the CPU 101;
2. DMAC automatically stops when an error occurs. Descriptor information is retained and the transfer amount counter is stopped;
3. The CPU 101 reads the register of the DMAC (and the hard disk controller HDC) and confirms in which band the transfer is stopped;
4). Set the start address of the band to be retransmitted in the DMAC so as to transfer from the band immediately before the band being transferred;
5). The DMAC reads the set band descriptor again and resumes data transfer according to the information. Although it may be retransmitted from the band being transferred, it is retransmitted from the previous band for safety. The DMAC 33 that reads the HDD 111 starts reading the next descriptor, but the DMAC 32 that writes the RAM 105 is to avoid the confusion that the RAM 105 is congested and the previous band is still being transferred.

  For example, as illustrated in FIG. 8, when an interrupt due to a communication error occurs while transferring the third band image data Sdr to the RAM 105 based on the third descriptor, the CPU 101 performs the third descriptor by performing a communication error interrupt process. The control information for transferring the immediately preceding second descriptor is reset in the DMACs 33 and 32, and the transfer from the second descriptor is resumed.

  In the transfer of band-segment image data from the RAM 105 to the HDD 111 shown in FIG. 5, if a communication error occurs, the communication error interruption process holds the communication error in the DMAC as described above. The control information for transferring the descriptor immediately preceding the descriptor (preceding descriptor) is reset in the DMACs 31 and 34, and the transfer from the preceding descriptor is resumed.

According to the first embodiment, when any one of the divided data (bands) is retransmitted only once due to a communication error, the total transfer time is equal to or less than the allocated time Y, so that the productivity / real-time property is achieved. Can be maintained. SATA standard error rate or bit error rate, 1/10 ¹² So multiple error never occurs in the data transfer to be close, i.e., during transfers of the entire data, more than once a communication error It is thought that it does not occur. Therefore, the number of band divisions can be minimized. When the number of divisions is large, software data management becomes complicated, and the number of DMAC descriptors increases and memory is wasted.

  The hardware of the second embodiment is the same as that of the first embodiment described above. However, in the second embodiment, compressed data obtained by compressing and encoding image data by the compression / decompression unit 123 is stored in the HDD 111. Store.

  FIG. 9 shows an outline of data transfer control of the CPU 101 when print data of the personal computer PC is printed out by the printer 14. The CPU 101 stores the PDL sent from the personal computer PC via the network LAN in the RAM 105 (1). The CPU 101 develops (draws) a page image in the RAM 104 using the font conversion data (font ROM) of the ROM 104, and in the case of full color image recording, each color (C, M, Y, K) is stored on the RAM 104. An image (plane) is generated (2). Then, compression encoding is performed (21).

  In the case of facsimile reception data, the data is received by the RAM 105, decompressed to image data, expanded into the RAM 105, and then compressed and encoded (21). In the case of copying, the original read image data is converted by the ASIC 102 into image data to be printed by the printer 14, read into the RAM 105, and compressed and encoded (21). The processing after compression encoding (21) is common to all image forming modes of printing, facsimile reception output and copying. In the following, the processing after compression encoding (21) will be described by taking the case of full color image recording as an example. In FIG. 10, the flow of data in compression encoding (21) is indicated by solid arrows.

  In this compression encoding (21), the CPU 101 first generates band division information (22). That is, band division information of image data of each plane is generated. Here, the code data amount is an image data amount that is equal to or less than the data amount that can be transferred within the timing margin A determined from the allocation time Y, the required time X, and the overhead time Z required for resuming communication at the time of a communication error. Band division information for dividing plane image data into bands is generated.

  Next, the CPU 101 reads out each band generated by plane division based on the generated band division information from the RAM 105 and transfers it to the compression / decompression unit 123, and transfers the code data compression-encoded by the compression / decompression unit 123 to the RAM 105. The descriptor chain for each read DMAC and each write DMAC in the image DMAC 124 and in the compression / decompression unit 123 is generated in the RAM 105 (23).

  Next, the CPU 101 writes transfer control data in various registers of each DMAC (24), and writes 1 in the EXEC of the control register of each DMAC (25). As a result, each DMAC is activated, image data is transferred from the RAM 105 to the compression / decompression unit 123 in band units, converted into code data in band units, and a code data band is written in the RAM 105 (26). A plurality of descriptors are transferred while being chained, whereby the image data of each plane on the RAM 105 is divided into bands for each descriptor, encoded, and written into the RAM 105. When the transfer is completed, a COMPLETE interrupt enters the CPU 101 (27), and in response to this, the CPU 101 performs a transfer end process (28).

  Next, the CPU 101 transfers the band segment encoded data on the RAM 105 to the HDD 111 (3B). This content is the same as the transfer control in steps 5 to 10 in the transfer (3) to the HDD 111 shown in FIG. However, the transfer data is a band of encoded data. In FIG. 10, the flow of encoded data from the RAM 105 to the HDD 111 is indicated by dotted arrows.

  When a serial communication error occurs due to detection of a CRC error, protocol violation, or the like on the data receiving side when the encoded data Sdw is being transferred from the RAM 105 to the HDD 111 in band units, the CPU 101 Reads the register of the DMAC (and the hard disk controller HDC), confirms which band has been stopped, and sets the start address of the band to be retransmitted so as to transfer from the previous band. Set to DMAC and restart DMAC. The DMAC reads the set band descriptor again and resumes data transfer according to the information. For example, as illustrated in FIG. 11, when an interrupt due to a communication error occurs when the encoded data of the third band is transferred to the HDD 111 based on the third descriptor, the CPU 101 performs the third descriptor by performing a communication error interrupt process. The control information for transferring the immediately preceding second descriptor is reset in the DMAC, and the transfer from the second descriptor is resumed.

  As indicated by arrows in FIG. 10, instead of transfer processing in which image data is transferred from the RAM 105 to the compression / decompression unit 123 and compressed and encoded, the encoded data is written in the RAM 105, and then transferred from the RAM 105 to the HDD 111. As shown in FIG. 12, it is also possible to employ a transfer process in which the image data Sdw is transferred from the RAM 105 to the compression / decompression unit 123 and compressed and encoded, and the encoded data is transferred from the compression / decompression unit 123 to the HDD 111.

  Refer to FIG. 9 again. When the encoded data is transferred to the HDD 111, the CPU 101 transfers the code data Sdr of the band of the HDD 111 to the RAM 105 (31), and then transferred from the RAM 105 to the compression / decompressor 123, where it is decoded into image data and is decoded via the video output VOUT. To the printer 14 (12B). The flow of data in this transfer process is shown in FIG.

  The flow of data in this transfer process is shown in FIG. The compressed data stored in the HDD 111 is transferred as it is to the RAM 105 by the DMAC in the ASIC 102 (dotted line arrow in FIG. 13). This transfer is performed sequentially for each plane. Transfer of each plane is performed sequentially for each band. When each plane is transferred to the RAM 105, each plane is output to the printer 14 while being decompressed into image data by the DMAC in the ASIC 102 (solid arrow in FIG. 13). This transfer mode is assumed to be applied to a high-speed machine. Even if it starts to output to the printer 14 for each plane, even if a serial communication error occurs, it can be retransmitted for each band, so that a system that does not wait for the printer 14 at a timing can be constructed. In addition, the RAM 105 reads and writes the first band image data in the first area of the RAM 105, and then reads out the first band image data from the first area and outputs it to the printer 14 in parallel. The second band image data is written in the second area, and then the second band image data is read from the second area and output to the printer 14 in parallel with the third band in the first area of the RAM 105. This is toggle-type read / write control in which the first area and the second area of the RAM 105 are alternately switched between reading and writing and the small area of the RAM 105 is used efficiently. However, the RAM 105 may be a large-capacity memory in which all data is stored, and each band may be sequentially written in different areas of the RAM 105, and at the same time, the band written earlier may be sequentially read out to the plotter. .

  When a serial communication error occurs due to detection of a CRC error, protocol violation, etc. on the data receiving side while transferring encoded data in units of bands from the HDD 111 to the RAM 105, the CPU 101 The DMAC (and the hard disk controller HDC) register is read to confirm which band has been transferred, and the start address of the band to be retransmitted is set to DMAC so that transfer is performed from the band immediately before the band being transferred. To restart the DMAC. The DMAC reads the set band descriptor again and resumes data transfer according to the information. For example, as illustrated in FIG. 14, when an interrupt due to a communication error occurs when encoded data of the third band is transferred to the HDD 111 based on the third descriptor, the CPU 101 performs the third descriptor by performing a communication error interrupt process. The control information for transferring the immediately preceding second descriptor is reset in the DMAC, and the transfer from the second descriptor is resumed.

  Instead of the transfer process of transferring the code data band from the RAM 105 to the compression / decompression unit 123 as shown by the solid line arrow in FIG. 13 and decoding it into image data, and outputting the image data to the printer 14 via the video output VOUT, A transfer process in which the image data decoded by the compression / decompression unit 123 is transferred to the RAM 105 and then output from the RAM 105 to the printer 14 via the video output VOUT may be employed.

  Other configurations and functions of the second embodiment are the same as those of the first embodiment.

  The hardware of the third embodiment is similar to that of the first embodiment, but in the DMAC that performs ASATA transfer in the ASIC 102, a backup register that stores the previous register setting value, and responds to an error occurrence. A mechanism for setting the data stored in the backup register (the previous register setting value) in the register for starting (resuming) the transfer. The data transfer format by the CPU 101 and the ASIC 102 in the third embodiment stores code data (compressed data) obtained by compressing and encoding image data in the HDD 111 as in the second embodiment. Again, as in the second embodiment, the code data amount uses the timing margin A determined from the allocation time Y, the required time X, and the overhead time Z required for restarting communication when a communication error occurs.

In the third embodiment, the CPU 101 divides one plane into bands and performs SATA transfer based on the descriptor chain, so that even if there are N times of retransmission corresponding to an error, data processing or image processing is not hindered. To divide each plane into bands:
1. Calculate “(Y−X−Z) / N = B (s)” [(Y−X−Z) = A],
2. Calculate the amount of data that can be transferred in B (s) “HDD transfer rate (bps) × B (s)”.
3. The image data of one plane of the RAM 105 is divided into bands and read from the RAM 105 with less than the transferable data amount, the image data of each band is compressed and encoded, and the code data is stored in the HDD 111 in the band division.

  In the above band division concept, a time for the DMAC to read the descriptor from the RAM 105 is generated for each band, but this time is omitted. This is because, as described above, it is assumed that no memory access occurs due to the register mechanism that stores the previous register setting value in the DMAC. In an embodiment without a register setting value saving mechanism, “(Y−X−Z−C) / N = B (s)” in consideration of the descriptor read time C from the RAM 105 (N−1) times. And

The DMAC that performs the SATA transfer of the ASIC 102 of the third embodiment holds the previous descriptor in a register, and provides a “retry bit” in a certain register (for example, the control register 402). Operate:
1. The CPU 101 is notified of a communication error interrupt. DMAC automatically stops;
2. The CPU 101 writes 1 in the “retry bit” instead of the original “activation bit” EXEC;
3. If the previous descriptor information is stored, the information is loaded into the operation register 401 and the DMAC is activated. If the previous descriptor information is not stored (for example, when an error has not occurred), an error interrupt is issued to the CPU 101;
4). After that, it is the same as normal operation. Other configurations and functions of the third embodiment are the same as those of the second embodiment.

  The DMAC that controls the SATA transfer of the ASIC 102 according to the third embodiment stores the data representing the descriptor preceding the descriptor represented by the descriptor pointer register 401 in addition to the descriptor pointer register 401 and the next descriptor pointer 411 shown in FIG. When the descriptor control circuit 405 has a descriptor pointer (412: not shown) and stops the transfer due to a communication error, the descriptor control circuit 405 writes the data of the descriptor pointer register 401 to the next descriptor pointer 411 and the data of the ahead descriptor pointer 412 to the descriptor pointer. Write to the register 401, write "1" to the ahead use register, and when the CPU 101 sets EXEC to 1, the transfer is started A. Descriptor control circuit 405 When this transfer ends normally, the descriptor control circuit 405 clears the ahead use register, but if a communication error occurs and the ahead use register has “1”, the descriptor pointer registers 401 and 411 When the CPU 101 sets EXEC to 1, the transfer is started. That is, the transfer of the same band is resumed again based on the descriptor when the communication error occurs.

  Other configurations and functions of the fourth embodiment are the same as those of the second embodiment.

  As in the fourth embodiment, the DMAC that controls the SATA transfer of the ASIC 102 of the fifth embodiment includes an ahead descriptor pointer (412: not shown). When the transfer is stopped due to a communication error, the descriptor control circuit 405 The data of the descriptor pointer register 401 is written to the next descriptor pointer 411, the data of the ahead descriptor pointer 412 is written to the descriptor pointer register 401, and the decimal number 1 is written to the error count register. In the fifth embodiment, when the descriptor control circuit 405 updates the data in response to a communication error, the DMAC transfer is automatically started. When the descriptor control circuit 405 normally completes this transfer, the descriptor control circuit 405 clears the error number register. However, when a communication error occurs and the value of the error number register is 1 or more, the descriptor pointer register The data 401 and 411 are not updated, and the transfer is automatically started. That is, the transfer of the same band is resumed again based on the descriptor when the communication error occurs. When the transfer for one plane is completed, the error count register data is sent to the CPU 101 to initialize the error count register.

  As described above, in the fifth embodiment, the communication error interrupt is interpreted not by the CPU 101 but by the DMAC itself, and the subsequent retransmission procedure is automatically performed. After the transfer is completed, it is desirable to cumulatively display the number of errors in the register in order to notify the CPU of the occurrence of the error. Other configurations and functions of the fifth embodiment are the same as those of the fourth embodiment.

1 is a block diagram showing a system configuration of an electrical system of a multifunction digital color copier according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a functional configuration mainly relating to image data transfer of the ASIC shown in FIG. 1. FIG. 3 is a block diagram showing a descriptor chain for DMAC generated on a RAM 105 by a CPU 101 shown in FIG. 2. (A) is a block diagram showing an outline of a functional configuration of the read DMAC 31 shown in FIG. 2, and (b) and (c) are block diagrams showing data names stored in a register 401 shown in (a). 3 is a flowchart showing an outline of image data transfer control at the time of “printing” performed by the CPU 101 shown in FIG. 2 is a time chart schematically showing the lengths of time parameters X, Y, Z and Z used by the CPU 101 for band division, and the horizontal axis is the time axis. FIG. 6 is a block diagram showing a flow (solid arrow) of image data transferred to the printer 14 by “transfer to RAM 105” (11) and “transfer to printer 14” (12) shown in FIG. 5; FIG. 8 is a block diagram illustrating a process of starting retransfer using a second band descriptor when a communication error occurs during the third band transfer in the transfer illustrated in FIG. 7. 12 is a flowchart showing an outline of image data transfer control during “printing” performed by the CPU 101 of the second embodiment using the ASIC 102 of the second embodiment. FIG. 10 is a block diagram showing a flow of transfer data by “encoding” (21) and “transfer to HDD 111” (3B) shown in FIG. 9; FIG. 11 is a block diagram illustrating a process of starting retransfer using a second band descriptor when a communication error occurs during the third band transfer in the transfer illustrated in FIG. 10. FIG. 11 is a block diagram showing a variation of the transfer shown in FIG. 10. FIG. 10 is a block diagram showing a flow of transfer data by “transfer to RAM 105” (31) and “decryption and transfer to printer 14” (12B) shown in FIG. 9; FIG. 14 is a block diagram illustrating a process of starting retransfer using a second band descriptor when a communication error occurs during the third band transfer in the transfer illustrated in FIG. 13. A block showing a flow of data transfer for reading the code data of each conventional full-color plane from the HDD, transferring it to the compression / decompression unit CEP via the RAM 105 in units of planes, decoding the image data there, and then outputting to the printer 14 FIG. In the data transfer shown in FIG. 15, a communication error occurs during transfer of one plane M, and when the transfer is restarted from one plane M in response to this, the time chart showing each plane transfer time is shown. It is a time axis.

Explanation of symbols

10: Scanner 14: Printer 20: Operation board 101: CPU
102: Controller ASIC
103: IC card I / F
104: ROM
105: RAM
106: HDD I / F
107: Operation unit I / F
108: Engine I / F
109: Network I / F
110: IC card 111: HDD
FCU: Facsimile control unit PN: Telephone line PC: Host (PC)

Claims (20)

When all the data that can be transferred in the required time within the allocated time is transferred by DMAC,
Data is transferred divided into bands that are less than or equal to the amount of data that can be transferred within the timing margin determined from the allocation time, the required time, and the overhead time required for resuming communication at the time of communication error. A data transfer control method, wherein transfer is resumed from a band or a band immediately before.   If the allowable setting value of the number of occurrences of communication errors in all data transfer is N, data is transferred in a band equal to or less than the amount of data that can be transferred within the timing margin / N, and if a communication error occurs, transfer is in progress The data transfer control method according to claim 1, wherein the transfer is resumed from the previous band or the band immediately preceding it.   3. The data transfer control method according to claim 1, wherein the all data is image data of one plane, and the transfer by the DMAC is communication using serial ATA. When transferring all the encoded data in an amount that can be transferred in the required time within the allocated time, by compressing and encoding the image data of one plane,
The amount of code data is the amount of image data that is less than or equal to the amount of data that can be transferred within the timing margin determined from the allocation time, the required time, and the overhead time required for restarting communication in the event of a communication error. Decode and compress and encode into code data for each band, transfer the band of code data generated by this, and when a communication error occurs, restart the transfer from the band of code data being transferred at that time or the band immediately preceding it A data transfer control method characterized by the above.   When the allowable setting value of the number of occurrences of communication errors in all code data transfer is N, the image data amount of one plane is divided into bands with an image data amount equal to or less than the data amount that can be transferred within the timing margin / N. The code data is compressed and encoded each time, and the band of the code data generated thereby is transferred. When a communication error occurs, the transfer is restarted from the band of the code data currently being transferred or the band immediately preceding it. The data transfer control method described.   6. The data transfer control method according to claim 4, wherein the transfer by the DMAC is communication using serial ATA.   The data transfer control method according to claim 1, wherein a data transfer destination or transfer source is an HDD.   The data transfer control method according to any one of claims 1 to 7, wherein a band from which retransmission is started is a band immediately before a band in which a communication error is detected. Descriptor chain for dividing the transfer target data group into a band that is less than or equal to the amount of data that can be transferred within a timing margin determined from the allocated time, required time for the transfer target data group, and the overhead time required for restarting communication in the event of a communication error Management information generating means for configuring the memory on the memory; and
A DMAC that transfers a transfer target data group for each of the band sections based on the descriptor chain, and resumes transfer from the band that is being transferred at that time or the band immediately before it when a communication error occurs during the transfer;
A data transfer control device comprising:   The management information generation means assigns the transfer target data group to a band that is less than or equal to the amount of data that can be transferred within the timing margin / N, where N is the allowable setting value of the number of occurrences of communication errors in the transfer target data group transfer. The data transfer control device according to claim 9, wherein a descriptor chain for delimiting is configured on a memory.   The data transfer control device according to claim 9 or 10, wherein the transfer target data group is image data of one plane, and the DMAC transfers using serial ATA. The amount of code data is the amount of image data that is less than or equal to the amount of data that can be transferred within the timing margin determined from the allocation time, the required time, and the overhead time required for restarting communication in the event of a communication error. Means for compressing and coding into code data for each band by dividing;
Management information generating means for configuring a descriptor chain on the memory for transferring the band of code data; and
DMAC which transfers the band of the code data based on the descriptor chain and resumes transfer from the band being transferred at that time or the band immediately before it when a communication error occurs during the transfer;
A data transfer control device comprising:   The means for compressing and encoding the one-plane image data into bands and compressing the encoded data into code data for each band, where N is the allowable setting value for the number of occurrences of communication errors during the completion of the transfer for all bands, The data according to claim 12, wherein one band of image data is compressed into encoded data for each band by dividing the image data of one plane into bands with an image data amount equal to or less than a data amount that can be transferred within a timing margin / N. Transfer control device.   The data transfer control device according to claim 12 or 13, wherein the DMAC transfers data by communication using serial ATA.   The data transfer control device according to any one of claims 9 to 14, wherein a band from which the DMAC starts retransmission is a band immediately before a band in which a communication error is detected.   The DMAC has a register for holding information on a descriptor immediately preceding the descriptor being transferred. When a communication error occurs, the DMAC responds to a retransfer instruction from the management information generation means in response to the previous transfer instruction. The data transfer control device according to any one of claims 9 to 15, wherein the transfer of the band is resumed based on the descriptor.   The DMAC has a register for holding information on a descriptor immediately before the descriptor being transferred. When a communication error occurs, the DMAC restarts band transfer based on the previous descriptor by self-activation. The data transfer control device according to any one of claims 9 to 15. Primary storage means capable of storing image data of one or more planes;
Secondary storage means capable of storing image data of one or more planes;
Image output means;
The data transfer control device according to any one of claims 9 to 11, wherein the image data of the primary storage means is transferred to the secondary storage means; and
Means for transferring the image data of the band section transferred to the secondary storage means to the image output means via the primary storage means;
An image forming apparatus comprising: Primary storage means capable of storing image data of one or more planes;
Secondary storage means capable of storing code data of image data of one or more planes;
The data transfer control device according to any one of claims 12 to 14, wherein the image data of the primary storage means is encoded by band division and stored in the secondary storage means;
Means for transferring the code data of the band section transferred to the secondary storage means to the primary storage means, reading out from the primary storage means, decoding it into image data, and transferring it to the image output means;
An image forming apparatus comprising: The image forming apparatus according to claim 18, wherein the secondary storage unit is an HDD.

Images