JP2006012950A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2006012950A
JP2006012950A JP2004184631A JP2004184631A JP2006012950A JP 2006012950 A JP2006012950 A JP 2006012950A JP 2004184631 A JP2004184631 A JP 2004184631A JP 2004184631 A JP2004184631 A JP 2004184631A JP 2006012950 A JP2006012950 A JP 2006012950A
Authority
JP
Japan
Prior art keywords
metal protrusion
semiconductor element
metal
substrate
conductive paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004184631A
Other languages
Japanese (ja)
Inventor
Yukitoshi Ota
行俊 太田
Noriyuki Nagai
紀行 永井
Toshiyuki Fukuda
敏行 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2004184631A priority Critical patent/JP2006012950A/en
Publication of JP2006012950A publication Critical patent/JP2006012950A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499—Material of the matrix
    • H01L2224/8159—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To enlarge an adhesive area between the conductive paste on a metallic projection and the electrode pad of a substrate in order to correspond to multiple pins as well as prevent failure in open connection due to the warpage of a substrate or the like. <P>SOLUTION: The semiconductor device is provided with a semiconductor element 1 wherein a plurality of electrode pads 2 are arranged on a circuit formation surface and a substrate 7 wherein a plurality of electrodes 8 are arranged on a surface facing the circuit formation surface of the semiconductor element and a plurality of external terminals 11 are arranged on the reverse surface thereto, and the electrode pads 2 of the semiconductor element 1 and the electrodes 8 of the substrate 7 are electrically connected with each other by means of a plurality of metallic projections 4 and a conductive paste 6. The metallic projections 4 are formed on the electrode pads 2 in plural rows on the circuit formation surface of the semiconductor element 1, and the sectional shape of a metallic projection 4c arranged in the central area on the circuit formation surface of the semiconductor element 1 is in nearly a chevron form having a field with swelling skirts. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、半導体素子の回路形成面に複数列の電極パッドを有し、前記半導体素子をフリップチップ実装方法で実装した半導体装置に関するものであり、特に半導体装置の多ピン化、小型化に対応できる半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device having a plurality of rows of electrode pads on a circuit formation surface of a semiconductor element, and mounting the semiconductor element by a flip chip mounting method, and is particularly suitable for increasing the number of pins and miniaturization of a semiconductor device. The present invention relates to a semiconductor device that can be manufactured and a manufacturing method thereof.

近年の電子機器の小型化により、半導体装置にも小型化が要求されている。しかし、高性能化に伴う半導体素子の多ピン化により、従来の半導体素子の外周部だけに電極パッドを形成するペリフェラル配置では半導体装置は大型化してしまい小型化の要求に対応できない。そこで、半導体素子の回路形成面に電極パッドをペリフェラル配置から電極パッドを複数列に配置したエリアパッド配置が必要となってきている。半導体装置を小さく（薄型化）するために半導体素子の回路形成面を直接基板に実装する方法としフリップチップ実装方法がある（例えば特許文献１）。   Due to the recent miniaturization of electronic devices, miniaturization of semiconductor devices is also required. However, due to the increase in the number of pins of the semiconductor element due to the high performance, the peripheral arrangement in which the electrode pad is formed only on the outer peripheral portion of the conventional semiconductor element becomes large in size and cannot meet the demand for downsizing. Therefore, an area pad arrangement in which electrode pads are arranged in a plurality of rows from a peripheral arrangement to a circuit formation surface of a semiconductor element is required. There is a flip chip mounting method as a method of directly mounting a circuit formation surface of a semiconductor element on a substrate in order to make a semiconductor device small (thinner) (for example, Patent Document 1).

以下、図１５と図１６を参照して従来のフリップチップ実装方法を説明する。半導体素子１の回路形成面に配置した複数列の電極パッド２にキャピラリ３により凸型金属突起４を形成する。以下、凸型金属突起４は金（Ａｕ）で形成する場合について説明する。   Hereinafter, a conventional flip chip mounting method will be described with reference to FIGS. Convex metal protrusions 4 are formed by capillaries 3 on a plurality of rows of electrode pads 2 arranged on the circuit formation surface of the semiconductor element 1. Hereinafter, the case where the convex metal protrusion 4 is formed of gold (Au) will be described.

図１５（ａ）に示すようにキャピラリ３の形状は、先端に平坦面３１を有し、先端方向に細くなった円錐形状である。キャピラリ３の軸心には金属ワイヤ４１の通るキャピラリホール３２が設けられている。前記金属ワイヤ４１の材質は９９．９９％以上の金（Ａｕ）より構成され、金属ワイヤ４１の線径はφ１８μｍから３０μｍ程度である。   As shown in FIG. 15A, the shape of the capillary 3 is a conical shape having a flat surface 31 at the tip and narrowing in the tip direction. A capillary hole 32 through which the metal wire 41 passes is provided at the axial center of the capillary 3. The metal wire 41 is made of 99.99% or more gold (Au), and the wire diameter of the metal wire 41 is about 18 μm to 30 μm.

キャピラリホール３２より金属ワイヤ４１を出し、金属ワイヤ４１の先端を放電等で融解させ、球状のＡｕボール４２を形成する。図１５（ｂ）に示すようにＡｕボール４２は半導体素子１の回路形成面に配置した複数列の電極パッド２に、超音波振動を加えながら圧着される。電極パッド２の最表面の材質はＡｌ層で構成され、ＡｌとＡｕの合金形成により接続される。   A metal wire 41 is taken out from the capillary hole 32, and the tip of the metal wire 41 is melted by electric discharge or the like to form a spherical Au ball. As shown in FIG. 15B, the Au balls 42 are pressure-bonded to the plurality of rows of electrode pads 2 arranged on the circuit formation surface of the semiconductor element 1 while applying ultrasonic vibration. The material of the outermost surface of the electrode pad 2 is composed of an Al layer and is connected by forming an alloy of Al and Au.

キャピラリ３を上に引き上げ、金属ワイヤ４１を引きちぎることにより図１５（ｃ）に示すように中心が突き出て周囲が平らな台４３になった環状の金属突起４が形成される。これを繰り返すことにより、図１６（ａ）に示すように半導体素子外周部と中央領域に複数列の金属突起を形成する。図１６（ｂ）に示すように金属突起の先端部４４にレベリングツール５で一定の荷重を加えレベリングを行い、金属突起４の高さを均一にする。この金属突起４にレベリング時に加える荷重は金属突起あたり、１５ｇｆから２５ｇｆである。図１６（ｃ）に示すように金属突起４の形成面を下側にし、金属突起４を導電性ペーストに浸漬させ、表面張力により導電性ペースト６を転写する。図１６（ｄ）に示すように金属突起４を基板７の電極パッド８に圧着し、導電性ペース６トを加熱により硬化させる。図１６（ｅ）に示すように半導体素子１の回路形成面と基板７の電極面側間にアンダーフィルと呼ばれるエポキシ樹脂等９を充填する。図１６（ｆ）に示すように加熱硬化させ封止する。   By pulling up the capillary 3 and tearing the metal wire 41, an annular metal protrusion 4 having a center 43 protruding into a flat base 43 as shown in FIG. 15C is formed. By repeating this, as shown in FIG. 16A, a plurality of rows of metal protrusions are formed in the outer periphery of the semiconductor element and the central region. As shown in FIG. 16B, the leveling tool 5 applies a constant load to the tip 44 of the metal protrusion to level it, thereby making the height of the metal protrusion 4 uniform. The load applied to the metal protrusion 4 during leveling is 15 gf to 25 gf per metal protrusion. As shown in FIG. 16C, the metal projection 4 is formed on the lower side, the metal projection 4 is immersed in the conductive paste, and the conductive paste 6 is transferred by surface tension. As shown in FIG. 16 (d), the metal protrusion 4 is pressure-bonded to the electrode pad 8 of the substrate 7, and the conductive pace 6 is cured by heating. As shown in FIG. 16E, an epoxy resin 9 called an underfill is filled between the circuit forming surface of the semiconductor element 1 and the electrode surface side of the substrate 7. As shown in FIG. 16 (f), it is cured by heating and sealing.

図１７は従来の半導体装置の断面図である。図１８は上から見た金属突起の配置図である。線Ａ−Ａ’は図１７の断面図の位置である。金属突起４ａが半導体素子１の外周に形成された金属突起となり、金属突起４ｂが半導体素子の中央領域に形成された金属突起になる。基板の下には外部端子１１がある。
特開２００１−８５４７２号公報 FIG. 17 is a cross-sectional view of a conventional semiconductor device. FIG. 18 is a layout view of metal protrusions as viewed from above. Line AA ′ is the position of the cross-sectional view of FIG. The metal protrusion 4a becomes a metal protrusion formed on the outer periphery of the semiconductor element 1, and the metal protrusion 4b becomes a metal protrusion formed in the central region of the semiconductor element. There are external terminals 11 under the substrate.
JP 2001-85472 A

従来の方法で半導体素子の電極パッドがエリアパッド配置の場合に半導体素子を基板にフリップチップ実装した場合、熱等により図１９の様に凹型に基板が反ると、半導体素子１の外周部の電極パッド２ａに形成された金属突起４ａの位置での基板の反り量が１０μｍ以下に対し、半導体素子１の中央領域の電極パッド２ｂに形成された金属突起４ｂの位置での基板の反り量は５０μｍと大きいため、半導体素子１の中央領域にオープン不良が多発していた。また、最初は半導体素子１の中央領域の電極パッド２ｂに形成された金属突起４ｂが電気的に接続されていても繰り返し使用している間に、図２０に示すように半導体素子１の中央領域にオープン不良が起こるという問題も生じていた。   When the semiconductor element is flip-chip mounted on the substrate when the electrode pads of the semiconductor element are arranged in an area pad by a conventional method, if the substrate warps in a concave shape as shown in FIG. Whereas the amount of warpage of the substrate at the position of the metal protrusion 4a formed on the electrode pad 2a is 10 μm or less, the amount of warpage of the substrate at the position of the metal protrusion 4b formed on the electrode pad 2b in the central region of the semiconductor element 1 is Since it was as large as 50 μm, open defects frequently occurred in the central region of the semiconductor element 1. First, as shown in FIG. 20, while the metal protrusion 4b formed on the electrode pad 2b in the central region of the semiconductor element 1 is electrically connected, it is repeatedly used, as shown in FIG. There was also a problem that an open failure occurred.

これらの問題を解決するには、基板７の反り量を吸収し、接着強度を確保できる様に、半導体素子１の中央領域の電極パッド２ｂに形成された金属突起４ｂ上の導電性ペースト６と基板７の電極パッド８の接着面積を大きくする必要がある。そのためには、金属突起４上に多くかつ高く導電性ペースト６を積む必要がある。しかしながら、転写できる導電性ペースト６の量は、導電性ペースト６と金属突起４の接着面積により限界がある。その上、凸型の金属突起の場合、図２１（ａ）に示すように金属突起４に転写する導電性ペースト６の量が多いと基板７と金属突起４を圧着する時に、図２１（ｂ）に示すように金属突起の台部４３で導電性ペースト６を支えきれずこぼれてしまい、導電性ペースト６が隣接した他の金属突起等に接触しショートしてしまうという問題も生じていた。これは、特に基板７と金属突起４との間隔が狭くなる、基板７の反り量が小さい位置に接着される金属突起４で生じていた。   In order to solve these problems, the conductive paste 6 on the metal protrusion 4b formed on the electrode pad 2b formed in the central region of the semiconductor element 1 can be used to absorb the warp amount of the substrate 7 and secure the adhesive strength. It is necessary to increase the bonding area of the electrode pads 8 on the substrate 7. For this purpose, it is necessary to stack a large amount of conductive paste 6 on the metal protrusion 4. However, the amount of the conductive paste 6 that can be transferred is limited by the bonding area between the conductive paste 6 and the metal protrusion 4. In addition, in the case of a convex metal protrusion, when the amount of the conductive paste 6 transferred to the metal protrusion 4 is large as shown in FIG. ), The conductive paste 6 cannot be supported by the base portion 43 of the metal protrusions, and the conductive paste 6 spills, causing a problem that the conductive paste 6 contacts other adjacent metal protrusions and shorts. This occurs particularly in the metal protrusion 4 bonded to a position where the distance between the substrate 7 and the metal protrusion 4 becomes narrow and the warpage amount of the substrate 7 is small.

また、基板は図２２に示すように凸型に反る場合もある。この場合、半導体素子１の外周部の電極パッド２ａの位置の基板７の反り量が大きくなるので、半導体素子１の外周部にオープン不良が生じる問題が発生していた。   Further, the substrate may warp in a convex shape as shown in FIG. In this case, the amount of warpage of the substrate 7 at the position of the electrode pad 2a on the outer peripheral portion of the semiconductor element 1 becomes large, so that there is a problem that an open defect occurs on the outer peripheral portion of the semiconductor element 1.

したがって、この発明の目的は、多ピン化に対応し、基板の反り等によるオープン不良を防ぐ為に、金属突起上の導電性ペーストと基板の電極パッドの接着面積を大きくでき、かつ金属突起と基板とを圧着する時にも金属突起の台部で導電性ペーストを支えることができる金属突起を有し、また量産でのロスをなくすために一本のキャピラリで金属突起を形成することができる半導体装置およびその製造方法を提供することである。   Therefore, the object of the present invention is to increase the number of pins, to prevent open defects due to warping of the substrate, etc., and to increase the bonding area between the conductive paste on the metal protrusion and the electrode pad of the substrate, and Semiconductor that has metal protrusions that can support the conductive paste on the base of the metal protrusions when crimping to the substrate, and can form metal protrusions with a single capillary to eliminate loss in mass production An apparatus and a method for manufacturing the same are provided.

上記目的を達成するためにこの発明の請求項１記載の半導体装置は、回路形成面に複数の電極パッドを配置した半導体素子と、前記半導体素子の回路形成面と対向する面に複数の電極部を配置し反対側の面に複数の外部端子を配置した基板とを備え、前記半導体素子の電極パッドと前記基板の電極部は、複数の金属突起と導電性ペーストを介して各々電気的に接続される半導体装置であって、前記金属突起は、前記半導体素子の回路形成面に複数列となるように前記電極パッドに形成され、前記半導体素子の回路形成面の中央領域に配置する金属突起の断面形状は、周縁が盛り上がった裾野を有する略山形形状である。   In order to achieve the above object, a semiconductor device according to claim 1 of the present invention includes a semiconductor element in which a plurality of electrode pads are arranged on a circuit formation surface, and a plurality of electrode portions on a surface facing the circuit formation surface of the semiconductor element. And an electrode pad of the semiconductor element and an electrode portion of the substrate are electrically connected to each other through a plurality of metal protrusions and a conductive paste, respectively. The metal protrusion is formed on the electrode pad so as to form a plurality of rows on the circuit formation surface of the semiconductor element, and the metal protrusion is disposed in a central region of the circuit formation surface of the semiconductor element. The cross-sectional shape is a substantially chevron shape having a base with a raised peripheral edge.

請求項２記載の半導体装置は、回路形成面に複数の電極パッドを配置した半導体素子と、前記半導体素子の回路形成面と対向する面に複数の電極部を配置し反対側の面に複数の外部端子を配置した基板とを備え、前記半導体素子の電極パッドと前記基板の電極部は、複数の金属突起と導電性ペーストを介して各々電気的に接続される半導体装置であって、前記金属突起は、前記半導体素子の回路形成面に複数列となるように前記電極パッドに形成され、前記半導体素子の回路形成面の最外周に配置する金属突起の断面形状は、周縁が盛り上がった裾野を有する略山形形状である。   The semiconductor device according to claim 2, wherein a semiconductor element having a plurality of electrode pads disposed on a circuit formation surface, a plurality of electrode portions disposed on a surface opposite to the circuit formation surface of the semiconductor element, and a plurality of electrode portions disposed on an opposite surface A semiconductor device, wherein the electrode pad of the semiconductor element and the electrode portion of the substrate are electrically connected to each other via a plurality of metal protrusions and a conductive paste, respectively, The protrusions are formed on the electrode pads so as to form a plurality of rows on the circuit formation surface of the semiconductor element, and the cross-sectional shape of the metal protrusion disposed on the outermost periphery of the circuit formation surface of the semiconductor element has a base where the periphery rises. It has a substantially chevron shape.

請求項３記載の半導体装置は、請求項１または２記載の半導体装置において、前記金属突起は、周縁の盛り上がった部分が複数の段を持つ階段状になっている。   According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the metal protrusion has a stepped shape with a plurality of raised portions at the periphery.

請求項４記載の半導体装置は、請求項１，２または３記載の半導体装置において、前記金属突起の頭頂部がハンマー型である。   According to a fourth aspect of the present invention, in the semiconductor device according to the first, second, or third aspect, the top of the metal protrusion is a hammer type.

請求項５記載の半導体装置の製造方法は、半導体素子の回路形成面に配置した複数の電極パッドに金属突起を形成する工程と、前記金属突起を平坦化する工程と、導電性ペーストを前記金属突起に転写する工程と、複数の電極部を有し、前記電極部と反対側の面に複数の外部端子を有した基板を準備する工程と、前記基板の複数の電極部に前記半導体素子の金属突起と導電性ペーストを加熱硬化し接合する工程と、前記半導体素子の回路形成面と前記基板の電極部側の面との間にアンダーフィルを注入する工程と、前記アンダーフィルを加熱硬化する工程とを含み、前記金属突起を形成する際、同一キャピラリで凸型の金属突起と、周縁が盛り上がった裾野を有する略山形形状の金属突起とを形成する。   6. The method of manufacturing a semiconductor device according to claim 5, wherein a metal protrusion is formed on a plurality of electrode pads arranged on a circuit formation surface of a semiconductor element, the metal protrusion is flattened, and a conductive paste is applied to the metal. A step of transferring to the protrusion, a step of preparing a substrate having a plurality of electrode portions and having a plurality of external terminals on a surface opposite to the electrode portions, and a plurality of electrode portions of the substrate on the semiconductor element. A step of heat-curing and bonding the metal protrusion and the conductive paste, a step of injecting an underfill between the circuit formation surface of the semiconductor element and the surface of the substrate on the electrode portion side, and heat-curing the underfill. And forming the metal protrusions, a convex metal protrusion and a substantially chevron-shaped metal protrusion having a base with a raised peripheral edge are formed in the same capillary.

請求項６記載の半導体装置の製造方法は、半導体素子の回路形成面に配置した複数の電極パッドに金属突起を形成する工程と、前記金属突起を平坦化する工程と、導電性ペーストを前記金属突起に転写する工程と、複数の電極部を有し、前記電極部と反対側の面に複数の外部端子を有した基板を準備する工程と、前記基板の複数の電極部に前記半導体素子の金属突起と導電性ペーストを加熱硬化し接合する工程と、前記半導体素子の回路形成面と前記基板の電極部側の面との間にアンダーフィルを注入する工程と、前記アンダーフィルを加熱硬化する工程とを含み、前記金属突起を形成する際、周縁が盛り上がった裾野を有する略山形形状で、盛り上がった部分の段数が違う複数の金属突起を同一キャピラリで形成する。   7. The method of manufacturing a semiconductor device according to claim 6, wherein a metal protrusion is formed on a plurality of electrode pads arranged on a circuit formation surface of a semiconductor element, the metal protrusion is flattened, and a conductive paste is applied to the metal paste. A step of transferring to the protrusion, a step of preparing a substrate having a plurality of electrode portions and having a plurality of external terminals on a surface opposite to the electrode portions, and a plurality of electrode portions of the substrate on the semiconductor element. A step of heat-curing and bonding the metal protrusion and the conductive paste, a step of injecting an underfill between the circuit formation surface of the semiconductor element and the surface of the substrate on the electrode portion side, and heat-curing the underfill. A plurality of metal protrusions having a substantially chevron shape having a skirt with a raised rim, and having different numbers of raised portions, are formed with the same capillary.

請求項７記載の半導体装置の製造方法は、請求項５または６記載の半導体装置の製造方法において、前記金属突起を平坦化する工程において、前記略山形形状の金属突起の頭頂部がハンマー型となるように平坦化する。   The method of manufacturing a semiconductor device according to claim 7 is the method of manufacturing a semiconductor device according to claim 5 or 6, wherein the top of the substantially chevron-shaped metal protrusion is a hammer type in the step of planarizing the metal protrusion. It flattens so that it may become.

請求項８記載の半導体装置の製造方法は、請求項５，６または７記載の半導体装置の製造方法において、前記キャピラリは、先端の外周に段付き部分を有し、略山形形状の金属突起の周縁の盛り上がった部分を前記段付き部分によって形成する。   The method for manufacturing a semiconductor device according to claim 8 is the method for manufacturing a semiconductor device according to claim 5, 6 or 7, wherein the capillary has a stepped portion on the outer periphery of the tip, and is formed of a substantially chevron-shaped metal protrusion. A raised portion at the periphery is formed by the stepped portion.

請求項９記載の半導体装置の製造方法は、請求項５または７記載の半導体装置の製造方法において、前記略山形形状の金属突起の頭頂部はハンマー型であり、前記導電性ペーストを前記金属突起に転写する工程において、前記頭頂部の大きさを変化させることによって前記導電性ペーストの転写量を変化させる。   The method for manufacturing a semiconductor device according to claim 9 is the method for manufacturing a semiconductor device according to claim 5 or 7, wherein a top of the substantially chevron-shaped metal protrusion is a hammer type, and the conductive paste is used as the metal protrusion. In the transferring step, the transfer amount of the conductive paste is changed by changing the size of the top of the head.

この発明の請求項１記載の半導体装置によれば、金属突起は、半導体素子の回路形成面に複数列となるように電極パッドに形成され、半導体素子の回路形成面の中央領域に配置する金属突起の断面形状は、周縁が盛り上がった裾野を有する略山形形状であるので、金属突起の台部の外周部の盛り上がった部分が壁になり、その壁の側面の部分によって金属突起と導電性ペーストとの接着面積が増えるので、凸型金属突起より多くの導電性ペーストを金属突起に積むことができる。このように、多くの導電性ペーストを金属突起に積むことができるので、導電性ペーストと基板の電極パッドとの接着面積を大きくすることができ、凹型に基板が反る場合、基板の反り量の大きい位置に対応する半導体素子の中央領域でのオープン不良を防ぐことができる。また、台部の外周部の壁の部分が導電性ペーストの広がりを抑えるので、導電性ペーストが金属突起の台部よりこぼれることを防ぐことができる。このため、導電性ペーストが隣の金属突起等に接触しショート不良が起こることを防ぐことができる。この発明により、多ピン化に対応した半導体素子の電極パッドがエリアパッド配置の場合に半導体素子を基板にフリップチップ実装することが可能になる。   According to the first aspect of the present invention, the metal protrusion is formed on the electrode pad so as to form a plurality of rows on the circuit formation surface of the semiconductor element, and is disposed in the central region of the circuit formation surface of the semiconductor element. Since the cross-sectional shape of the protrusion is a substantially chevron shape with a skirt with a raised peripheral edge, the raised portion of the outer peripheral portion of the base portion of the metal protrusion becomes a wall, and the metal protrusion and the conductive paste are formed by the side portion of the wall. Therefore, more conductive paste can be stacked on the metal protrusion than the convex metal protrusion. As described above, since a large amount of conductive paste can be stacked on the metal protrusion, the adhesion area between the conductive paste and the electrode pad of the substrate can be increased, and when the substrate warps in a concave shape, the amount of warpage of the substrate An open defect in the central region of the semiconductor element corresponding to a large position can be prevented. Moreover, since the part of the wall of the outer peripheral part of a base part suppresses the spreading of a conductive paste, it can prevent that a conductive paste spills from the base part of a metal protrusion. For this reason, it can prevent that a conductive paste contacts an adjacent metal protrusion etc. and a short circuit defect arises. According to the present invention, when the electrode pad of the semiconductor element corresponding to the increase in the number of pins is an area pad arrangement, the semiconductor element can be flip-chip mounted on the substrate.

この発明の請求項２記載の半導体装置によれば、金属突起は、半導体素子の回路形成面に複数列となるように電極パッドに形成され、半導体素子の回路形成面の最外周に配置する金属突起の断面形状は、周縁が盛り上がった裾野を有する略山形形状であるので、金属突起の台部の外周部の盛り上がった部分が壁になり、その壁の側面の部分によって金属突起と導電性ペーストとの接着面積が増える。このため、同様に金属突起に導電性ペーストを多く積むことができるので、凸型に基板が反る場合、基板の反り量の多い位置に対応する半導体素子の最外周の電極パッドでのオープン不良を防ぐことができる。また、同様に台部の外周部の壁の部分が導電性ペーストの広がりを抑えるので、導電性ペーストが金属突起の台部よりこぼれることを防ぐことができる。このため、導電性ペーストが隣の金属突起等に接触しショート不良が起こることを防ぐことができる。この発明により、多ピン化に対応した半導体素子の電極パッドがエリアパッド配置の場合に半導体素子を基板にフリップチップ実装することが可能になる。   According to a second aspect of the present invention, the metal protrusion is formed on the electrode pad so as to form a plurality of rows on the circuit formation surface of the semiconductor element, and is disposed on the outermost periphery of the circuit formation surface of the semiconductor element. Since the cross-sectional shape of the protrusion is a substantially chevron shape with a skirt with a raised peripheral edge, the raised portion of the outer peripheral portion of the base portion of the metal protrusion becomes a wall, and the metal protrusion and the conductive paste are formed by the side portion of the wall. And the adhesion area increases. For this reason, a large amount of conductive paste can be stacked on the metal protrusions as well, so that when the substrate warps in a convex shape, an open failure at the outermost electrode pad of the semiconductor element corresponding to the position where the amount of warpage of the substrate is large Can be prevented. Similarly, since the wall portion of the outer peripheral portion of the base portion suppresses the spreading of the conductive paste, the conductive paste can be prevented from spilling from the base portion of the metal protrusion. For this reason, it can prevent that a conductive paste contacts an adjacent metal protrusion etc. and a short circuit defect arises. According to the present invention, when the electrode pad of the semiconductor element corresponding to the increase in the number of pins is an area pad arrangement, the semiconductor element can be flip-chip mounted on the substrate.

請求項３では、金属突起は、周縁の盛り上がった部分が複数の段を持つ階段状になっているので、段の部分は裾野の最外の壁より内側の部分で、金属突起の台部より高くなり、その分同じ導電性ペーストが転写されても導電性ペーストが高く積まれることになる。また、段の部分は最外の壁の内側であるので、その段の上に導電性ペーストが積まれても、導電性ペーストの広がりを抑える効果も残る。段の数や高さを変えることで金属突起に積む導電性ペーストの高さを調整することができる。これにより、基板の電極パッドと導電性ペーストの接着面積が大きくなり、接着強度が増し、しかも導電性ペーストの広がりを抑える壁として役割も残るので、略山形形状の金属突起の裾野の周縁の盛り上がった部分が複数の段を持つ形状にすることにより、複数の段を持つ形状にしない場合に比べショート不良に対する信頼性を損なうことなくオープン不良に対する信頼性を増すことができる。   In claim 3, since the metal protrusion has a stepped shape with a plurality of steps at the peripheral edge, the step portion is a portion on the inner side of the outermost wall of the skirt, from the base portion of the metal protrusion. Therefore, even if the same conductive paste is transferred, the conductive paste is stacked high. Further, since the step portion is inside the outermost wall, even if the conductive paste is stacked on the step, the effect of suppressing the spread of the conductive paste remains. The height of the conductive paste stacked on the metal protrusion can be adjusted by changing the number and height of the steps. This increases the bonding area between the electrode pad of the substrate and the conductive paste, increases the bonding strength, and also serves as a wall that suppresses the spread of the conductive paste. By forming the portion having a plurality of steps, the reliability with respect to the open defect can be increased without impairing the reliability with respect to the short defect as compared with the case without the shape having the plurality of steps.

請求項４では、金属突起の頭頂部がハンマー型であるので、頭頂部の平坦化された部分の面積が大きくなり、金属突起と導電性ペーストとの接着面積が大きくなるとともに、金属突起の頭頂部という高い位置に導電性ペーストが多く転写されるので、導電性ペーストを高く積むことができる。これにより、基板の電極パッドと導電性ペーストの接着面積が増し、接着強度が増すので、略山形形状の金属突起の頭頂部をハンマー型にすることで、ハンマー型にしない場合に比べオープン不良に対する信頼性を増すことができる。さらに金属突起と導電性ペーストとの接着面積が、金属突起の頭頂部という基板と導電性ペーストの接着面に近い部分で大きくなることにより、導電性が良くなるという効果もある。   In claim 4, since the top of the metal protrusion is a hammer type, the area of the flattened portion of the top of the head is increased, the adhesion area between the metal protrusion and the conductive paste is increased, and the head of the metal protrusion is increased. Since a large amount of conductive paste is transferred to a high position such as the top, the conductive paste can be stacked high. This increases the bonding area between the electrode pad of the substrate and the conductive paste and increases the bonding strength. By making the top of the substantially chevron-shaped metal protrusion a hammer type, it is more resistant to open defects than not using a hammer type. Reliability can be increased. Further, the adhesion area between the metal protrusion and the conductive paste is increased at a portion near the bonding surface between the substrate and the conductive paste, that is, the top of the metal protrusion, so that the conductivity is improved.

この発明の請求項５記載の半導体装置の製造方法によれば、金属突起を形成する際、同一キャピラリで凸型の金属突起と、周縁が盛り上がった裾野を有する略山形形状の金属突起とを形成するので、1本のキャピラリで基板の反りの大きい部分は略山形形状の金属突起を形成し、基板の反りの小さい部分は凸型の金属突起を形成した半導体装置を製造することができる。また、基板の反り量の小さい部分では従来の凸型金属突起でオープン不良に対する信頼性は問題なく、またこれによって、基板と金属突起の間隔が狭くなる基板の反り量の小さい部分の金属突起に積む導電性ペーストの量が、基板と金属突起の間隔が広くなる基板の反り量の大きい部分に積む導電性ペーストの量に比べて少なくなるので、導電性ペーストが金属突起の台部からこぼれることを防ぐことができる。この場合、凸型の金属突起の形状を形成するのは、キャピラリ先端の平坦部なので、キャピラリの外形によらずキャピラリ先端の平坦部の大きさが十分であれば、凸型の金属突起を形成することができる。よって、先端に平坦部を有し、側周面の部分に段差をつけたキャピラリを用いることにより、1本のキャピラリで凸型の金属突起も形成でき、裾野の周縁が盛り上がった形状の略山形形状の金属突起も形成すことができる。この発明により、多ピン化に対応した半導体素子の電極パッドがエリアパッド配置の場合に半導体素子を基板にフリップチップ実装することが可能になり、1本のキャピラリで製造できるので量産にも対応できる。   According to the method for manufacturing a semiconductor device according to claim 5 of the present invention, when forming the metal protrusion, a convex metal protrusion and a substantially chevron-shaped metal protrusion having a skirt with a raised peripheral edge are formed in the same capillary. Therefore, it is possible to manufacture a semiconductor device in which a portion having a large warp of a substrate forms a substantially chevron-shaped metal protrusion and a portion having a small warp of the substrate has a convex metal protrusion. In addition, in the portion where the warpage amount of the substrate is small, there is no problem with the reliability with respect to the open defect due to the conventional convex metal protrusion, and as a result, the distance between the substrate and the metal protrusion becomes narrow and the metal protrusion in the portion where the warpage amount of the substrate is small is reduced. The amount of conductive paste that accumulates is less than the amount of conductive paste that accumulates on the large warped portion of the substrate where the distance between the substrate and the metal protrusion is wide, so that the conductive paste spills from the base portion of the metal protrusion. Can be prevented. In this case, since the shape of the convex metal protrusion is the flat part at the capillary tip, the convex metal protrusion is formed if the size of the flat part at the capillary tip is sufficient regardless of the outer shape of the capillary. can do. Therefore, by using a capillary with a flat part at the tip and a step on the side peripheral surface, it is possible to form convex metal protrusions with a single capillary, and a substantially chevron shape with a raised rim at the base Shaped metal protrusions can also be formed. According to the present invention, when an electrode pad of a semiconductor element corresponding to the increase in the number of pins is an area pad arrangement, the semiconductor element can be flip-chip mounted on a substrate, and can be manufactured with a single capillary, so that it can cope with mass production. .

この発明の請求項６記載の半導体装置の製造方法によれば、金属突起を形成する際、周縁が盛り上がった裾野を有する略山形形状で、盛り上がった部分の段数が違う複数の金属突起を同一キャピラリで形成するので、1本のキャピラリで基板の反りの大きい部分に、多くかつ高く導電性ペーストを積むことができる段数の多い略山形形状の金属突起を形成した半導体装置を製造することができ、同様にオープン不良やショート不良に対する信頼性を上げることができる。この場合、側周面につける段差を複数にしたキャピラリを用いることにより、裾野の周縁の盛り上がった部分の段差の数が違う略山形形状の複数の金属突起を１本のキャピラリで形成することができる。この発明により、多ピン化に対応した半導体素子の電極パッドがエリアパッド配置の場合に半導体素子を基板にフリップチップ実装することが可能になり、1本のキャピラリで製造できるので量産にも対応できる。   According to the method of manufacturing a semiconductor device according to the sixth aspect of the present invention, when forming the metal protrusions, a plurality of metal protrusions having a substantially chevron shape having a skirt with a raised peripheral edge and having different number of steps of the raised portions are formed in the same capillary. Therefore, it is possible to manufacture a semiconductor device in which a large number of steps and a substantially chevron-shaped metal protrusion capable of stacking a large amount of conductive paste on a large warped portion of a substrate with a single capillary, Similarly, the reliability with respect to open defects and short defects can be increased. In this case, by using a capillary having a plurality of steps to be applied to the side peripheral surface, a plurality of substantially chevron-shaped metal projections having different numbers of steps at the raised portion at the periphery of the skirt can be formed by one capillary. it can. According to the present invention, when an electrode pad of a semiconductor element corresponding to the increase in the number of pins is an area pad arrangement, the semiconductor element can be flip-chip mounted on a substrate, and can be manufactured with a single capillary, so that it can cope with mass production. .

請求項７では、金属突起を平坦化する工程において、略山形形状の金属突起の頭頂部がハンマー型となるように平坦化するので、導電性ペーストの転写量を変化させ、安定したフリップチップ接続を得ることが可能となる。具体的には、金属突起の突起部は金線を引きちぎることによってできているので、突起の頭頂部は引き伸ばされており金属突起の他の部分より強度が弱くなっている。そのため、レベリング時にかける金属突起あたりの荷重を通常金属突起を平坦化する時にかける荷重より大きくすることにより、頭頂部のみを潰すことができる。これによって、略山形形状の金属突起の頭頂部がハンマー型となるように平坦化の量を大きくすることができる。   According to the seventh aspect of the present invention, in the step of flattening the metal protrusion, the top of the substantially chevron-shaped metal protrusion is flattened in a hammer shape, so that the transfer amount of the conductive paste is changed, and stable flip chip connection is achieved. Can be obtained. Specifically, since the protrusion of the metal protrusion is formed by tearing a gold wire, the top of the protrusion is stretched and has a lower strength than the other part of the metal protrusion. Therefore, only the top of the head can be crushed by making the load per metal projection applied during leveling larger than the load applied when flattening the metal projection. As a result, the amount of flattening can be increased so that the top of the substantially chevron-shaped metal projection becomes a hammer shape.

請求項８では、キャピラリは、先端の外周に段付き部分を有し、略山形形状の金属突起の周縁の盛り上がった部分を段付き部分によって形成するので、金属突起の安定した裾野の形状を得ることができる。このため、金属突起と導電性ペーストの接着面積が安定し、略山形形状の金属突起に安定した量の導電性ペーストを積むことができる。   According to the eighth aspect of the present invention, the capillary has a stepped portion on the outer periphery of the tip, and the raised portion on the periphery of the substantially chevron-shaped metal projection is formed by the stepped portion, so that a stable skirt shape of the metal projection is obtained. be able to. For this reason, the adhesion area of the metal protrusion and the conductive paste is stabilized, and a stable amount of the conductive paste can be stacked on the substantially chevron-shaped metal protrusion.

請求項９では、略山形形状の金属突起の頭頂部はハンマー型であり、導電性ペーストを金属突起に転写する工程において、頭頂部の大きさを変化させることによって導電性ペーストの転写量を変化させるので、安定したフリップチップ接続を得ることが可能となる。この場合、レベリング時にかける金属突起あたりの荷重を変化させることにより、略山形形状の金属突起の頭頂部の面積を変化させることによって、金属突起と導電性ペーストの接着面積を変化させることができ、略山形形状の金属突起に転写する導電性ペーストの量を変化させることができる。   According to the ninth aspect of the present invention, the top portion of the substantially chevron-shaped metal protrusion is a hammer type, and in the step of transferring the conductive paste to the metal protrusion, the transfer amount of the conductive paste is changed by changing the size of the top portion. Therefore, it is possible to obtain a stable flip chip connection. In this case, it is possible to change the adhesion area between the metal protrusion and the conductive paste by changing the area of the top of the substantially protrusion-shaped metal protrusion by changing the load per metal protrusion applied during leveling. The amount of the conductive paste transferred to the substantially chevron-shaped metal protrusion can be changed.

この発明の第１の実施の形態を図１〜図８に基づいて説明する。図１は本発明の第１の実施形態における半導体装置を示す断面図であり、基板が凹型に反る場合を示す。   A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention, and shows a case where a substrate warps in a concave shape.

図１に示すように、半導体素子１の回路形成面上に複数の電極パッド２が配置され、前記電極パッド２上に金属突起４が形成される。金属突起４は従来例と同様にＡｕで形成する場合について示す。基板７にも電極パッド８が形成され、半導体素子１の電極パッド２上に形成された金属突起４は金属突起４上に転写された導電性ペースト６で基板７の電極パッド８に接着されている。半導体素子１と基板７の間にはエポキシ系樹脂９が充填されている。ここで、例えば導電性ペースト６の材質はＡｇ−Ｐｄの粉末を含んだペースト状の熱硬化性樹脂からなる。また、半導体素子１の電極パッド２と基板７の電極パッド８は、複数の金属突起４と導電性ペースト６を介して各々電気的に接続される。この場合、半導体素子１の電極パッド２の最表面材質はＡｌ層で構成され、ＡｌとＡｕの合金形成により接続される。   As shown in FIG. 1, a plurality of electrode pads 2 are disposed on the circuit formation surface of the semiconductor element 1, and metal protrusions 4 are formed on the electrode pads 2. The case where the metal protrusion 4 is formed of Au as in the conventional example will be described. An electrode pad 8 is also formed on the substrate 7, and the metal protrusion 4 formed on the electrode pad 2 of the semiconductor element 1 is bonded to the electrode pad 8 of the substrate 7 with the conductive paste 6 transferred onto the metal protrusion 4. Yes. An epoxy resin 9 is filled between the semiconductor element 1 and the substrate 7. Here, for example, the material of the conductive paste 6 is made of a paste-like thermosetting resin containing Ag—Pd powder. Further, the electrode pad 2 of the semiconductor element 1 and the electrode pad 8 of the substrate 7 are electrically connected to each other via the plurality of metal protrusions 4 and the conductive paste 6. In this case, the outermost surface material of the electrode pad 2 of the semiconductor element 1 is composed of an Al layer and is connected by forming an alloy of Al and Au.

また、半導体素子１上には、基板７の反り量の小さい位置に対応する半導体素子１の最外周の電極パッド２ａには凸型金属突起４ａが形成され、基板７の反り量の大きい位置に対応する半導体素子１の中央領域の電極パッド２ｂには略山形形状の金属突起４ｃが形成されている。   On the semiconductor element 1, convex metal protrusions 4a are formed on the outermost electrode pad 2a of the semiconductor element 1 corresponding to the position where the warpage amount of the substrate 7 is small. A substantially chevron-shaped metal protrusion 4 c is formed on the electrode pad 2 b in the central region of the corresponding semiconductor element 1.

図２は本発明の第１の実施形態において基板が凹型に反る場合の半導体装置の上から見た金属突起の配置図である。線Ａ−Ａ’の図１の断面図の位置である。図２に示すように、金属突起４ａが半導体素子１の外周部に形成された金属突起となり、金属突起４ｃが半導体素子１の中央領域に形成された略山形形状の金属突起になる。   FIG. 2 is an arrangement view of metal protrusions as viewed from above the semiconductor device when the substrate warps in a concave shape in the first embodiment of the present invention. It is the position of the cross-sectional view of FIG. 1 along line A-A ′. As shown in FIG. 2, the metal protrusion 4 a becomes a metal protrusion formed on the outer periphery of the semiconductor element 1, and the metal protrusion 4 c becomes a substantially chevron-shaped metal protrusion formed in the central region of the semiconductor element 1.

図３（ａ）は、本発明の実施形態と比較するために半導体素子の外周部と半導体素子の中央領域に凸型金属突起を形成し、熱衝撃試験(Ｈ／Ｓ）を行った時の試験サイクル数と半導体素子の中央領域の凸型金属突起の接続抵抗の関係を示す図である。測定は１０チップで行っている。１００サイクルで最大値６００ｍΩと大きな値になっているが、３００サイクルで最大値１９００ｍΩと非常に大きな値になっている。これは、オープン不良である。   FIG. 3A shows a case where convex metal protrusions are formed on the outer peripheral portion of the semiconductor element and the central region of the semiconductor element and a thermal shock test (H / S) is performed for comparison with the embodiment of the present invention. It is a figure which shows the relationship between the test cycle number and the connection resistance of the convex-shaped metal protrusion of the center area | region of a semiconductor element. The measurement is performed with 10 chips. Although the maximum value is 600 mΩ at 100 cycles, the maximum value is 1900 mΩ at 300 cycles, which is a very large value. This is an open failure.

図３（ｂ）は、本発明の実施形態において半導体素子の外周部に凸型金属突起を、半導体素子の中央領域には略山形形状の金属突起を形成し、熱衝撃試験(Ｈ／Ｓ）を行った時の試験サイクル数と半導体素子の中央領域の裾野の周縁が盛り上がった形状の略山形形状の金属突起の接続抵抗の関係を示す図である。１００サイクルで最大値１４０ｍΩ、３００サイクルでも最大値１００ｍΩと小さい値になっている。よって、凸型金属突起を裾野の周縁が盛り上がった略山形形状の金属突起に変えることで接続強度が上がっていることがわかる。   FIG. 3B shows a thermal shock test (H / S) in the embodiment of the present invention, in which convex metal protrusions are formed on the outer periphery of the semiconductor element, and substantially chevron-shaped metal protrusions are formed in the central area of the semiconductor element. It is a figure which shows the connection resistance of the number of test cycles when performing, and the connection resistance of the substantially chevron-shaped metal protrusion of the shape where the periphery of the base of the center area | region of a semiconductor element rose. The maximum value is 140 mΩ at 100 cycles and the maximum value is 100 mΩ even at 300 cycles. Therefore, it can be seen that the connection strength is increased by changing the convex metal protrusion into a substantially chevron-shaped metal protrusion with a raised peripheral edge.

図４は本発明の第１の実施形態における半導体装置の断面図であり、基板が凸型に反る場合を示す。   FIG. 4 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, showing a case where the substrate warps in a convex shape.

図４に示すように、半導体素子１上には、基板７の反り量の小さい半導体素子１の中央領域の電極パッド２ｂに凸型金属突起４ｂが形成され、反り量の大きい半導体素子１の外周部の電極パッド２ａには略山形形状の金属突起４ｃが形成されている。   As shown in FIG. 4, a convex metal protrusion 4 b is formed on the electrode pad 2 b in the central region of the semiconductor element 1 with a small warpage amount of the substrate 7 on the semiconductor element 1, and the outer periphery of the semiconductor element 1 with a large warpage amount is formed. The electrode pad 2a is formed with a substantially chevron-shaped metal protrusion 4c.

図５は本発明の第１の実施形態において基板が凸型に反る場合の半導体装置上から見た金属突起の配置図である。線Ａ−Ａ’は図４の断面図の位置である。図５に示すように、金属突起４ｃが半導体素子１の外周部に形成された略山形形状の金属突起となり、金属突起４ｂが半導体素子１の中央領域に形成された金属突起になる。   FIG. 5 is a layout view of metal protrusions as seen from above the semiconductor device when the substrate is warped in the first embodiment of the present invention. Line A-A 'is the position of the cross-sectional view of FIG. As shown in FIG. 5, the metal protrusion 4 c is a substantially chevron-shaped metal protrusion formed on the outer periphery of the semiconductor element 1, and the metal protrusion 4 b is a metal protrusion formed in the central region of the semiconductor element 1.

ここで、本発明の実施形態における製造方法に用いるキャピラリの形状について図６に基づいて説明する。本実施形態のキャピラリ３ａの形状は図６（ａ）で示すように、先端部３１は平坦であり、側周面に段差３３を有した円錐形状である。この段差３３により、金属突起４の台部の外周に安定した高さの壁４５を形成することができる。キャピラリ３ａの軸心には金線など金属ワイヤ４１の通るキャピラリホール３２が設けられている。また前記金属ワイヤ４１の材質は一例を挙げると、９９．９９％以上の金（Ａｕ）より構成され、金属ワイヤ４１の線径はφ１８μｍから３０μｍ程度である。   Here, the shape of the capillary used in the manufacturing method according to the embodiment of the present invention will be described with reference to FIG. As shown in FIG. 6A, the shape of the capillary 3a of the present embodiment is a conical shape having a flat tip 31 and a step 33 on the side peripheral surface. Due to the step 33, the wall 45 having a stable height can be formed on the outer periphery of the base portion of the metal protrusion 4. A capillary hole 32 through which a metal wire 41 such as a gold wire passes is provided at the axial center of the capillary 3a. For example, the material of the metal wire 41 is composed of 99.99% or more of gold (Au), and the wire diameter of the metal wire 41 is about φ18 μm to 30 μm.

このキャピラリ３ａにより形成される裾野の周縁が盛り上がった形状の略山形形状の金属突起４ｃの形状について説明する。本実施形態の略山形形状の金属突起４ｃは環状の形状をしており、図６（ｃ）に示すように中心が突き出て、その周囲が平らな台４３になっており、その台４３の外周は壁４５になっている。この壁の高さｈ１は、図６（ｂ）に示すようにキャピラリ３ａの段差の大きさｈ２で変化させることができる。   The shape of the substantially chevron-shaped metal protrusion 4c having a shape in which the peripheral edge of the base formed by the capillary 3a is raised will be described. The substantially chevron-shaped metal protrusion 4c of the present embodiment has an annular shape, and the center protrudes as shown in FIG. The outer periphery is a wall 45. The height h1 of the wall can be changed by the step size h2 of the capillary 3a as shown in FIG. 6 (b).

次に図６および図７を用いて本発明の第１の実施形態の半導体装置の製造方法を説明する。本発明の第１の実施形態の形成方法は、背景技術において説明した形成方法とほぼ同じであるので、相違点のみ詳しく説明する。   Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. Since the forming method of the first embodiment of the present invention is almost the same as the forming method described in the background art, only the differences will be described in detail.

図１に示すように基板７が凹型に反る場合、基板７の反り量の小さい半導体素子の外周部の電極パッド２ａにはキャピラリ３ａにより凸型の金属突起４ａを形成する。その形成方法は背景技術で説明した方法と同じで、図７（ａ）で示すようにキャピラリホール３２より金属ワイヤ４１を出し、金属ワイヤ４１の先端を放電等で融解させ、球状のＡｕボール４２を形成する。図７（ｂ）で示すようにＡｕボール４２は半導体素子１の電極２に、超音波振動を加えながら圧着される。キャピラリ３ａを上に引き上げ、金属ワイヤ４１を引きちぎるという方法である。図７（ｃ）は、形成された凸型金属突起４ａである。   As shown in FIG. 1, when the substrate 7 warps in a concave shape, a convex metal protrusion 4a is formed by the capillary 3a on the electrode pad 2a on the outer periphery of the semiconductor element having a small warpage amount. The formation method is the same as the method described in the background art. As shown in FIG. 7A, the metal wire 41 is taken out from the capillary hole 32, the tip of the metal wire 41 is melted by discharge or the like, and a spherical Au ball 42 is formed. Form. As shown in FIG. 7B, the Au ball 42 is pressure-bonded to the electrode 2 of the semiconductor element 1 while applying ultrasonic vibration. This is a method of pulling up the capillary 3 a and tearing the metal wire 41. FIG. 7C shows the formed convex metal protrusion 4a.

基板7の反り量の大きい半導体素子中央部の電極パッド２ｂには、図６（ａ）で示すようにキャピラリ先端部３１の外周径より金属突起の外周径が大きくなるように、金属ワイヤ４１の先端を融解させるための放電時間を長くする等で形成するＡｕボール４１を大きくする。さらにＡｕボール４１に与える荷重と超音波振動を大きくし、図６（ｂ）で示すようにＡｕボールを圧着し略山形形状の金属突起４ｃを形成する。図６（ｃ）は、形成された略山形形状の金属突起４ｃである。   The electrode pad 2b in the central portion of the semiconductor element having a large amount of warpage of the substrate 7 has a metal wire 41 so that the outer peripheral diameter of the metal protrusion is larger than the outer peripheral diameter of the capillary tip 31 as shown in FIG. The Au ball 41 to be formed is enlarged by increasing the discharge time for melting the tip. Further, the load and the ultrasonic vibration applied to the Au ball 41 are increased, and the Au ball is pressure-bonded as shown in FIG. 6B to form a substantially chevron-shaped metal protrusion 4c. FIG. 6C shows a substantially chevron-shaped metal protrusion 4 c formed.

このように、1本のキャピラリで、図８（ａ）に示すような凸型の金属突起４ａと略山形形状の金属突起４ｃを形成することができる。この後の形成方法は、背景技術で説明した方法と同じで、図８（ｂ）で示すように金属突起の先端部４４にレベリングツール５で一定の荷重を加えレベリングを行い、金属突起４の高さを均一にする。この金属突起４にレベリング時に加える荷重は金属突起あたり、１５ｇｆから２５ｇｆである。図8（ｃ）で示すように金属突起４の形成面を下側にし、金属突起４を導電性ペースト６に浸漬させ、表面張力により導電性ペースト６を転写する。図８（ｄ）に示すように金属突起４を基板７の電極パッド８に圧着し、導電性ペースト６を加熱により硬化させる。図８（ｅ）に示すように半導体素子１の回路形成面と基板７の電極面側間にアンダーフィルと呼ばれるエポキシ樹脂等９を充填する。図８（ｆ）に示すように加熱硬化させ封止する。   Thus, with one capillary, the convex metal protrusion 4a and the substantially chevron-shaped metal protrusion 4c as shown in FIG. 8A can be formed. The subsequent forming method is the same as the method described in the background art. As shown in FIG. 8B, the metal protrusion 4 is leveled by applying a constant load to the tip 44 of the metal protrusion with the leveling tool 5. Make the height uniform. The load applied to the metal protrusion 4 during leveling is 15 gf to 25 gf per metal protrusion. As shown in FIG. 8C, the metal protrusion 4 is formed on the lower side, the metal protrusion 4 is immersed in the conductive paste 6, and the conductive paste 6 is transferred by surface tension. As shown in FIG. 8 (d), the metal protrusion 4 is pressure-bonded to the electrode pad 8 of the substrate 7, and the conductive paste 6 is cured by heating. As shown in FIG. 8E, an epoxy resin or the like 9 called an underfill is filled between the circuit formation surface of the semiconductor element 1 and the electrode surface side of the substrate 7. As shown in FIG. 8 (f), it is heat-cured and sealed.

基板７が凸型に反る場合は、半導体素子の中央領域は基板の反り量が小さくなるので凸型の金属突起４ｂを形成し、半導体素子の外周部は反り量が大きくなるので略山形形状の金属突起４ｃを形成する点以外は形成方法が、基板７が凹型に反る場合と同じである。   When the substrate 7 warps in a convex shape, the warp amount of the substrate is small in the central region of the semiconductor element, so that the convex metal protrusion 4b is formed, and the outer peripheral portion of the semiconductor element has a large warp amount, so The formation method is the same as the case where the substrate 7 warps in a concave shape except that the metal protrusion 4c is formed.

この発明の第２の実施の形態を図９〜図１１に基づいて説明する。図９は本発明の第２の実施形態における半導体装置を示す断面図である。図１０は、第２の実施形態におけるキャピラリの形状を示す図である。   A second embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a cross-sectional view showing a semiconductor device according to the second embodiment of the present invention. FIG. 10 is a diagram showing the shape of the capillary in the second embodiment.

図９に示すように第２の実施形態は、第１の実施形態の略山形形状の金属突起４ｃを、裾野の周縁の盛り上がった部分に複数の段４５ａが形成された略山形形状の金属突起４ｅに変えたものである。よって、裾野の周縁の盛り上がった部分に複数の段４５ａが形成された略山形形状の金属突起４ｅとその製造に方法以外は、形状、製造方法ともに第１の実施形態と同じなので、裾野の周縁の盛り上がった部分に複数の段４５ａが形成された略山形形状の金属突起４ｅの形状と製造方法について図１０および図１１を用いて説明する。   As shown in FIG. 9, in the second embodiment, the substantially chevron-shaped metal protrusion 4c of the first embodiment is substantially the same as the substantially chevron-shaped metal protrusion in which a plurality of steps 45a are formed on the raised portion of the periphery of the skirt. It is changed to 4e. Accordingly, the shape and the manufacturing method are the same as those of the first embodiment except for the substantially chevron-shaped metal protrusion 4e in which a plurality of steps 45a are formed on the raised portion of the periphery of the skirt and the method of manufacturing the metal protrusion 4e. The shape and manufacturing method of the substantially chevron-shaped metal protrusion 4e in which a plurality of steps 45a are formed in the raised portion will be described with reference to FIGS.

図１０（ｂ）に示すように、裾野の周縁の盛り上がった部分に複数の段４５ａを持った略山形形状の金属突起４ｅは環状の形状になっており、中心に突起があり、その突起の周囲が平らな台４３になっており、その台４３の外周は壁４５になっており、この壁４５に複数の段４５ａを持っている。   As shown in FIG. 10 (b), a substantially chevron shaped metal protrusion 4e having a plurality of steps 45a at the raised portion of the periphery of the skirt has an annular shape, and has a protrusion at the center. The periphery is a flat base 43, and the outer periphery of the base 43 is a wall 45. The wall 45 has a plurality of steps 45a.

次に、図１０（ａ）で示すように本実施形態の製造方法に用いるキャピラリ３ｂの形状は、先端部３１は平坦であり、側周面に複数の段差３３ａを有した円錐形状である。この複数の段差３３ａにより、金属突起４ｅの台部の外周に複数の段４５ａを持った壁４５を形成することができる。キャピラリ３ｂの軸心には金線など金属ワイヤの通るキャピラリホール３２が設けられている。また前記金属ワイヤ４１の材質は一例を挙げると、９９．９９％以上の金（Ａｕ）より構成され、金属ワイヤ４１の線径はφ１８μｍから３０μｍ程度である。このキャピラリを用いた第２の実施形態の略山形形状の金属突起の製造方法は、第1の実施形態の略山形形状の金属突起の製造方法とほぼ同じである。キャピラリホール３２より金属ワイヤ４１を出し、金属ワイヤ４１の先端を放電等で融解させ、球状のＡｕボール４２を形成する。Ａｕボール４２は半導体素子１の電極２に、超音波振動を加えながら圧着される。キャピラリ３ｂを上に引き上げ、金属ワイヤ４１を引きちぎるという方法である。このとき放電時間を変えるなどで形成するＡｕボール４２の大きさを変えることで、図１１（ａ）に示すような凸型の金属突起４ａ、図１１（ｂ）に示すような裾野の周縁の盛り上がった部分が1段の略山形形状の金属突起４ｃ、図１０（ｂ）で示すような裾野の周縁の盛り上がった部分が2段以上の複数の略山形形状の金属突起４ｅを1本のキャピラリで形成することができる。   Next, as shown in FIG. 10A, the shape of the capillary 3b used in the manufacturing method of the present embodiment is a conical shape in which the tip portion 31 is flat and the side peripheral surface has a plurality of steps 33a. By the plurality of steps 33a, a wall 45 having a plurality of steps 45a on the outer periphery of the base portion of the metal protrusion 4e can be formed. A capillary hole 32 through which a metal wire such as a gold wire passes is provided at the axial center of the capillary 3b. For example, the material of the metal wire 41 is composed of 99.99% or more of gold (Au), and the wire diameter of the metal wire 41 is about φ18 μm to 30 μm. The manufacturing method of the substantially chevron-shaped metal protrusion of the second embodiment using this capillary is substantially the same as the manufacturing method of the approximately chevron-shaped metal protrusion of the first embodiment. A metal wire 41 is taken out from the capillary hole 32, and the tip of the metal wire 41 is melted by electric discharge or the like to form a spherical Au ball. The Au ball 42 is pressed against the electrode 2 of the semiconductor element 1 while applying ultrasonic vibration. In this method, the capillary 3b is pulled up and the metal wire 41 is torn off. At this time, by changing the size of the Au ball 42 to be formed by changing the discharge time, the convex metal protrusion 4a as shown in FIG. 11 (a) and the peripheral edge of the skirt as shown in FIG. 11 (b) are obtained. The raised portion has one step of an approximately chevron-shaped metal projection 4c, and the raised portion at the periphery of the skirt as shown in FIG. 10 (b) has a plurality of approximately chevron-shaped metal projections 4e having a single capillary. Can be formed.

この発明の第３の実施の形態を図１２〜図１４に基づいて説明する。図１２は本発明の第３の実施形態の基板が凹型に反る場合の断面図、図１３は本発明の第３の実施形態の基板が凸型に反る場合の断面図である。   A third embodiment of the present invention will be described with reference to FIGS. FIG. 12 is a cross-sectional view when the substrate according to the third embodiment of the present invention warps in a concave shape, and FIG. 13 is a cross-sectional view when the substrate according to the third embodiment of the present invention warps in a convex shape.

図１２、図1３に示すように第３の実施形態は、第１の実施形態の略山形形状の金属突起または、第１の実施形態または第２の実施形態（図は第１の実施形態）の略山形形状の金属突起の頭頂部をつぶしてハンマー型４ｄにしたものである。よって、略山形形状の金属突起の頭頂部をハンマー型に変えた以外は形状、製造方法とも第１の実施形態または第２の実施形態と同じなので、頭頂部がハンマー型の略山形形状の金属突起の形状とその製造方法について説明する。   As shown in FIG. 12 and FIG. 13, the third embodiment is a metal projection having a substantially chevron shape of the first embodiment, or the first embodiment or the second embodiment (the figure is the first embodiment). The crest of the substantially chevron shaped metal projection is crushed into a hammer type 4d. Therefore, the shape and the manufacturing method are the same as those in the first embodiment or the second embodiment except that the head portion of the substantially chevron-shaped metal protrusion is changed to the hammer shape, so that the head portion is a hammer-shaped substantially chevron-shaped metal. The shape of the protrusion and the manufacturing method thereof will be described.

図１４（ａ）は略山形形状の金属突起の断面図であり、（ｄ）はその上から見た図である。図１４（ｃ）は頭頂部がハンマー型の金属突起の断面図であり、図１４（ｅ）はその上から見た図である。図１４（ｃ）、（ｅ）で示すように頭頂部がハンマー型の金属突起４ｄは環状の形状になっており、中心に突起４６があり、その突起４６の頭頂部４４がつぶされ環状の平坦部４７が形成され、その突起４６の周囲が平らな台４３になっており、その台４３の外周は壁４５になっている。この金属突起の頭頂部の平坦部４７は、略山形形状の金属突起４ｃの突起４６に比べて大きくなっている。   FIG. 14A is a cross-sectional view of a substantially chevron-shaped metal protrusion, and FIG. 14D is a view seen from above. FIG. 14C is a cross-sectional view of a metal protrusion whose top is a hammer type, and FIG. 14E is a view from above. As shown in FIGS. 14 (c) and 14 (e), the hammer-shaped metal protrusion 4d has an annular shape with a protrusion 46 at the center, and the vertex 44 of the protrusion 46 is crushed and has an annular shape. A flat portion 47 is formed, and the periphery of the protrusion 46 is a flat base 43, and the outer periphery of the base 43 is a wall 45. The flat portion 47 at the top of the metal protrusion is larger than the protrusion 46 of the substantially chevron-shaped metal protrusion 4c.

次に、頭頂部がハンマー型の略山形形状の金属突起４ｄの製造方法については、図１４（ａ）、（ｂ）で示すように高強度の金属ワイヤで形成された山形金属突起４ｃのレベリング時に、レベリングツール５で与える荷重を従来のレベリング時に比べ大きくすることで、頭頂部をつぶしハンマー型にする。   Next, regarding the manufacturing method of the metal protrusion 4d having a hammer-shaped substantially chevron shape, the leveling of the chevron metal protrusion 4c formed of a high-strength metal wire as shown in FIGS. 14 (a) and 14 (b). Occasionally, the load applied by the leveling tool 5 is increased as compared with the conventional leveling to crush the top of the head into a hammer type.

略山形形状の金属突起４ｃの頭頂部をつぶしハンマー型にする効果として、ハンマー型の大きさを変化させる事によって導電性ペーストの転写量を変化させ、安定したフリップチップ接続を得ることが可能となる。   As an effect of crushing the top of the metal protrusion 4c having a substantially chevron shape into a hammer shape, it is possible to change the transfer amount of the conductive paste by changing the size of the hammer shape and obtain a stable flip chip connection. Become.

本発明にかかる半導体装置およびその製造方法は、半導体素子の電極パッドがエリアパッド配置の場合に半導体素子を基板にフリップチップ実装することが可能になり、1本のキャピラリで製造できるので、多ピン化に対応した半導体装置とその量産方法に対して有用である。   In the semiconductor device and the manufacturing method thereof according to the present invention, when the electrode pad of the semiconductor element is an area pad arrangement, the semiconductor element can be flip-chip mounted on the substrate, and can be manufactured with one capillary. This is useful for a semiconductor device and its mass production method.

本発明の第１の実施形態にかかる半導体装置の断面図である。1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施形態にかかる半導体装置の金属突起のエリアパッド配置を示す平面図である。It is a top view which shows area pad arrangement | positioning of the metal protrusion of the semiconductor device concerning the 1st Embodiment of this invention. （ａ）はエリア配置された凸型金属突起において、熱衝撃試験(Ｈ／Ｓ）を行った時の試験サイクル数と接続抵抗の関係を示す図、（ｂ）はエリア配置された略山形形状の金属突起において、熱衝撃試験(Ｈ／Ｓ）を行った時の試験サイクル数と接続抵抗の関係を示す図である。(A) is a diagram showing the relationship between the number of test cycles and connection resistance when a thermal shock test (H / S) is performed on convex metal protrusions arranged in an area, and (b) is a substantially chevron shape arranged in an area. It is a figure which shows the relationship between the number of test cycles when a thermal shock test (H / S) is performed, and connection resistance in metal protrusions. 本発明の第１の実施形態にかかる半導体装置の他の例の断面図である。It is sectional drawing of the other example of the semiconductor device concerning the 1st Embodiment of this invention. 本発明の第１の実施形態にかかる半導体装置の他の例の金属突起のエリアパッド配置を示す平面図である。It is a top view which shows area pad arrangement | positioning of the metal protrusion of the other example of the semiconductor device concerning the 1st Embodiment of this invention. 本発明の第１の実施形態にかかる半導体装置の金属突起の製造方法と製造にかかわるキャピラリの断面図である。It is sectional drawing of the capillary in connection with the manufacturing method of metal protrusion of the semiconductor device concerning the 1st Embodiment of this invention, and manufacture. 本発明の第１の実施形態にかかる半導体装置の金属突起の製造方法と製造にかかわるキャピラリの断面図である。It is sectional drawing of the capillary in connection with the manufacturing method of metal protrusion of the semiconductor device concerning the 1st Embodiment of this invention, and manufacture. 本発明の第１の実施形態にかかる半導体装置のフリップチップ実装工法を示す工程断面図である。It is process sectional drawing which shows the flip-chip mounting method of the semiconductor device concerning the 1st Embodiment of this invention. 本発明の第２の実施形態にかかる半導体装置の断面図である。It is sectional drawing of the semiconductor device concerning the 2nd Embodiment of this invention. 本発明の第２の実施形態にかかる半導体装置の金属突起の製造方法と製造にかかわるキャピラリの断面図である。It is sectional drawing of the capillary in connection with the manufacturing method of metal protrusion of the semiconductor device concerning the 2nd Embodiment of this invention, and manufacture. 本発明の第２の実施形態にかかる半導体装置の金属突起の製造方法と製造にかかわるキャピラリの断面図である。It is sectional drawing of the capillary in connection with the manufacturing method of metal protrusion of the semiconductor device concerning the 2nd Embodiment of this invention, and manufacture. 本発明の第３の実施形態にかかる半導体装置の断面図である。It is sectional drawing of the semiconductor device concerning the 3rd Embodiment of this invention. 本発明の第３の実施形態にかかる半導体装置の他の例の断面図である。It is sectional drawing of the other example of the semiconductor device concerning the 3rd Embodiment of this invention. （ａ）〜（ｃ）は本発明の第３の実施形態にかかる半導体装置の金属突起の製造方法を示す断面図、（ｄ）、（ｅ）は金属突起の平面図である。(A)-(c) is sectional drawing which shows the manufacturing method of the metal protrusion of the semiconductor device concerning the 3rd Embodiment of this invention, (d), (e) is a top view of a metal protrusion. 従来の半導体装置の金属突起の製造方法と製造にかかわるキャピラリの断面図である。It is sectional drawing of the capillary in connection with the manufacturing method of metal protrusion of the conventional semiconductor device, and manufacture. 従来の半導体装置のフリップチップ実装工法を示す工程断面図である。It is process sectional drawing which shows the flip-chip mounting method of the conventional semiconductor device. 従来のエリアパッド配置の半導体装置の断面図である。It is sectional drawing of the semiconductor device of the conventional area pad arrangement | positioning. 従来のエリアパッド配置の半導体装置の金属突起の配置を示す平面図である。It is a top view which shows arrangement | positioning of the metal protrusion of the semiconductor device of the conventional area pad arrangement | positioning. 従来のエリアパッド配置の半導体装置の断面図である。It is sectional drawing of the semiconductor device of the conventional area pad arrangement | positioning. 従来のエリアパッド配置の半導体装置の断面図である。It is sectional drawing of the semiconductor device of the conventional area pad arrangement | positioning. （ａ）は従来の金属突起に導電性ペーストを転写した状態の断面図、（ｂ）はその導電性ペーストを転写した金属突起を基板の電極パッドに圧着した状態の断面図である。(A) is sectional drawing of the state which transferred the electrically conductive paste to the conventional metal protrusion, (b) is sectional drawing of the state which crimped | bonded the metal protrusion which transcribe | transferred the conductive paste to the electrode pad of a board | substrate. 従来のエリアパッド配置の半導体装置の他の例の断面図である。It is sectional drawing of the other example of the semiconductor device of the conventional area pad arrangement | positioning.

符号の説明Explanation of symbols

１ 半導体素子
２ 半導体素子の電極パッド
３ キャピラリ
３１ キャピラリ先端の平坦面
３２ キャピラリホール
３３ キャピラリの側周面の段差
４ 金属突起
４ｃ 裾野の周縁が盛り上がった形状をしている略山形形状の金属突起
４ｄ 頭頂部がハンマー型の略山形形状の金属突起
４ｅ 裾野の周縁の盛り上がった部分が複数の段を持つ形状をしている略山形形状の金属突起
４１ 金属ワイヤ
４２ Ａｕボール
４３ 金属突起の台の平坦部
４４ 金属突起の中心部の突起の先端
４５ 略山形形状の金属突起の台の外周部の壁
４５ａ略山形形状の金属突起の台の外周部の壁に形成された複数の段
４６ 金属突起の中心部の突起
４７ 頭頂部がハンマー型の山形金属突起の頭頂部
５ レベリングツール
６ 導電性ペースト
７ 基板
８ 基板の電極パッド
９ エポキシ樹脂
１１ 外部端子
ｈ１ 山形金属突起の壁の高さ
ｈ２ キャピラリの段差の大きさ DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Electrode pad 3 of semiconductor element Capillary 31 Flat surface 32 of capillary tip Capillary hole 33 Level difference 4 on the peripheral surface of the capillary 4 Metal protrusion 4c A substantially chevron-shaped metal protrusion 4d having a raised rim Hammer-shaped substantially chevron-shaped metal protrusion 4e having a head-like shape The substantially chevron-shaped metal protrusion 41 having a shape in which the raised portion of the periphery of the skirt has a plurality of steps 41 Metal wire 42 Au ball 43 Flat of the metal protrusion base Part 44 Projection tip 45 in the center of the metal projection 45 Wall 46a of the outer periphery of the substantially chevron shaped metal projection base 45a A plurality of steps 46 formed on the outer peripheral wall of the base of the metal protuberance of the substantially chevron shape Protrusion 47 in the center part The top part of the chevron metal protrusion whose top part is a hammer type 5 Leveling tool 6 Conductive paste 7 Substrate 8 Substrate electrode pad 9 Epoxy resin 11 External terminal h1 Angle of metal projection wall height h2 Capillary step size

Claims (9)

回路形成面に複数の電極パッドを配置した半導体素子と、前記半導体素子の回路形成面と対向する面に複数の電極部を配置し反対側の面に複数の外部端子を配置した基板とを備え、前記半導体素子の電極パッドと前記基板の電極部は、複数の金属突起と導電性ペーストを介して各々電気的に接続される半導体装置であって、
前記金属突起は、前記半導体素子の回路形成面に複数列となるように前記電極パッドに形成され、前記半導体素子の回路形成面の中央領域に配置する金属突起の断面形状は、周縁が盛り上がった裾野を有する略山形形状であることを特徴とする半導体装置。 A semiconductor element having a plurality of electrode pads disposed on a circuit forming surface, and a substrate having a plurality of electrode portions disposed on a surface facing the circuit forming surface of the semiconductor element and a plurality of external terminals disposed on the opposite surface. The semiconductor device electrode pad and the substrate electrode portion are electrically connected to each other through a plurality of metal protrusions and a conductive paste,
The metal protrusions are formed on the electrode pads so as to form a plurality of rows on the circuit formation surface of the semiconductor element, and the periphery of the cross-sectional shape of the metal protrusion disposed in the central region of the circuit formation surface of the semiconductor element is raised A semiconductor device having a substantially chevron shape having a base. 回路形成面に複数の電極パッドを配置した半導体素子と、前記半導体素子の回路形成面と対向する面に複数の電極部を配置し反対側の面に複数の外部端子を配置した基板とを備え、前記半導体素子の電極パッドと前記基板の電極部は、複数の金属突起と導電性ペーストを介して各々電気的に接続される半導体装置であって、
前記金属突起は、前記半導体素子の回路形成面に複数列となるように前記電極パッドに形成され、前記半導体素子の回路形成面の最外周に配置する金属突起の断面形状は、周縁が盛り上がった裾野を有する略山形形状であることを特徴とする半導体装置。 A semiconductor element having a plurality of electrode pads disposed on a circuit forming surface, and a substrate having a plurality of electrode portions disposed on a surface facing the circuit forming surface of the semiconductor element and a plurality of external terminals disposed on the opposite surface. The semiconductor device electrode pad and the substrate electrode portion are electrically connected to each other through a plurality of metal protrusions and a conductive paste,
The metal protrusions are formed on the electrode pads so as to form a plurality of rows on the circuit formation surface of the semiconductor element, and the periphery of the metal protrusion arranged on the outermost periphery of the circuit formation surface of the semiconductor element is raised. A semiconductor device having a substantially chevron shape having a base. 前記金属突起は、周縁の盛り上がった部分が複数の段を持つ階段状になっている請求項１または２記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the metal protrusion has a stepped shape with a plurality of steps on a peripheral edge. 前記金属突起の頭頂部がハンマー型である請求項１，２または３記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the top of the metal protrusion is a hammer type. 半導体素子の回路形成面に配置した複数の電極パッドに金属突起を形成する工程と、前記金属突起を平坦化する工程と、導電性ペーストを前記金属突起に転写する工程と、複数の電極部を有し、前記電極部と反対側の面に複数の外部端子を有した基板を準備する工程と、前記基板の複数の電極部に前記半導体素子の金属突起と導電性ペーストを加熱硬化し接合する工程と、前記半導体素子の回路形成面と前記基板の電極部側の面との間にアンダーフィルを注入する工程と、前記アンダーフィルを加熱硬化する工程とを含み、
前記金属突起を形成する際、同一キャピラリで凸型の金属突起と、周縁が盛り上がった裾野を有する略山形形状の金属突起とを形成することを特徴とする半導体装置の製造方法。 Forming a metal protrusion on a plurality of electrode pads arranged on a circuit formation surface of a semiconductor element, flattening the metal protrusion, transferring a conductive paste to the metal protrusion, and a plurality of electrode portions. And preparing a substrate having a plurality of external terminals on a surface opposite to the electrode portion, and heat-curing and bonding the metal protrusions of the semiconductor element and the conductive paste to the plurality of electrode portions of the substrate Including a step, a step of injecting an underfill between a circuit formation surface of the semiconductor element and a surface on the electrode portion side of the substrate, and a step of heat curing the underfill.
A method of manufacturing a semiconductor device, wherein when forming the metal protrusion, a convex metal protrusion is formed with the same capillary and a substantially chevron-shaped metal protrusion having a base with a raised periphery. 半導体素子の回路形成面に配置した複数の電極パッドに金属突起を形成する工程と、前記金属突起を平坦化する工程と、導電性ペーストを前記金属突起に転写する工程と、複数の電極部を有し、前記電極部と反対側の面に複数の外部端子を有した基板を準備する工程と、前記基板の複数の電極部に前記半導体素子の金属突起と導電性ペーストを加熱硬化し接合する工程と、前記半導体素子の回路形成面と前記基板の電極部側の面との間にアンダーフィルを注入する工程と、前記アンダーフィルを加熱硬化する工程とを含み、
前記金属突起を形成する際、周縁が盛り上がった裾野を有する略山形形状で、盛り上がった部分の段数が違う複数の金属突起を同一キャピラリで形成することを特徴とする半導体装置の製造方法。 Forming a metal protrusion on a plurality of electrode pads arranged on a circuit formation surface of a semiconductor element, flattening the metal protrusion, transferring a conductive paste to the metal protrusion, and a plurality of electrode portions. And preparing a substrate having a plurality of external terminals on a surface opposite to the electrode portion, and heat-curing and bonding the metal protrusions of the semiconductor element and the conductive paste to the plurality of electrode portions of the substrate Including a step, a step of injecting an underfill between a circuit formation surface of the semiconductor element and a surface on the electrode portion side of the substrate, and a step of heat curing the underfill.
A method of manufacturing a semiconductor device, wherein when forming the metal protrusion, a plurality of metal protrusions having a substantially chevron shape having a skirt with a raised periphery and different numbers of raised portions are formed with the same capillary. 前記金属突起を平坦化する工程において、前記略山形形状の金属突起の頭頂部がハンマー型となるように平坦化する請求項５または６記載の半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 5, wherein in the step of flattening the metal protrusion, the top of the substantially chevron-shaped metal protrusion is flattened so as to have a hammer shape. 前記キャピラリは、先端の外周に段付き部分を有し、略山形形状の金属突起の周縁の盛り上がった部分を前記段付き部分によって形成する請求項５，６または７記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 5, wherein the capillary has a stepped portion on the outer periphery of the tip, and a raised portion of a peripheral edge of a substantially chevron-shaped metal projection is formed by the stepped portion. 前記略山形形状の金属突起の頭頂部はハンマー型であり、前記導電性ペーストを前記金属突起に転写する工程において、前記頭頂部の大きさを変化させることによって前記導電性ペーストの転写量を変化させる請求項５または７記載の半導体装置の製造方法。   The top portion of the substantially chevron-shaped metal protrusion is a hammer type, and in the step of transferring the conductive paste to the metal protrusion, the transfer amount of the conductive paste is changed by changing the size of the top portion. A method for manufacturing a semiconductor device according to claim 5 or 7.
JP2004184631A 2004-06-23 2004-06-23 Semiconductor device and its manufacturing method Pending JP2006012950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004184631A JP2006012950A (en) 2004-06-23 2004-06-23 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004184631A JP2006012950A (en) 2004-06-23 2004-06-23 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2006012950A true JP2006012950A (en) 2006-01-12

Family

ID=35779851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004184631A Pending JP2006012950A (en) 2004-06-23 2004-06-23 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2006012950A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10727385B2 (en) 2018-03-15 2020-07-28 Nichia Corporation Light emitting device, light emitting element and method for manufacturing the light emitting element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10727385B2 (en) 2018-03-15 2020-07-28 Nichia Corporation Light emitting device, light emitting element and method for manufacturing the light emitting element

Similar Documents

Publication Publication Date Title
CN101578695B (en) Semiconductor element mounting structure and semiconductor element mounting method
US6391683B1 (en) Flip-chip semiconductor package structure and process for fabricating the same
US20100109159A1 (en) Bumped chip with displacement of gold bumps
US20060125113A1 (en) Flip chip package with anti-floating structure
JP2006202991A (en) Circuit board and its manufacturing method, and semiconductor package and its manufacturing method
JP5645592B2 (en) Manufacturing method of semiconductor device
JP2006310530A (en) Circuit device and its manufacturing process
US9520374B2 (en) Semiconductor device, substrate and semiconductor device manufacturing method
JP5181261B2 (en) Contact pad for integrated circuit and method of forming contact pad
US6396155B1 (en) Semiconductor device and method of producing the same
JP2008277751A (en) Method of manufacturing semiconductor device, and semiconductor device
JPH08153830A (en) Semiconductor device and manufacture thereof
JPH11312711A (en) Method for connecting electronic component
JP2009246337A (en) Semiconductor device and method of manufacturing the same
US7994638B2 (en) Semiconductor chip and semiconductor device
JP2008517475A (en) Substrate having electric contact and method of manufacturing the same
JP3981817B2 (en) Manufacturing method of semiconductor device
JP2007059638A (en) Semiconductor device and its manufacturing method
JP4835406B2 (en) Mounting structure and manufacturing method thereof, and semiconductor device and manufacturing method thereof
US20080157305A1 (en) Chip package structure
JP2006012950A (en) Semiconductor device and its manufacturing method
JP4267549B2 (en) SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE
JP2012023409A (en) Circuit device and method for manufacturing thereof
JP4565931B2 (en) Manufacturing method of semiconductor device
JP3859963B2 (en) Semiconductor device and manufacturing method thereof