JP2006005132A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To raise the withstanding voltage of a protective circuit for semiconductor devices and improve the degree of design freedom of the withstanding voltage. <P>SOLUTION: A protective circuit formed to deal with a gate electrode 4 has a gate oxide film composed of a laminate oxide film (a gate oxide film 3 and a gate oxide film 16) on an n-type semiconductor substrate 1. The gate oxide films 3, 16 have respectively optimized thicknesses for realizing a protective circuit having a high withstanding voltage of nearly a target value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a technique for realizing a protection circuit exhibiting desired withstand voltage characteristics.

  In recent years, with the high integration and miniaturization of semiconductor integrated circuit devices, the importance of protection circuits that prevent external damage due to high voltage or static electricity is increasing.

  In addition, with the miniaturization of semiconductor integrated circuits, the operating voltage is lowered and the thickness of the gate oxide film is also reduced. Along with this, the design parameters of the protection circuit are also limited. In order to obtain a desired protection circuit operating voltage, it is necessary to optimize the concentration profile of the source / drain region, which determines the breakdown voltage of the MOS type protection circuit, and the film thickness of the gate insulating film.

  However, when the diffusion condition for optimizing the protection circuit operating voltage is adopted, there is a problem that the number of processes increases due to the introduction of the diffusion condition dedicated to the protection circuit.

  Therefore, a technique has been proposed in which a diffusion condition currently used in a semiconductor integrated circuit is directly transferred to a protection circuit.

  Hereinafter, a method of forming a protection circuit for a semiconductor device according to a conventional method will be described with reference to FIG. In this conventional method, a semiconductor device with a high breakdown voltage specification will be described.

  In FIG. 4, 1 is an n-type semiconductor substrate, 2 is a p-type well, 3 is a gate oxide film, 4 is a gate electrode, 5 is a polysilicon oxide film, 6 is a silicon oxide film, 7 is an n + -type diffusion region, 8 Is an n ++ type diffusion region, 9 is an interlayer insulating CVD (Chemical Vapor Deposition) film, 10 is a BPSG (Boron-Phospho Silicated Glass) film, 11 is an adhesion layer, 12 is a tungsten buried layer, 13 is an aluminum wiring, 14 is A contact window 15 is a protective film.

The substrate concentration of the n-type semiconductor substrate 1 is 10 ¹⁴ to 10 ¹⁵ cm ⁻³ , and the p-type well 2 having a concentration of 10 ¹⁵ to 10 ¹⁶ cm ⁻³ is formed in the n-type semiconductor substrate 1. A gate oxide film 3 grown by a thermal oxidation method is formed on the entire surface of the n-type semiconductor substrate 1. Since the protection circuit of this conventional method has a high breakdown voltage specification, the gate oxide film 3 has a thickness as thick as about 30 nm. A gate electrode 4 made of polysilicon is formed on the gate oxide film 3. The polysilicon gate electrode is doped with about 10 ²⁰ cm ⁻³ of phosphorus and is an electrically low-resistance material.

  Since the semiconductor device according to the conventional method has a high breakdown voltage specification, the gate length L of the gate electrode 4 is as large as 5 μm, and the gate width W is 300 μm to ensure sufficient surge resistance. Next, a polysilicon oxide film 5 and a silicon oxide film 6 are respectively formed on the polysilicon surface and the semiconductor substrate surface by thermal oxidation after the formation of the gate electrode 4. The thickness of the polysilicon oxide film 5 is about 40 nm. Further, since the silicon oxide film 6 is laminated with the film thickness of the gate oxide film 3, the film thickness is about 40 nm.

  An interlayer insulating CVD film 9 is grown on the polysilicon oxide film 5 and the silicon oxide film 6. The film thickness is about 50 nm, and since it is a CVD film, it shows good step coverage and a weak spot with a weak withstand voltage disappears. Further, a BPSG film 10 is formed on the upper layer, and planarization of the semiconductor device and insulation between the wiring and the semiconductor substrate are performed.

At the both ends of the gate, n ++ type diffusion regions 8 serving as source / drain regions are formed in the p type well 2. The concentration is as high as 10 ²⁰ cm ⁻³ . Since this n ++ type diffusion region 8 has a very high concentration, only a low reverse voltage can be obtained when it is directly joined to the p type well 2. Thus, the breakdown voltage between the p-type well 2 is ensured by positioning the n + -type diffusion region 7 having a low concentration around the high-concentration n ++ type diffusion region 8.

  Further, since the n + -type diffusion region 8 becomes a source / drain region, it overlaps with the gate electrode 4 by about 0.3 μm. An adhesion layer 11, a tungsten buried layer 12, and an aluminum wiring 13 are connected to the n ++ type diffusion region 8 through a contact window 14. Finally, a protective film 15 made of a CVD film is formed with a thickness of about 500 nm.

  From the above structure, a protection circuit for a semiconductor device according to the conventional method is configured.

In addition, as a technique for improving the breakdown voltage of the gate insulating film itself of a semiconductor device, Patent Document 1 discloses that a CVD oxide film is deposited on a silicon thermal oxide film and a weak spot is embedded in the silicon thermal oxide film, thereby stacking layers. A technique for improving the breakdown voltage of the film itself has been proposed.
JP 9-326487 A

  However, in the conventional method, the diffusion parameters (gate oxide film thickness, n + -type diffusion region impurity concentration, p-type well impurity concentration) that determine the breakdown voltage of the protection circuit are determined so as to improve the internal device characteristics of the semiconductor device. Therefore, it has been difficult to realize ideal protection circuit characteristics.

  The present invention provides a method of manufacturing a semiconductor device and a semiconductor device capable of realizing protection circuit characteristics having ideal characteristics without significantly increasing the diffusion process in view of the conventional technique. For the purpose.

  In order to solve the above-described problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a protection circuit having a MOS type transistor. Forming a first oxide film on the substrate; removing a first oxide film other than a predetermined region of the first oxide film; and forming a second oxide film on the semiconductor substrate including the predetermined region A step of forming a gate electrode on the first oxide film and the second oxide film in a predetermined region, and a step of forming a reverse conductivity type diffusion layer in the semiconductor substrate on both sides of the gate electrode. It is characterized by having.

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a protection circuit having a MOS transistor. In the process for manufacturing a MOS transistor, the first method is provided on a semiconductor substrate of one conductivity type. Forming a first oxide film, removing a first oxide film other than a predetermined region of the first oxide film, forming a second oxide film on a semiconductor substrate including the predetermined region, and a predetermined Forming a silicon nitride film on the second oxide film in the region; forming a gate electrode on the silicon nitride film; and forming a diffusion layer of opposite conductivity type in the semiconductor substrate on both sides of the gate electrode And a process.

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a protection circuit having a MOS transistor. In the process for manufacturing a MOS transistor, the first method is provided on a semiconductor substrate of one conductivity type. Forming a first oxide film, removing a first oxide film other than a predetermined region of the first oxide film, forming a second oxide film on a semiconductor substrate including the predetermined region, and a predetermined Forming a silicon nitride film on the second oxide film in the region; forming a third oxide film on the silicon nitride film; forming a gate electrode on the third oxide film; And a step of forming a reverse conductivity type diffusion layer in the semiconductor substrate on both sides of the electrode.

  According to another aspect of the present invention, there is provided a semiconductor device including a protection circuit having a MOS transistor, the MOS transistor being a first substrate formed in a predetermined region on a semiconductor substrate of one conductivity type. An oxide film, a second oxide film formed on a semiconductor substrate including a predetermined region, a first oxide film in a predetermined region and a gate electrode formed on the second oxide film, and sandwiching the gate electrode And a reverse conductivity type diffusion layer formed in the semiconductor substrate on both sides.

  According to another aspect of the present invention, there is provided a semiconductor device including a protection circuit having a MOS transistor, the MOS transistor being a first substrate formed in a predetermined region on a semiconductor substrate of one conductivity type. An oxide film, a second oxide film formed on a semiconductor substrate including a predetermined region, a silicon nitride film formed on the second oxide film in the predetermined region, and a gate formed on the silicon nitride film A semiconductor device comprising: an electrode; and a reverse conductivity type diffusion layer formed in a semiconductor substrate on both sides of the gate electrode.

  According to another aspect of the present invention, there is provided a semiconductor device including a protection circuit having a MOS transistor, the MOS transistor being a first substrate formed in a predetermined region on a semiconductor substrate of one conductivity type. An oxide film, a second oxide film formed on the semiconductor substrate including the predetermined region, a silicon nitride film formed on the second oxide film in the predetermined region, and a second oxide film formed on the silicon nitride film 3, a gate electrode formed on the third oxide film, and a reverse conductivity type diffusion layer formed in the semiconductor substrate on both sides of the gate electrode.

  As described above, in the semiconductor device according to the present invention, the gate oxide film of the protection circuit has two or more stacked oxide films, and is formed to be thicker than the gate oxide film thickness other than the protection circuit. Features.

  According to the semiconductor device of the present invention, it is possible to realize a protection circuit exhibiting ideal withstand voltage characteristics regardless of the internal cell design of the semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, members corresponding to the members described in FIG.

(Embodiment 1)
FIG. 1 is a cross-sectional view of a semiconductor device for explaining the first embodiment of the present invention. In this embodiment, a semiconductor device with a high breakdown voltage specification will be explained.

  In FIG. 1, 1 is an n-type semiconductor substrate, 2 is a p-type well, 3 is a gate oxide film, 4 is a gate electrode, 5 is a polysilicon oxide film, 6 is a silicon oxide film, 7 is an n + -type diffusion region, 8 Is an n ++ type diffusion region, 9 is an interlayer insulating CVD film, 10 is a BPSG film, 11 is an adhesion layer, 12 is a tungsten buried layer, 13 is an aluminum wiring, 14 is a contact window, 15 is a protective film, 16 is a gate oxide It is a membrane.

  Similar to the conventional example described with reference to FIG. 4, a p-type well 2 is formed in an n-type semiconductor substrate 1. Next, a thermal oxide film 20 nm is formed on the entire surface of the n-type semiconductor substrate 1. This oxide film is formed as a protective oxide film in order to form the diffusion layer of the internal device of the semiconductor device.

  Thereafter, the oxide film is removed by oxide film etching after a region to be a gate insulating film of the protection circuit is masked with a resist. Eventually, the gate oxide film 16 remains in the region of the gate insulating film 3 of the protection circuit. When the gate oxide film 3 is again grown to 30 nm on the upper layer, the gate oxide film 3 is laminated, and the film thickness becomes 45 nm. With this stacked structure, a gate oxide film having a thickness of 45 nm can be realized. Thereafter, as in the prior art, the gate electrode 4 and the like are processed to form a diffusion layer, an interlayer insulating film, and a wiring layer, thereby completing the protection circuit including the MOS transistor of the semiconductor device.

The polysilicon electrode is doped with about 10 ²⁰ cm ⁻³ of phosphorus and has a large value of W / L = 300 μm / 5 μm. Next, a polysilicon oxide film 5 and a silicon oxide film 6 are respectively formed on the surface of the semiconductor substrate. The thickness of the polysilicon oxide film 5 is about 40 nm. Further, since the silicon oxide film 6 is laminated with the film thickness of the gate oxide film 3, the film thickness is about 40 nm.

  An interlayer insulating CVD film 9 is grown on the polysilicon oxide film 5 and the silicon oxide film 6. The film thickness is about 50 nm. Further, a BPSG film 10 is formed on the upper layer, and planarization of the semiconductor device and insulation between the wiring and the semiconductor substrate are performed.

At the both ends of the gate, n ++ type diffusion regions 8 serving as source / drain regions are formed in the p type well 2. The concentration is as high as 10 ²⁰ cm ⁻³ . In order to secure a breakdown voltage between the n ++ type diffusion region 8 and the p type well, the low concentration n + type diffusion region 7 is positioned around the high concentration n ++ type diffusion region 8.

  According to the first embodiment, as shown in FIG. 5, a stacked gate oxide film structure is introduced without adopting a method of changing the implantation amount of the n + -type diffusion region 7 and ensuring the breakdown voltage of the protection circuit. As a result, as shown in FIG. 6, the effective thickness of the gate insulating film can be changed to realize a protection circuit having an arbitrary withstand voltage, and the protection circuit withstand voltage design flexibility can be increased.

  In this embodiment, the gate oxide film 3 is a two-layered oxide film. However, the gate oxide film 3 may be formed by repeatedly laminating two or more layers.

  Further, the gate oxide film of the MOS transistor of the protection circuit is formed by a plurality of layers (for example, two layers), and the gate oxide film of a circuit other than the protection circuit is formed by a smaller number of layers (for example, one layer). Thus, it is possible to achieve both the characteristics of the circuits other than the protection circuit and the breakdown voltage characteristics of the protection circuit.

(Embodiment 2)
FIG. 2 is a cross-sectional view of a semiconductor device for explaining the second embodiment of the present invention. The second embodiment is different from the first embodiment in that the gate insulating film is a stacked oxide of the gate oxide film 16 and the gate oxide film 3. This is different in that it is composed of a film and a laminated gate insulating film of the silicon nitride film 17.

The laminated gate insulating film is first grown by thermal oxidation on the entire surface of the semiconductor substrate to a thickness of 20 nm, a region to be a gate insulating film of the protective circuit is masked with a resist, and then removed by oxide film etching, thereby removing the gate of the protective circuit. The gate oxide film 16 remains in the insulating film region. A gate oxide film is laminated by growing a 30 nm thick gate oxide film 3 on the upper layer. The film thickness is 45 nm. Further, by growing the silicon nitride film 17 to a thickness of 20 nm on the upper layer by the low pressure CVD method, the electric SiO ₂ equivalent film thickness of the entire gate insulating film including the film thickness of 45 nm of the underlying laminated oxide film becomes 55 nm.

According to the second embodiment, since it is possible to grow a silicon nitride film on the upper layer in addition to the lower oxide film, it is possible to easily realize a thick gate insulating film with an equivalent SiO ₂ thickness. The selection range of the withstand voltage design of the protection circuit is expanded (see FIG. 6).

(Embodiment 3)
FIG. 3 is a cross-sectional view of a semiconductor device for explaining the third embodiment of the present invention. The third embodiment is different from the first embodiment in that the gate insulating film is a stacked oxide of the gate oxide film 16 and the gate oxide film 3. The difference is that the film is composed of a laminated gate insulating film of a silicon nitride film 17 and a silicon nitride oxide film 18.

The laminated gate insulating film is formed by first growing a thermal oxide film 16 on the entire surface of the semiconductor substrate to a thickness of 20 nm, masking a region to be a gate insulating film of the protective circuit with a resist, and then removing the oxide film by etching the oxide film. The gate oxide film 16 remains in the gate insulating film region. When the gate oxide film 3 is again grown to 30 nm on the upper layer, the gate oxide film is laminated. The film thickness is 45 nm. Further, a 20 nm thick silicon nitride film 17 is grown thereon by a low pressure CVD method. Next, by thermally oxidizing the entire semiconductor substrate, the silicon oxynitride film 18 is grown by about 2 nm. The electrical SiO ₂ equivalent film thickness of the entire gate insulating film including the film thickness of 45 nm of the underlying laminated oxide film is 57 nm. For example, the electric SiO ₂ equivalent film thickness of the entire gate insulating film is 57 nm including the film thickness of 45 nm of the underlying laminated oxide film and the film thickness of 20 nm of the silicon nitride film 17.

According to the third embodiment, the thicker gate insulating film can be realized by increasing the electrical SiO ₂ equivalent film thickness by 2 nm, so that the selection range of the withstand voltage design of the protection circuit is widened (see FIG. 6).

  The present invention is useful for increasing the breakdown voltage of a protection circuit of a semiconductor device and improving the degree of freedom in design of the breakdown voltage.

Sectional drawing of the semiconductor device for describing Embodiment 1 of this invention Sectional drawing of the semiconductor device for describing Embodiment 2 of this invention Sectional drawing of the semiconductor device for describing Embodiment 3 of this invention Sectional view showing a conventional semiconductor device The figure for demonstrating the n + type diffused layer injection amount dependence of a protection circuit breakdown voltage Diagram for explaining the dependency of the protection circuit withstand voltage on the thickness of the gate insulating film

Explanation of symbols

1 n-type semiconductor substrate 2 p-type well 3 gate oxide film 4 gate electrode 5 polysilicon oxide film 6 silicon oxide film 7 n + type diffusion region 8 n ++ type diffusion region 9 interlayer insulating CVD film 10 BPSG film 11 adhesion layer 12 Tungsten buried layer 13 Aluminum wiring 14 Contact window 15 Protective film 16 Gate oxide film 17 Silicon nitride film 18 Silicon nitride oxide film

Claims (6)

A method of manufacturing a semiconductor device including a protection circuit having a MOS transistor, wherein the MOS transistor is manufactured in a process,
Forming a first oxide film on a semiconductor substrate of one conductivity type;
Removing a first oxide film other than a predetermined region of the first oxide film;
Forming a second oxide film on the semiconductor substrate including the predetermined region;
Forming a gate electrode on the first oxide film and the second oxide film in the predetermined region;
Forming a reverse conductivity type diffusion layer in the semiconductor substrate on both sides of the gate electrode; and
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device including a protection circuit having a MOS transistor, wherein the MOS transistor is manufactured in a process,
Forming a first oxide film on a semiconductor substrate of one conductivity type;
Removing a first oxide film other than a predetermined region of the first oxide film;
Forming a second oxide film on the semiconductor substrate including the predetermined region;
Forming a silicon nitride film on the second oxide film in the predetermined region;
Forming a gate electrode on the silicon nitride film;
Forming a reverse conductivity type diffusion layer in the semiconductor substrate on both sides of the gate electrode; and
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device including a protection circuit having a MOS transistor, wherein the MOS transistor is manufactured in a process,
Forming a first oxide film on a semiconductor substrate of one conductivity type;
Removing a first oxide film other than a predetermined region of the first oxide film;
Forming a second oxide film on the semiconductor substrate including the predetermined region;
Forming a silicon nitride film on the second oxide film in the predetermined region;
Forming a third oxide film on the silicon nitride film;
Forming a gate electrode on the third oxide film;
Forming a reverse conductivity type diffusion layer in the semiconductor substrate on both sides of the gate electrode; and
A method for manufacturing a semiconductor device, comprising: A semiconductor device including a protection circuit having a MOS transistor, wherein the MOS transistor is
A semiconductor substrate of one conductivity type;
A first oxide film formed in a predetermined region on the semiconductor substrate;
A second oxide film formed on the semiconductor substrate including the predetermined region;
A gate electrode formed on the first oxide film and the second oxide film in the predetermined region;
A reverse conductivity type diffusion layer formed in the semiconductor substrate on both sides of the gate electrode;
A semiconductor device comprising: A semiconductor device including a protection circuit having a MOS transistor, wherein the MOS transistor is
A semiconductor substrate of one conductivity type;
A first oxide film formed in a predetermined region on the semiconductor substrate;
A second oxide film formed on the semiconductor substrate including the predetermined region;
A silicon nitride film formed on the second oxide film in the predetermined region;
A gate electrode formed on the silicon nitride film;
A reverse conductivity type diffusion layer formed in the semiconductor substrate on both sides of the gate electrode;
A semiconductor device comprising: A semiconductor device including a protection circuit having a MOS transistor, wherein the MOS transistor is
A semiconductor substrate of one conductivity type;
A first oxide film formed in a predetermined region on the semiconductor substrate;
A second oxide film formed on the semiconductor substrate including the predetermined region;
A silicon nitride film formed on the second oxide film in the predetermined region;
A third oxide film formed on the silicon nitride film;
A gate electrode formed on the third oxide film;
A reverse conductivity type diffusion layer formed in the semiconductor substrate on both sides of the gate electrode;
A semiconductor device comprising:

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