JP2005535965A5 - - Google Patents
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- JP2005535965A5 JP2005535965A5 JP2004527782A JP2004527782A JP2005535965A5 JP 2005535965 A5 JP2005535965 A5 JP 2005535965A5 JP 2004527782 A JP2004527782 A JP 2004527782A JP 2004527782 A JP2004527782 A JP 2004527782A JP 2005535965 A5 JP2005535965 A5 JP 2005535965A5
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- text representation
- generate
- register transfer
- transfer level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000013500 data storage Methods 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/215,869 | 2002-08-09 | ||
| US10/215,869 US6904576B2 (en) | 2002-08-09 | 2002-08-09 | Method and system for debugging using replicated logic |
| PCT/US2003/024601 WO2004015596A2 (en) | 2002-08-09 | 2003-08-05 | Method and system for debugging using replicated logic |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005535965A JP2005535965A (ja) | 2005-11-24 |
| JP2005535965A5 true JP2005535965A5 (OSRAM) | 2006-09-28 |
| JP4806529B2 JP4806529B2 (ja) | 2011-11-02 |
Family
ID=31494954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004527782A Expired - Lifetime JP4806529B2 (ja) | 2002-08-09 | 2003-08-05 | 複製されたロジックを使用するデバッグの方法とシステム |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US6904576B2 (OSRAM) |
| EP (1) | EP1546947B1 (OSRAM) |
| JP (1) | JP4806529B2 (OSRAM) |
| AT (1) | ATE365349T1 (OSRAM) |
| AU (1) | AU2003261401A1 (OSRAM) |
| DE (1) | DE60314530T2 (OSRAM) |
| WO (1) | WO2004015596A2 (OSRAM) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7222315B2 (en) * | 2000-11-28 | 2007-05-22 | Synplicity, Inc. | Hardware-based HDL code coverage and design analysis |
| US7213216B2 (en) * | 2002-08-09 | 2007-05-01 | Synplicity, Inc. | Method and system for debugging using replicated logic and trigger logic |
| US6904576B2 (en) * | 2002-08-09 | 2005-06-07 | Synplicity, Inc. | Method and system for debugging using replicated logic |
| US7398445B2 (en) * | 2002-08-09 | 2008-07-08 | Synplicity, Inc. | Method and system for debug and test using replicated logic |
| DE10345150B3 (de) * | 2003-09-29 | 2005-04-14 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren, Vorrichtung und System zum Analysieren digitaler Schaltungen |
| US7134104B2 (en) * | 2003-12-05 | 2006-11-07 | International Business Machines Corporation | Method of selectively building redundant logic structures to improve fault tolerance |
| US7373631B1 (en) * | 2004-08-11 | 2008-05-13 | Altera Corporation | Methods of producing application-specific integrated circuit equivalents of programmable logic |
| US7487473B2 (en) * | 2006-09-12 | 2009-02-03 | International Business Machines Corporation | Enabling netlist for modeling of technology dependent BEOL process variation |
| US7904859B2 (en) * | 2007-05-09 | 2011-03-08 | Synopsys, Inc. | Method and apparatus for determining a phase relationship between asynchronous clock signals |
| US7908574B2 (en) | 2007-05-09 | 2011-03-15 | Synopsys, Inc. | Techniques for use with automated circuit design and simulations |
| US8756557B2 (en) * | 2007-05-09 | 2014-06-17 | Synopsys, Inc. | Techniques for use with automated circuit design and simulations |
| US7984400B2 (en) * | 2007-05-09 | 2011-07-19 | Synopsys, Inc. | Techniques for use with automated circuit design and simulations |
| US7657851B2 (en) * | 2007-06-29 | 2010-02-02 | International Business Machines Corporation | Device, system, and method for correction of integrated circuit design |
| US8181135B2 (en) * | 2009-08-27 | 2012-05-15 | International Business Machines Corporation | Hold transition fault model and test generation method |
| US8397195B2 (en) * | 2010-01-22 | 2013-03-12 | Synopsys, Inc. | Method and system for packet switch based logic replication |
| US8638792B2 (en) | 2010-01-22 | 2014-01-28 | Synopsys, Inc. | Packet switch based logic replication |
| US8924788B2 (en) * | 2010-06-28 | 2014-12-30 | Intel Corporation | Replaying architectural execution with a probeless trace capture |
| US8886507B2 (en) | 2011-07-13 | 2014-11-11 | General Electric Company | Methods and systems for simulating circuit operation |
| WO2014052936A1 (en) * | 2012-09-28 | 2014-04-03 | Arteris SAS | Automatic safety logic insertion |
| CN106886210B (zh) * | 2017-01-04 | 2019-03-08 | 北京航天自动控制研究所 | 基于序列触发拍照的火工品时序测试装置 |
| US10409994B1 (en) | 2017-03-01 | 2019-09-10 | National Technology & Engineering Solutions Of Sandia, Llc | FPGA/ASIC framework and method for requirements-based trust assessment |
| CN110988662B (zh) * | 2019-12-09 | 2022-08-02 | 上海国微思尔芯技术股份有限公司 | 一种基于fpga原型验证开发板的信号调试系统及方法 |
| CN113095015B (zh) * | 2021-05-08 | 2024-05-24 | 中国科学院上海微系统与信息技术研究所 | Sfq时序电路综合计算方法、系统以及终端 |
| CN113608491B (zh) * | 2021-07-16 | 2022-09-02 | 广东财经大学 | 一种编译延时逻辑原理图到字节码方法 |
| CN114254575A (zh) * | 2021-12-10 | 2022-03-29 | 山东云海国创云计算装备产业创新中心有限公司 | 一种生成寄存器转换级文件列表文件的方法和装置 |
| CN116108783B (zh) * | 2023-04-04 | 2023-07-18 | 上海思尔芯技术股份有限公司 | 分块逻辑时序分析建模及处理方法、系统、设备及介质 |
Family Cites Families (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0358365B1 (en) * | 1988-09-07 | 1998-10-21 | Texas Instruments Incorporated | Testing buffer/register |
| US5056094A (en) * | 1989-06-09 | 1991-10-08 | Texas Instruments Incorporated | Delay fault testing method and apparatus |
| US5272390A (en) * | 1991-09-23 | 1993-12-21 | Digital Equipment Corporation | Method and apparatus for clock skew reduction through absolute delay regulation |
| US5452239A (en) * | 1993-01-29 | 1995-09-19 | Quickturn Design Systems, Inc. | Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system |
| US5706473A (en) | 1995-03-31 | 1998-01-06 | Synopsys, Inc. | Computer model of a finite state machine having inputs, outputs, delayed inputs and delayed outputs |
| JPH1010196A (ja) | 1996-06-21 | 1998-01-16 | Hitachi Ltd | 論理エミュレーション装置 |
| US6205579B1 (en) * | 1996-10-28 | 2001-03-20 | Altera Corporation | Method for providing remote software technical support |
| US6014510A (en) * | 1996-11-27 | 2000-01-11 | International Business Machines Corporation | Method for performing timing analysis of a clock circuit |
| JPH10177590A (ja) | 1996-12-18 | 1998-06-30 | Toshiba Corp | 論理回路モデルのデバッグ装置およびデバッグ方法 |
| US5923676A (en) * | 1996-12-20 | 1999-07-13 | Logic Vision, Inc. | Bist architecture for measurement of integrated circuit delays |
| US6286128B1 (en) * | 1998-02-11 | 2001-09-04 | Monterey Design Systems, Inc. | Method for design optimization using logical and physical information |
| IL142279A0 (en) * | 1998-09-30 | 2002-03-10 | Cadence Design Systems Inc | Block based methodology |
| US6438735B1 (en) * | 1999-05-17 | 2002-08-20 | Synplicity, Inc. | Methods and apparatuses for designing integrated circuits |
| US6519754B1 (en) * | 1999-05-17 | 2003-02-11 | Synplicity, Inc. | Methods and apparatuses for designing integrated circuits |
| KR100710972B1 (ko) | 1999-06-26 | 2007-04-24 | 양세양 | 혼합된 에뮬레이션과 시뮬레이션이 가능한 혼합 검증 장치및 이를 이용한 혼합 검증 방법 |
| JP2003503791A (ja) * | 1999-06-26 | 2003-01-28 | セイ−ヤン ヤン、 | 入出力探針装置及びこれを用いた入出力探針方法と、これを基盤とする混合エミュレーション/シミュレーション方法 |
| KR20010006983A (ko) | 1999-06-26 | 2001-01-26 | 양세양 | 신속 프로토타이핑 장치와 그것의 입출력 탐침방법 및그것을 이용한 혼합 검증 방법 |
| JP4642304B2 (ja) | 1999-11-29 | 2011-03-02 | セロツト・インコーポレーテツド | 汎用のハードウエアデバイス及び方法とそれと共に使用するツール |
| US7065481B2 (en) * | 1999-11-30 | 2006-06-20 | Synplicity, Inc. | Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer |
| DE10030349A1 (de) * | 2000-06-20 | 2002-01-10 | Kuratorium Offis E V | Verfahren zum Analysieren der Verlustleistung bzw. der Energieaufnahme einer elektrischen Schaltung bzw. eines elektrischen Bauelementes |
| US6725406B2 (en) * | 2001-01-09 | 2004-04-20 | Intel Corporation | Method and apparatus for failure detection utilizing functional test vectors and scan mode |
| US6634011B1 (en) * | 2001-02-15 | 2003-10-14 | Silicon Graphics, Inc. | Method and apparatus for recording program execution in a microprocessor based integrated circuit |
| US7191373B2 (en) * | 2001-03-01 | 2007-03-13 | Syntest Technologies, Inc. | Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques |
| US6516449B2 (en) * | 2001-04-02 | 2003-02-04 | Sun Microsystems, Inc. | Methodology to create integrated circuit designs by replication maintaining isomorphic input output and fault behavior |
| US6580299B2 (en) * | 2001-04-05 | 2003-06-17 | Parthus Ireland Limited | Digital circuit for, and a method of, synthesizing an input signal |
| US6530073B2 (en) * | 2001-04-30 | 2003-03-04 | Lsi Logic Corporation | RTL annotation tool for layout induced netlist changes |
| KR100794916B1 (ko) | 2001-09-14 | 2008-01-14 | 양세양 | 에뮬레이션과 시뮬레이션을 혼용한 점진적 설계 검증을위한 설계검증 장치 및 이를 이용한 설계 검증 방법 |
| JP2003099495A (ja) * | 2001-09-25 | 2003-04-04 | Fujitsu Ltd | 集積回路の設計システム、集積回路の設計方法およびプログラム |
| US6651227B2 (en) * | 2001-10-22 | 2003-11-18 | Motorola, Inc. | Method for generating transition delay fault test patterns |
| US6687882B1 (en) * | 2002-01-31 | 2004-02-03 | Synplicity, Inc. | Methods and apparatuses for non-equivalence checking of circuits with subspace |
| JP2003337845A (ja) | 2002-05-21 | 2003-11-28 | Matsushita Electric Ind Co Ltd | エミュレーション装置、及び、エミュレーション方法 |
| US6904576B2 (en) * | 2002-08-09 | 2005-06-07 | Synplicity, Inc. | Method and system for debugging using replicated logic |
| US7398445B2 (en) * | 2002-08-09 | 2008-07-08 | Synplicity, Inc. | Method and system for debug and test using replicated logic |
| US7213216B2 (en) * | 2002-08-09 | 2007-05-01 | Synplicity, Inc. | Method and system for debugging using replicated logic and trigger logic |
| JP2004280426A (ja) | 2003-03-14 | 2004-10-07 | Mitsubishi Electric Corp | 論理集積回路の内部信号トレース装置 |
| US7266489B2 (en) * | 2003-04-28 | 2007-09-04 | International Business Machines Corporation | Method, system and program product for determining a configuration of a digital design by reference to an invertible configuration database |
| US7055117B2 (en) * | 2003-12-29 | 2006-05-30 | Agere Systems, Inc. | System and method for debugging system-on-chips using single or n-cycle stepping |
-
2002
- 2002-08-09 US US10/215,869 patent/US6904576B2/en not_active Expired - Lifetime
-
2003
- 2003-08-05 EP EP03784944A patent/EP1546947B1/en not_active Expired - Lifetime
- 2003-08-05 JP JP2004527782A patent/JP4806529B2/ja not_active Expired - Lifetime
- 2003-08-05 AT AT03784944T patent/ATE365349T1/de not_active IP Right Cessation
- 2003-08-05 AU AU2003261401A patent/AU2003261401A1/en not_active Abandoned
- 2003-08-05 WO PCT/US2003/024601 patent/WO2004015596A2/en not_active Ceased
- 2003-08-05 DE DE60314530T patent/DE60314530T2/de not_active Expired - Lifetime
-
2008
- 2008-07-01 US US12/166,298 patent/US7962869B2/en not_active Expired - Lifetime
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