DE60314530T2 - Verfahren und system zum debuggen unter verwendung duplizierter logik - Google Patents

Verfahren und system zum debuggen unter verwendung duplizierter logik Download PDF

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Publication number
DE60314530T2
DE60314530T2 DE60314530T DE60314530T DE60314530T2 DE 60314530 T2 DE60314530 T2 DE 60314530T2 DE 60314530 T DE60314530 T DE 60314530T DE 60314530 T DE60314530 T DE 60314530T DE 60314530 T2 DE60314530 T2 DE 60314530T2
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Germany
Prior art keywords
circuit
logic
transfer level
register transfer
level netlist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60314530T
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German (de)
English (en)
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DE60314530D1 (de
Inventor
Chun Kit Portland NG
Kenneth S. Los Altos MCELVAIN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synplicity LLC
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Synplicity LLC
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Publication date
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Publication of DE60314530D1 publication Critical patent/DE60314530D1/de
Application granted granted Critical
Publication of DE60314530T2 publication Critical patent/DE60314530T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Hardware Redundancy (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)
DE60314530T 2002-08-09 2003-08-05 Verfahren und system zum debuggen unter verwendung duplizierter logik Expired - Lifetime DE60314530T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/215,869 US6904576B2 (en) 2002-08-09 2002-08-09 Method and system for debugging using replicated logic
US215869 2002-08-09
PCT/US2003/024601 WO2004015596A2 (en) 2002-08-09 2003-08-05 Method and system for debugging using replicated logic

Publications (2)

Publication Number Publication Date
DE60314530D1 DE60314530D1 (de) 2007-08-02
DE60314530T2 true DE60314530T2 (de) 2008-02-14

Family

ID=31494954

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60314530T Expired - Lifetime DE60314530T2 (de) 2002-08-09 2003-08-05 Verfahren und system zum debuggen unter verwendung duplizierter logik

Country Status (7)

Country Link
US (2) US6904576B2 (OSRAM)
EP (1) EP1546947B1 (OSRAM)
JP (1) JP4806529B2 (OSRAM)
AT (1) ATE365349T1 (OSRAM)
AU (1) AU2003261401A1 (OSRAM)
DE (1) DE60314530T2 (OSRAM)
WO (1) WO2004015596A2 (OSRAM)

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US7134104B2 (en) * 2003-12-05 2006-11-07 International Business Machines Corporation Method of selectively building redundant logic structures to improve fault tolerance
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US7984400B2 (en) * 2007-05-09 2011-07-19 Synopsys, Inc. Techniques for use with automated circuit design and simulations
US7908574B2 (en) * 2007-05-09 2011-03-15 Synopsys, Inc. Techniques for use with automated circuit design and simulations
US7904859B2 (en) * 2007-05-09 2011-03-08 Synopsys, Inc. Method and apparatus for determining a phase relationship between asynchronous clock signals
US8756557B2 (en) * 2007-05-09 2014-06-17 Synopsys, Inc. Techniques for use with automated circuit design and simulations
US7657851B2 (en) * 2007-06-29 2010-02-02 International Business Machines Corporation Device, system, and method for correction of integrated circuit design
US8181135B2 (en) * 2009-08-27 2012-05-15 International Business Machines Corporation Hold transition fault model and test generation method
US8638792B2 (en) * 2010-01-22 2014-01-28 Synopsys, Inc. Packet switch based logic replication
US8397195B2 (en) * 2010-01-22 2013-03-12 Synopsys, Inc. Method and system for packet switch based logic replication
US8924788B2 (en) * 2010-06-28 2014-12-30 Intel Corporation Replaying architectural execution with a probeless trace capture
US8886507B2 (en) * 2011-07-13 2014-11-11 General Electric Company Methods and systems for simulating circuit operation
WO2014052936A1 (en) * 2012-09-28 2014-04-03 Arteris SAS Automatic safety logic insertion
CN106886210B (zh) * 2017-01-04 2019-03-08 北京航天自动控制研究所 基于序列触发拍照的火工品时序测试装置
US10409994B1 (en) 2017-03-01 2019-09-10 National Technology & Engineering Solutions Of Sandia, Llc FPGA/ASIC framework and method for requirements-based trust assessment
CN110988662B (zh) * 2019-12-09 2022-08-02 上海国微思尔芯技术股份有限公司 一种基于fpga原型验证开发板的信号调试系统及方法
CN113095015B (zh) * 2021-05-08 2024-05-24 中国科学院上海微系统与信息技术研究所 Sfq时序电路综合计算方法、系统以及终端
CN113608491B (zh) * 2021-07-16 2022-09-02 广东财经大学 一种编译延时逻辑原理图到字节码方法
CN116108783B (zh) * 2023-04-04 2023-07-18 上海思尔芯技术股份有限公司 分块逻辑时序分析建模及处理方法、系统、设备及介质

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Also Published As

Publication number Publication date
DE60314530D1 (de) 2007-08-02
US6904576B2 (en) 2005-06-07
WO2004015596A2 (en) 2004-02-19
EP1546947B1 (en) 2007-06-20
WO2004015596A3 (en) 2004-06-03
US7962869B2 (en) 2011-06-14
JP4806529B2 (ja) 2011-11-02
EP1546947A2 (en) 2005-06-29
AU2003261401A1 (en) 2004-02-25
ATE365349T1 (de) 2007-07-15
US20080270958A1 (en) 2008-10-30
JP2005535965A (ja) 2005-11-24
US20040030999A1 (en) 2004-02-12

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