JP2005530161A5 - - Google Patents
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- JP2005530161A5 JP2005530161A5 JP2004513786A JP2004513786A JP2005530161A5 JP 2005530161 A5 JP2005530161 A5 JP 2005530161A5 JP 2004513786 A JP2004513786 A JP 2004513786A JP 2004513786 A JP2004513786 A JP 2004513786A JP 2005530161 A5 JP2005530161 A5 JP 2005530161A5
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- JP
- Japan
- Prior art keywords
- sequence
- circuit
- output
- digitized
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 claims 56
- 238000000034 method Methods 0.000 claims 32
- 238000004422 calculation algorithm Methods 0.000 claims 9
- 238000005457 optimization Methods 0.000 claims 7
- 238000004590 computer program Methods 0.000 claims 6
- 238000012544 monitoring process Methods 0.000 claims 3
- 238000005094 computer simulation Methods 0.000 claims 2
- 238000013500 data storage Methods 0.000 claims 2
- 238000001514 detection method Methods 0.000 claims 2
- 235000009854 Cucurbita moschata Nutrition 0.000 claims 1
- 240000001980 Cucurbita pepo Species 0.000 claims 1
- 235000009852 Cucurbita pepo Nutrition 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 claims 1
- 230000007547 defect Effects 0.000 claims 1
- 238000011156 evaluation Methods 0.000 claims 1
- 230000002068 genetic effect Effects 0.000 claims 1
- 238000012545 processing Methods 0.000 claims 1
- 235000020354 squash Nutrition 0.000 claims 1
- 230000004936 stimulating effect Effects 0.000 claims 1
- 238000010998 test method Methods 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBGB0213882.4A GB0213882D0 (en) | 2002-06-17 | 2002-06-17 | A digital system & method for testing analogue & mixed-signal circuits or systems |
| PCT/GB2003/002599 WO2003107019A2 (en) | 2002-06-17 | 2003-06-17 | A digital system and method for testing analogue and mixed-signal circuits or systems |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005530161A JP2005530161A (ja) | 2005-10-06 |
| JP2005530161A5 true JP2005530161A5 (cg-RX-API-DMAC10.html) | 2006-08-03 |
Family
ID=9938726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004513786A Pending JP2005530161A (ja) | 2002-06-17 | 2003-06-17 | アナログ信号及び混合信号の回路又はシステムを試験するためのデジ試験システムおよび試験方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7174491B2 (cg-RX-API-DMAC10.html) |
| EP (1) | EP1514125B1 (cg-RX-API-DMAC10.html) |
| JP (1) | JP2005530161A (cg-RX-API-DMAC10.html) |
| AT (1) | ATE521898T1 (cg-RX-API-DMAC10.html) |
| AU (1) | AU2003250369A1 (cg-RX-API-DMAC10.html) |
| GB (1) | GB0213882D0 (cg-RX-API-DMAC10.html) |
| WO (1) | WO2003107019A2 (cg-RX-API-DMAC10.html) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1382975B1 (en) * | 2002-07-19 | 2008-01-02 | Qimonda AG | Method of generating a test pattern for the simulation and/or test of the layout of an integrated circuit |
| US7823128B2 (en) * | 2004-04-19 | 2010-10-26 | Verigy (Singapore) Pte. Ltd. | Apparatus, system and/or method for combining multiple tests to a single test in a multiple independent port test environment |
| US20050278160A1 (en) * | 2004-06-14 | 2005-12-15 | Donnelly James M | Reduction of settling time in dynamic simulations |
| US7504975B2 (en) | 2006-03-24 | 2009-03-17 | Ics Triplex Technology Limited | Method and apparatus for output current control |
| US7476891B2 (en) | 2006-03-24 | 2009-01-13 | Ics Triplex Technology, Ltd. | Fault detection method and apparatus |
| US8166362B2 (en) | 2006-03-24 | 2012-04-24 | Rockwell Automation Limited | Fault detection method and apparatus for analog to digital converter circuits |
| US7688560B2 (en) | 2006-03-24 | 2010-03-30 | Ics Triplex Technology Limited | Overload protection method |
| DE602006020243D1 (de) * | 2006-03-24 | 2011-04-07 | Ics Triplex Technology Ltd | Überlastungsschutz für ein digitales Ausgangsmodul |
| US7613974B2 (en) | 2006-03-24 | 2009-11-03 | Ics Triplex Technology Limited | Fault detection method and apparatus |
| US7747405B2 (en) | 2006-03-24 | 2010-06-29 | Ics Triplex Technology Ltd. | Line frequency synchronization |
| US7729098B2 (en) | 2006-03-24 | 2010-06-01 | Ics Triplex Technology Limited | Overload protection method |
| US9459316B2 (en) | 2011-09-06 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for testing a semiconductor device |
| CN103064009B (zh) * | 2012-12-28 | 2015-03-11 | 辽宁大学 | 基于小波分析和有限高斯混合模型em方法的模拟电路故障诊断方法 |
| FI126901B (en) | 2014-09-12 | 2017-07-31 | Enics Ag | Method and system for testing an electronic unit |
| CN105223495A (zh) * | 2015-10-20 | 2016-01-06 | 国家电网公司 | 一种基于专家系统的模数混合电路故障诊断的测试方法 |
| US11199177B2 (en) | 2016-12-22 | 2021-12-14 | Vestas Wind Systems A/S | Detecting electrical failures in a wind turbine generator control system |
| JP6822281B2 (ja) * | 2017-03-31 | 2021-01-27 | 富士通株式会社 | 入力データ生成装置、方法及びプログラム |
| CN112444737B (zh) * | 2020-09-21 | 2021-10-22 | 电子科技大学 | 模拟电路故障参数范围确定方法 |
| CN112684282B (zh) * | 2020-11-12 | 2022-07-19 | 国网河北省电力有限公司电力科学研究院 | 配电网单相接地故障识别方法、装置及终端设备 |
| CN113051862B (zh) * | 2021-04-19 | 2022-07-26 | 电子科技大学 | 基于遗传算法的数模混合电路测试向量集优选方法 |
| US20230094919A1 (en) * | 2021-09-23 | 2023-03-30 | Hsinho Wu | Techniques for monitoring and control of high speed serial communication link |
| CN115099146B (zh) * | 2022-06-27 | 2025-08-29 | 上海集成电路装备材料产业创新中心有限公司 | 电路生成方法、装置、电子设备及存储介质 |
| CN115085194B (zh) * | 2022-07-20 | 2022-12-23 | 南方电网科学研究院有限责任公司 | 一种电力系统稳控策略生成方法、系统、装置及存储介质 |
| US20240219453A1 (en) * | 2023-01-03 | 2024-07-04 | Nxp B.V. | Test system for detecting faults in multiple devices of the same type |
| CN117970039B (zh) * | 2024-04-01 | 2024-06-04 | 山东大学 | 一种配电线路故障时刻检测方法 |
| CN118731656B (zh) * | 2024-09-02 | 2024-12-10 | 陕西星环聚能科技有限公司 | 隔离放大器测试方法和测试系统 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5694356A (en) * | 1994-11-02 | 1997-12-02 | Invoice Technology, Inc. | High resolution analog storage EPROM and flash EPROM |
| US5646521A (en) * | 1995-08-01 | 1997-07-08 | Schlumberger Technologies, Inc. | Analog channel for mixed-signal-VLSI tester |
| US5745409A (en) * | 1995-09-28 | 1998-04-28 | Invox Technology | Non-volatile memory with analog and digital interface and storage |
| US5793778A (en) * | 1997-04-11 | 1998-08-11 | National Semiconductor Corporation | Method and apparatus for testing analog and digital circuitry within a larger circuit |
| CA2206738A1 (en) * | 1997-06-02 | 1998-12-02 | Naim Ben Hamida | Fault modeling and simulation for mixed-signal circuits and systems |
| US6467058B1 (en) * | 1999-01-20 | 2002-10-15 | Nec Usa, Inc. | Segmented compaction with pruning and critical fault elimination |
| US20020188904A1 (en) * | 2001-06-11 | 2002-12-12 | International Business Machines Corporation | Efficiency of fault simulation by logic backtracking |
| US6898746B2 (en) * | 2001-06-19 | 2005-05-24 | Intel Corporation | Method of and apparatus for testing a serial differential/mixed signal device |
-
2002
- 2002-06-17 GB GBGB0213882.4A patent/GB0213882D0/en not_active Ceased
-
2003
- 2003-06-17 AT AT03760088T patent/ATE521898T1/de not_active IP Right Cessation
- 2003-06-17 EP EP03760088A patent/EP1514125B1/en not_active Expired - Lifetime
- 2003-06-17 AU AU2003250369A patent/AU2003250369A1/en not_active Abandoned
- 2003-06-17 US US10/518,743 patent/US7174491B2/en not_active Expired - Lifetime
- 2003-06-17 WO PCT/GB2003/002599 patent/WO2003107019A2/en not_active Ceased
- 2003-06-17 JP JP2004513786A patent/JP2005530161A/ja active Pending
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