JP2005522052A - Field effect transistor with lateral depletion structure - Google Patents

Abstract

Field effect transistor devices and methods of manufacturing field effect transistor devices are disclosed. The field effect transistor device includes a stripe trench extending from the main surface of the semiconductor substrate into the semiconductor substrate at a predetermined depth. The stripe trench includes a semiconductor material of a second conductivity type for forming a PN junction at an interface formed with respect to the semiconductor substrate.

Description

(Field of Invention)
Embodiments of the present invention relate to field effect transistors, such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices, and methods of manufacturing field effect transistors.

(Background of the Invention)
Power MOSFET devices are well known and are used in many applications. Typical applications include automotive electronic devices, portable electronic devices, power supplies, and telecommunications. One important electrical characteristic of a power MOSFET device is its drain-source on-resistance (R _{DS (on)} ), which is defined as the total resistance that the drain current encounters. R _{DS (on)} is proportional to the amount of power consumed while the MOSFET device is on. In a vertical power MOSFET device, this total resistance is comprised of several resistive components such as an inverted channel resistance ("channel resistance"), initial substrate resistance, epitaxial portion resistance, and other resistances. . The epitaxial portion is typically in the form of a layer and may be referred to as an “epitaxial layer”. R _{DS (on)} can be reduced by reducing the resistance of one or more of these MOSFET device components.

It is desirable to reduce _{RDS (on)} . For example, reducing _{RDS (on)} of a MOSFET device reduces power consumption and wasteful heat dissipation. The reduction in R _{DS (on)} of a MOSFET device preferably occurs without adversely affecting other MOSFET characteristics such as the device's maximum breakdown voltage (BV _DSS ). At this maximum breakdown voltage, the reverse-biased epitaxial / well diode in the MOSFET is destroyed, resulting in a significant and uncontrollable current flow between the source and drain.

It is also desirable to maximize the breakdown voltage of the MOSFET device without increasing _{RDS (on)} . The breakdown voltage of a MOSFET device can be reduced, for example, by increasing the resistivity of the epitaxial or by increasing the thickness of the epitaxial layer. However, increasing the thickness of the epitaxial layer or the resistivity of the epitaxial layer will undesirably increase _{RDS (on)} .

It would be desirable to provide a MOSFET device with a high breakdown voltage and a low R _{DS (on)} . Embodiments of the present invention address this and other issues.

(Summary of Invention)
Embodiments of the present invention are directed to MOSFET devices and methods of manufacturing the same. This MOSFET device has a low R _{DS (on)} and a high breakdown voltage. For example, with respect to the current state of the art, in an embodiment of the invention, a typical 200V N-channel trench MOSFET has a higher R _{DS (on)} than a conventional 200V N-channel trench MOSFET. It can be reduced by 80% while maintaining the breakdown voltage.

  According to an embodiment of the present invention, a first conductivity type semiconductor substrate having a main surface and a drain region, a second conductivity type well region formed in the semiconductor substrate, and a well region are formed. An electric field composed of a first conductivity type source region, a trench gate electrode formed adjacent to the source region, and a stripe trench extending from the main surface to the semiconductor substrate at a predetermined depth. It is aimed at effect transistor devices. The stripe trench includes a semiconductor material of a second conductivity type that forms a PN junction at the interface formed with respect to the semiconductor substrate.

  Another embodiment of the present invention includes a step of forming a second conductivity type well region in a first conductivity type semiconductor substrate including a main surface and a drain region, and a first conductivity type in the well region. Forming a mold source region, forming a trench gate electrode adjacent to the source region, and forming a stripe trench extending from the main surface of the semiconductor substrate toward the semiconductor substrate at a predetermined depth. The present invention is directed to a method of forming a field effect transistor device including a step and a step of depositing a semiconductor material of a second conductivity type in the stripe trench.

  Still another embodiment of the present invention includes: a) forming a second conductivity type well region in a first conductivity type semiconductor substrate including a main surface and a drain region; and b) in the well region. Forming a first conductivity type source region; c) forming a gate electrode adjacent to the source region; and d) extending from the semiconductor substrate main surface toward the semiconductor substrate at a predetermined depth. Forming a stripe trench; and e) depositing a second conductivity type semiconductor material in the stripe trench, wherein at least one of steps a), b), and c) is step e. ) Is directed to a method of forming a field effect transistor performed after.

  These and other embodiments of the invention are described in more detail below with respect to the accompanying drawings.

(Description of specific examples)
The inventor has found that the epitaxial layer in the MOSFET becomes an increasingly important component of R _{DS (on)} which increases the MOSFET voltage breakdown rating. Computer simulation shows that, for example, for a 30V N-channel trench MOSFET device, the resistance of the epitaxial layer is about 30% or more of the total intrinsic _{RDS (on)} . In another example, for a 200V N-channel trench MOSFET device, the resistance of the epitaxial layer is 75-90% of the total intrinsic R _{DS (on)} . Therefore, it is desirable to reduce the resistance of the epitaxial layer, and hence the RDS _(on) of the corresponding MOSFET device, especially for higher voltage applications. The reduction of R _{DS (on)} preferably occurs without degrading the breakdown voltage characteristics of the MOSFET device.

In order to illustrate the embodiments of the present invention, an example with a number of reference numbers is shown. In the present specification, it should be understood that the embodiments indicated by reference numbers such as breakdown voltage, _{RDS (on),} etc. are provided for illustrative purposes only. These and other numbers or values in this application may vary significantly or slightly depending on the semiconductor manufacturing process used and in particular with future advances in semiconductor processing.

Under normal operating conditions, the maximum breakdown voltage (BV _DSS ) of a trench or planar MOSFET (double diffused metal oxide semiconductor field effect transistor) is It is obtained by forming a depletion region at the interface between. This depletion region is formed by applying a reverse bias voltage across the junction. At the breakdown voltage, the epitaxial layer / well diode to which the reverse bias voltage is applied collapses and significant current begins to flow. Current flows between the source and drain by an avalanche doubling process, while the gate and source are shorted together.

  The formation of a depletion region in a conventional trench MOSFET device can be described with respect to FIGS. 1 (a) -1 (f). These figures show a schematic cross-sectional view of a conventional vertical trench MOSFET device. Each cross section shows a plurality of gate structures 45 on the main surface of the semiconductor substrate 29. The semiconductor substrate 29 includes an N− epitaxial layer 32 and a drain region 31. In FIG. 1A, an N + source region, a P− well, and a P + body region are shown. To clearly explain the horizontal depletion effect, the N + source region and the P + body region are shown in FIGS. 1 (b) -1 (f), 2 (a) -2 (f), and 3 (a) -3 (f ) Is not shown.

In this embodiment, the N-epitaxial layer 32 has a resistivity of about 5.0 Ω · cm, and the dopant concentration N _d (epi) of the epitaxial layer is about 1 × 10 ¹⁵ / cm ⁻³ . The thickness of the N-epitaxial layer 32 is about 20 microns. The device also has an “effective” thickness (sometimes referred to as an “effective epitaxial layer”) of the epitaxial layer of about 16.5 μm. The “effective” thickness of this epitaxial layer is the thickness of the epitaxial layer after considering any upward diffusion from the formation of regions such as the N + drain region 31 and the doped region (eg, P-well) in the semiconductor substrate 29. It is. For example, the effective epitaxial layer thickness is substantially the distance between the bottom of the P + body or P-well and the terminal end of any upwardly diffused donor in the N-epitaxial layer 32 from the N + substrate 31. Can be equal. The effective epitaxial layer of the device may also include the drift region of the device.

Each of FIGS. 1A to _1F shows a maximum electric field (“E _max ”) established when a different reverse bias voltage is applied. As shown, as the reverse bias voltage increases, E _max also increases. Avalanche breakdown occurs when E _max exceeds the critical electric field for a given dopant concentration. For this reason, it is preferable that _Emax is lower than this critical electric field.

1 (a) -1 (f) show how the depletion region 50 appears when reverse bias voltages increasing to 0V, 10V, 50V, 100V, 200V, and 250V are applied to a conventional trench MOSFET device. Each indicates whether to expand. As shown, the depletion region 50 extends “perpendicularly” from the P-well / epitaxial layer interface in the direction of the N + drain region 31 as a larger reverse bias voltage is applied. This vertical growth of the depletion region places a trade-off between lower R _{DS (on)} and higher BV _{DSS in} conventional trench MOSFET devices.

The present invention provides an improved MOSFET device in which the depletion region first extends “horizontally” as a higher reverse bias voltage is applied. In embodiments of the present invention, a number of additional (and preferably deep) trenches are formed in the semiconductor substrate. These deep trenches are ultimately used to form stripes that include the formation of horizontally extending depletion regions. The stripe includes a conductive material of the type opposite to the epitaxial layer. For example, the stripe may include a P-type material (eg, P, P +, or P-silicon) and the epitaxial layer may include an N-type material. Individual stripes may exist between adjacent gates and may extend from the main surface of the semiconductor substrate toward the epitaxial layer. The stripe can also extend to the epitaxial layer by any suitable distance. For example, in some embodiments, the stripe extends all the way to the epitaxial layer / well region interface. The presence of stripes allows the use of lower resistance epitaxial layers without exceeding the critical electric field. As described in more detail below, R _{DS (on)} can be reduced without adversely affecting the characteristics of other MOSFET devices, such as breakdown voltage.

  2 (a) to 2 (f) show an embodiment of the present invention. These figures show how the depletion region expands as a larger reverse bias voltage is applied. The voltages applied to the embodiments shown in FIGS. 2 (a) -2 (f) are 0V, 1V, 2V, 10V, 200V, and 250V. Similar to the conventional trench MOSFET device shown in FIGS. 1 (a) -1 (f), each of the cross-sections of FIGS. 2 (a) -2 (f) includes a plurality of trench gate structures 45 and an N-epitaxial structure. Layer 32 is included. N-epitaxial layer 32 is present on semiconductor substrate 29.

  However, in FIGS. 2A to 2F, a plurality of trenches that form stripes 35 (for example, P stripes) opposite to the N-epitaxial layer 32 are formed between adjacent gate structures 45, respectively. Has been placed. In this embodiment, stripe 35 includes a P-type material. As shown in FIGS. 2 (a) to 2 (c), as a larger reverse bias voltage is applied, the depletion region 50 first extends “horizontally” away from both sides of the stripe 35. As the depletion region 32 spreads from the side surface of the adjacent stripe 35, charge carriers are rapidly consumed in the region between the adjacent stripes 35. After the charge carriers are rapidly consumed in the region between the adjacent stripes 35, the depletion region 50 extends perpendicularly from the end of the stripe 35 toward the N + drain region 31. In the epitaxial layer 32 of this embodiment, charge carriers are more rapidly generated than in the case where the consumption first occurs in the “vertical” direction (for example, as shown in FIGS. 1A to 1F). Is consumed. As shown in FIG. 2 (c) (reverse bias voltage = 2V) and FIG. 1 (e) (reverse bias voltage = 200V), the depletion region 50 is similar in the area of a significantly lower applied voltage (2V compared to 200V). doing.

3 (a) -3 (f) show cross-sections of another MOSFET device of another embodiment of the present invention. In these figures, similar components are indicated using similar reference numbers above. However, unlike the MOSFET device described in the previous figure, the epitaxial layer 50 in the MOSFET device shown in FIGS. 3 (a) -3 (f) has a resistivity of about 0.6 Ω · cm, about 1 × It has a dopant concentration (N _d ) of 10 ¹⁶ / cm ⁻³ , a thickness of about 16 μ, and an effective thickness of the epitaxial layer of about 12.5 μ.

FIGS. 3A to 3F show how the depletion region 50 changes at reverse bias voltages of 0V, 10V, 50V, 100V, 200V, and 250V. Similar to the MOSFET device embodiment shown in FIGS. 2 (a) -2 (f), the depletion region 50 first expands "horizontally" as a higher reverse bias voltage is applied. Also, in this example, the maximum electric field (E _max ) of each applied reverse bias voltage does not exceed the critical field of avalanche breakdown for the dopant concentration. Therefore, a higher breakdown voltage (eg, 250V) can be obtained while using a thinner and lower resistivity. Advantageously, a thinner and lower resistivity epitaxial layer results in a lower resistivity epitaxial layer and thus a reduced value of _{RDS (on)} . The dimensions and doping levels within the stripe 35 are adjusted to balance the total charge of the stripe with the total charge of the depletion region 50 of the epitaxial layer.

As described above, as the breakdown voltage ratio of a MOSFET device increases, it becomes a component that significantly increases the total intrinsic R _{DS (on)} . For example, FIG. 4 is a bar graph showing some components of a number of N-channel MOSFET devices having different breakdown voltage ratios. Graph (a) shows the RDS _(on) of the control N-channel 30V MOSFET device at 500A. Graphs (b)-(f) show conventional trench N-channel MOSFET devices with breakdown voltages of 60, 80, 100, 150, and 200V, respectively. As is apparent from FIG. 4, as the breakdown voltage increases, the resistance of the epitaxial layer has a greater influence _on R _{DS (on)} . For example, in the example of a conventional 200V N-channel MOSFET device, the resistance of the epitaxial layer constitutes more than 90% of the total intrinsic R _{DS (on)} . In contrast, in the 30V N-channel MOSFET device example, the resistance of the epitaxial layer has a significantly lower effect _on R _{DS (on)} .

In embodiments of the present invention, the resistance of the epitaxial layer can be reduced by incorporating trench stripes in the epitaxial layer. This reduces R _{DS (on)} compared to similar conventional MOSFET devices with similar breakdown voltage ratios. For example, graph (g) of FIG. 4 shows the improvement provided for the trench MOSFET of an exemplary embodiment of the present invention. As shown, the resistance of the epitaxial layer can be significantly reduced when using a trench stripe with an epitaxial layer of the opposite conductivity type in the MOSFET device. As shown in graph (g), the total intrinsic R _{DS (on)} of the 200V N-channel trench MOSFET device is less than 1.4 mΩ · cm ² . In contrast, for a conventional 200V N-channel trench MOSFET without stripes of opposite conductivity type, the total intrinsic R _{DS (on)} is about 7.5 mΩ · cm ² . Thus, these exemplary embodiments of the present invention may exhibit a _{RDS (on)} reduction of more than 5 times compared to conventional trench MOSFET devices.

  5 to 11 show graphs of IV curves when a reverse bias is applied to the MOSFET device according to the embodiment of the present invention.

  FIG. 5 is a graph showing IV curves when a reverse bias is applied to a conventional trench MOSFET device and a MOSFET device according to an embodiment of the present invention. FIG. 5 shows IV curves 500, 502 for two MOSFET devices without P-stripe. The first curve 500 is for a MOSFET device having an epitaxial layer resistivity of 0.8 mΩ · cm and an epitaxial layer thickness of 15 μm. The second curve 502 is for a MOSFET device having an epitaxial layer resistivity of 4.6 mΩ · cm and an epitaxial layer thickness of 19.5μ. As expected, MOSFET devices with thinner epitaxial layers and higher resistivity have higher breakdown voltages.

An IV curve 504 of one embodiment of the present invention is also shown in FIG. This exemplary embodiment has an epitaxial layer resistance of about 0.8 Ω · cm, an epitaxial layer thickness of about 15 μm, and a P-stripe of about 12 μ depth. As the IV curve 504 shows, in this device embodiment, the epitaxial layer is relatively thin and the resistivity of the epitaxial layer is relatively low (hence _{RDS (on)} is low). This device embodiment also has a breakdown voltage of 220V. This breakdown voltage is comparable to that of conventional MOSFET devices having thicker, more resistive epitaxial layers.

FIG. 6 shows an IV curve when a reverse bias is applied to the MOSFET device of the embodiment of the present invention. This curve shows the effect of P-stripe depth variation on BV _DSS . In these devices, the epitaxial layer has a resistance of about 0.8 Ω · cm and a thickness of about 13μ. The width of the P-stripe is about 1.0 μm. The dopant concentration of the P-stripe is about 2.2 × 10 ¹⁶ / cm ⁻³ . The depth of the P-stripes varied at about 8, 10, and 12μ. These variation IV curves show that the breakdown voltage increases as the depth of the P-stripe increases.

FIG. 7 shows an IV curve when a reverse bias is applied to the MOSFET device according to the embodiment of the present invention. This curve shows the effect of P-stripe width variation on BV _DSS . In this example, the device has an epitaxial layer resistance of about 0.8 Ω · cm and a thickness of about 13μ. The depth of the P-stripe is about 10 μm, and the dopant concentration of the P-stripe is about 2.2 × 10 ¹⁶ / cm ⁻³ . P-striped IV curves with widths of about 0.8, 1.0, and 1.2 microns are shown. This IV curve shows that the breakdown voltage is higher when the width of the P-stripe is equal to 1μ.

  Embodiments of the present invention can be applied to trench and planar MOSFET technology. However, trench MOSFET devices are preferred when they advantageously occupy less space than planar MOSFETs. In any case, the breakdown voltage of the device may be about 100 to about 400 volts in some embodiments. For purposes of explanation, a method for fabricating a MOSFET device of the present invention is described below with respect to a trench gate process.

  A detailed view of a power trench MOSFET device according to one embodiment of the present invention is shown in FIG. The power trench MOSFET device comprises a semiconductor substrate 29 having a drain region 31 and an N-epitaxial region 32 adjacent to the drain region. The semiconductor substrate 29 can comprise any suitable semiconductor material including Si, GaAs, and the like. The drift region of the MOSFET device may be in the epitaxial region 32 of the semiconductor substrate 29. A plurality of gate structures 45 are adjacent to the main surface 28 of the semiconductor substrate 29, and each gate structure 45 includes a gate electrode 43 and a dielectric layer 44 on the gate electrode 43. A plurality of N + source regions 36 are formed in the semiconductor substrate 29. Each N + source region 36 is adjacent to one of the gate structures 45 and is formed in a plurality of P-well regions 34, which are also formed in the semiconductor substrate 29. Each P-well region 34 is disposed adjacent to one of the gate structures 45. A contact 41 of the source region 36 exists on the main surface 28 of the semiconductor substrate 29. This contact 41 may comprise a metal such as aluminum. For clarity, other components that may be present in the MOSFET device (eg, a passivation layer) may not be shown in FIG. 8 (d).

  In FIG. 8D, the trench P-stripe 35 exists in the semiconductor substrate 29. When the gate structures 45 form an array of gate structures 45, a plurality of P-stripes 35 can each be disposed between adjacent gate structures 45. The P-stripe 35 shown in FIG. 8D is disposed between adjacent gate structures 45. As shown in the figure, the P-stripe 35 shown in the figure is substantially vertical and substantially perpendicular to the direction of the semiconductor substrate 29. A P-stripe 35 extends beyond the gate structure 45 and may penetrate most of the N-epitaxial portion 32. The N-epitaxial portion 32 of this embodiment surrounds the bottom and sides of the P-stripe 35. The dopant concentration on both sides of the P-stripe 35 and below it may be similar in this embodiment. Preferably, the P-stripes 35 have substantially parallel sidewalls and a substantially planar bottom. If the sidewalls are substantially parallel, a thin P-stripe 35 can exist between adjacent gate structures 45. Thus, the spacing between the gates 45 can be minimized to a reduced size MOSFET array. In an exemplary embodiment of the invention, the spacing of the gate structures 45 (or gate electrodes) may be less than about 10 microns (eg, between about 4-6 microns). The width of P-stripe 35 may be less than 2 or 3 microns (eg, about 1-2 microns).

  The stripe trenches of embodiments of the present invention are filled or lined with a doping material opposite to the epitaxial portion in the semiconductor substrate. One example of this type is shown in FIG. 8 (e) and is described in more detail below. When the stripe is lined with a material of the opposite conductivity type to the epitaxial portion, the stripe may include an inner dielectric portion and an outer semiconductor layer of the opposite conductivity type to the epitaxial portion. For example, the inner dielectric portion may include silicon oxide or air, while the outer semiconductor layer may include P or N type epitaxial silicon.

  Also, the presence of doped stripes may be used as a heavy body to improve the durability of the formed device. For example, like the presence of a P-type heavy body in the epitaxial layer, the presence of P-stripe penetrating the epitaxial layer is believed to stabilize device voltage fluctuations, thereby improving device reliability.

  A suitable method of forming the power trench MOSFET device of the present invention may be described with respect to FIGS. 8 (a) -8 (d).

  Referring to FIG. 8A, a structure including a semiconductor substrate 29 is provided. The semiconductor substrate 29 may include an N + drain region 31 and an N− epitaxial portion 32. A gate trench 30 is formed adjacent to the main surface 28 of the semiconductor substrate 29. These gate trenches 30 may be formed using, for example, an anisotropic etching method well known in the art. After the gate trench 30 is formed, a gate structure 45 is formed in the gate trench 30 using methods well known in the art. Each gate structure 45 includes a dielectric layer 44 and a gate electrode 43. The gate electrode 43 may include polysilicon, and the dielectric layer 44 may include silicon oxide.

  Also, source regions, well regions, and other structures can be formed in the semiconductor substrate 29 before or after forming the gate structure 45. Referring to FIG. 8B, a P− well region 34 is formed in the semiconductor substrate 29, and then an N + source region 36 is formed in the semiconductor substrate 29. These regions may be formed using conventional ion implantation or diffusion processes. In this embodiment, these doped regions are formed after the gate structure 45 is formed.

  Further details regarding the formation of the well region, gate region, source region, and heavy body can be found in Brian Sze-KI Mo, Duc Chau, Steven Sapp, Izak Benculia, and Dean Edward Probst, “Field Effect Transistors and Manufacturing Methods (Field In US patent application Ser. No. 08 / 970,221 entitled “Effect Transistor and Methods of Its Manufacture”. This application is assigned to the same assignee as the present assignee and is incorporated herein by reference in its entirety for all purposes.

  In the preferred embodiment, one or more stripe trenches 30 are formed in the semiconductor substrate 29 after the source region, well region, and / or gate structure is formed. For example, after the P-well region 34, the N + source region 36, and the gate structure 45 are formed, the stripe trench 30 shown in FIG. 8C can be formed using, for example, an anisotropic etching process. . The formed stripe trench 30 extends from the main surface 28 of the semiconductor substrate 29. Striped trench 30 may extend through gate structure 45 over any suitable distance to the interface between epitaxial portion 32 and drain region 31. Preferably, the stripe trench 30 (and also the stripe material disposed therein) terminates at a depth that is between half the thickness of the N-epitaxial portion 32 and the entire thickness of the epitaxial portion 32. For example, the stripe trench 30 can extend to the interface between the epitaxial portion 32 and the drain region 31.

  After the stripe trench 30 is formed, a stripe 35 is formed in the stripe trench 30 as shown in FIG. The stripe 35 includes a second conductivity type material. In an embodiment of the present invention, the second conductivity type material is an epitaxial material such as epitaxial P-type silicon (eg, P, P +, P-silicon). The stripe trench 30 may be filled using any suitable method such as a selective epitaxial growth (SEG) process. For example, trench 30 may be filled with epitaxial silicon using in situ doping.

  The material of the second conductivity type can completely fill the stripe trench 30 as shown in FIG. 8 (d), or can line the stripe trench 35 as shown in FIG. 8 (e). In FIG. 8 (e), the same reference numerals represent the same components as in FIG. 8 (d). However, in this embodiment, stripe 35 includes P-layer 35 (a) and internal dielectric material 35 (b). First, P-layer 35 (a) may be formed in the formed stripe trench, and then dielectric material 35 (b) is deposited to fill the enclosure formed by P-layer 35 (a). obtain. Alternatively, the inner dielectric material may be formed by oxidizing the P-layer 35 (a). The dielectric layer 35 (b) may include a material such as silicon oxide or air.

  Other materials that may be used to form stripes of doped epitaxial material in the trench are described by Gordon Madsen and Joele Sharp, “Method of Manufacturing A Trench MOSFET Using Selective Growth Epitaxy. US patent application Ser. No. 09 / 586,720 entitled “Usine Selective Growth Epitaxy”. This application is assigned to the same assignee as the present assignee and is incorporated herein by reference in its entirety for all purposes.

  As described above, the stripe trenches 30 and the stripes 35 of the second conductivity type are preferably formed after at least one of the source region 36, the gate structure 45, and the well region 34 is formed. By forming the stripe 35 after these device elements are formed, the stripe 35 is not exposed to the high temperature processing used to form the gate structure 45 or the P-well region 34. For example, the high temperature processing (eg, ion implantation high temperature drive) used to form the P-well region can last for 1-3 hours at high temperature conditions (eg, greater than 1100 degrees). On the other hand, forming the P− stripe 35 in the semiconductor substrate 29 does not adversely affect the previously formed gate structure 45, P− well region 34, or N + source region 36. If these device elements are formed before the P-stripe 35 is formed, the possibility that the P-stripe 35 in the epitaxial layer diffuses and its shape is lost due to prolonged high-temperature processing steps is reduced. Is done. If this condition occurs, the width of the P-stripe 35 cannot be uniform below the P-stripe 35, and the effectiveness of the formed device can be reduced. For example, the laterally spread-dopant from the stripe 35 may diffuse toward the channel region of the MOSFET device, thereby affecting the threshold voltage characteristics of the MOSFET device. Furthermore, wider P-stripe widths can result in greater spacing between the gate structures 45, thus increasing the size of the corresponding array of gate structures 45.

  After the P-stripe 35 is formed, additional layers of material may be deposited. Additional layers may include a metal contact layer 41 and a passivation layer (not shown). These additional layers may be formed using any suitable method known in the art.

  While many specific embodiments have been illustrated and described, embodiments of the present invention are not limited thereto. For example, embodiments of the present invention have been described for N-type semiconductors, P-stripes, and the like. It will be understood that the invention is not limited thereto and that the doping polarity of the structures shown and described can be reversed. Also, although P-stripe is shown in detail, it is understood that the stripe used in the embodiments of the present invention may be P or N type. Also, stripes or other device elements may have an acceptor concentration or a donor concentration (eg, +, ++, −, −−, etc.).

  The terms and expressions employed herein are used as descriptive terms and not as limiting terms, and such terms and expressions are intended to exclude equivalents or portions of the features shown and described. It will be understood that various modifications are possible without departing from the scope of the claimed invention. Furthermore, any one or more features of any embodiment of the present invention may include any one or more other features of any other embodiment of the present invention without departing from the scope of the present invention. May be combined.

1 is a schematic cross-sectional view illustrating a conventional vertical trench MOSFET device. This figure shows a depletion region extending vertically as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a conventional vertical trench MOSFET device. This figure shows a depletion region extending vertically as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a conventional vertical trench MOSFET device. This figure shows a depletion region extending vertically as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a conventional vertical trench MOSFET device. This figure shows a depletion region extending vertically as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a conventional vertical trench MOSFET device. This figure shows a depletion region extending vertically as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a conventional vertical trench MOSFET device. This figure shows a depletion region extending vertically as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 1 is a schematic cross-sectional view illustrating a vertical trench MOSFET device according to one embodiment of the present invention. This figure shows a depletion region extending horizontally as a reverse bias voltage is applied. 6 is a bar graph showing various resistance components that make up _{RDS (on)} of various MOSFET devices for different breakdown voltage ratios. It is a graph which shows the comparison with IV curve at the time of reverse bias application of the conventional trench MOSFET device and IV curve at the time of reverse bias application of the trench MOSFET device of one Example of this invention. It is a graph which shows IV curve at the time of reverse bias application of trench MOSFET which has different P-stripe depth. This curve shows the effect of varying P-stripe depth on the BV _DSS . It is a graph which shows IV curve at the time of reverse bias application of trench MOSFET which has different P-stripe width. This curve shows the effect of varying P-stripe width on BV _DSS . FIG. 3 is a cross-sectional view illustrating a method of forming a MOSFET device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a method of forming a MOSFET device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a method of forming a MOSFET device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a method of forming a MOSFET device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a MOSFET device with a P-backing and a stripe having a dielectric interior portion.

Claims (26)

A field effect transistor device comprising:
A first conductivity type semiconductor substrate having a main surface and a drain region;
A second conductivity type well region formed in the semiconductor substrate;
A source region of the first conductivity type formed in the well region;
A trench gate electrode formed close to the source region;
A stripe trench extending from the main surface of the semiconductor to the semiconductor substrate at a predetermined depth; A field effect transistor device comprising a stripe trench containing a semiconductor material of two conductivity types.   2. The field effect transistor device of claim 1, wherein the first conductivity type includes an N type and the second conductivity type includes a P type.   The field effect transistor device of claim 1, wherein the gate electrode comprises polysilicon.   The field effect transistor device of claim 1, wherein the stripe trench extends from the main surface to the drain region.   The field effect transistor device of claim 1, wherein the device is a power MOSFET having a breakdown voltage between about 100 volts and about 400 volts.   The field effect transistor device of claim 1, wherein the stripe trench includes a dielectric material that lines the stripe trench, and the semiconductor material of the second conductivity type is disposed in the liner.   The field effect transistor device of claim 1, wherein the semiconductor substrate includes an epitaxial portion.   The field effect transistor device of claim 7, wherein the epitaxial portion has a thickness of less than about 40 microns.   The field effect transistor device of claim 7, wherein the epitaxial portion includes a drift region.   The field effect transistor device of claim 7, wherein the epitaxial portion has a low efficiency of less than 14 Ω · cm.   The field effect transistor device of claim 1, wherein the drain region comprises an N + semiconductor material. A method of manufacturing a field effect transistor device comprising:
Forming a second conductivity type well region in a first conductivity type semiconductor substrate, the semiconductor substrate having a main surface and a drain region;
Forming a source region of the first conductivity type in the well region;
Forming a trench gate electrode proximate to the source region;
Forming a stripe trench extending from the main surface of the semiconductor to a half depth in the conductor substrate;
Depositing the second conductivity type semiconductor material into the stripe trench.   The method of claim 12, wherein the step of forming the stripe trench is performed after forming the source region.   The method of claim 12, wherein the first conductivity type comprises an N type and the second conductivity type comprises a P type.   The method of claim 12, wherein the semiconductor substrate has a direction, and the stripe trench is perpendicular to the direction of the semiconductor.   The method of claim 12, wherein the gate electrode comprises polysilicon.   The method of claim 12, wherein the second conductivity type semiconductor material comprises epitaxial silicon.   The method of claim 12, wherein forming the stripe trenches is performed after the gate structure, the well region, and the source region are formed.   The method of claim 12, wherein the method includes depositing a dielectric material in the stripe trench. A method of manufacturing a field effect transistor device comprising:
a) forming a second conductivity type well region in a first conductivity type semiconductor substrate having a main surface and a drain region;
b) forming a source region of the first conductivity type in the well region;
c) forming a gate electrode adjacent to the source region;
d) forming a stripe trench extending from the main surface of the semiconductor halfway into the conductor substrate at a predetermined depth;
e) depositing the semiconductor material of the second conductivity type in the stripe trench;
A method of forming a field effect transistor device, wherein at least one of steps a), b), and c) is performed after step e).   21. The method of claim 20, wherein steps d) and e) are performed after steps a), b), and c).   21. The method of claim 20, wherein the gate electrode is a trench gate electrode.   21. The method of claim 20, wherein the first conductivity type comprises an N type and the second conductivity type comprises a P type.   21. The method of claim 20, wherein forming the stripe trench includes anisotropic etching.   21. A field effect transistor device manufactured according to the process of claim 20.   The field effect transistor device of claim 1, wherein the stripe trench extends through the well region.

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