JP2005353859A - Exfoliation method of semiconductor wafer - Google Patents

Exfoliation method of semiconductor wafer Download PDF

Info

Publication number
JP2005353859A
JP2005353859A JP2004173322A JP2004173322A JP2005353859A JP 2005353859 A JP2005353859 A JP 2005353859A JP 2004173322 A JP2004173322 A JP 2004173322A JP 2004173322 A JP2004173322 A JP 2004173322A JP 2005353859 A JP2005353859 A JP 2005353859A
Authority
JP
Japan
Prior art keywords
wafer
adhesive material
semiconductor wafer
support
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2004173322A
Other languages
Japanese (ja)
Inventor
Mitsuo Ueno
光生 上野
Yukiji Akiyama
雪治 秋山
Kazuma Tanida
一真 谷田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Rohm Co Ltd
Taiyo Yuden Co Ltd
Original Assignee
Renesas Technology Corp
Rohm Co Ltd
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Rohm Co Ltd, Taiyo Yuden Co Ltd filed Critical Renesas Technology Corp
Priority to JP2004173322A priority Critical patent/JP2005353859A/en
Publication of JP2005353859A publication Critical patent/JP2005353859A/en
Ceased legal-status Critical Current

Links

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide the exfoliation method of a semiconductor wafer capable of preventing the wafer from being damaged in the case of exfoliating the wafer from a support. <P>SOLUTION: In the method, a second adhesive material 26 is adhered to a side of the semiconductor wafer 30 adhered to the support 20 via a first adhesive material 28, the side of the semiconductor wafer 30 opposite to the adhering side of the semiconductor wafer 30 and the side of the second adhesive material is bent concavely to exfoliate the semiconductor wafer from the support. A relation of E1×h1>E2×h2 holds, wherein E1 is the Young's modulus of the first adhesive material, h1 is the thickness thereof, E2 is the Young's modulus of the second adhesive material, and h2 is the thickness thereof. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、ウェハを保持する支持体からの半導体ウェハの剥離方法に関する。   The present invention relates to a method for peeling a semiconductor wafer from a support that holds the wafer.

現在、電子機器は広範囲に普及しているが、携帯電話機等にはさらなる小型高機能化が求められており、これら電子機器に搭載される半導体素子(デバイス)もますます小型高機能化が要求されている。又、電子タグ等の極薄デバイスの開発も進んでいる。
そして、デバイスの小型高機能化を図る方法として、デバイスを極薄化して積層する3次元実装モジュールが提唱されている。このモジュールとしては、半導体ウェハの表面に回路を形成した後、裏面を研削してウェハを薄くし(例えば、口径200mmの半導体ウェハの場合、100μm厚以下)、さらに、研削後の裏面に回路形成するものが想定されている。また、ウェハ表面に回路を形成し、次にウェハ表裏の回路を接続するビアプラグを形成し、裏面を厚み50μm以下に研削した後、裏面に回路形成するモジュールも想定されている(例えば、非特許文献1、2参照)。
At present, electronic devices are widespread, but mobile phones are required to be smaller and more functional, and semiconductor elements (devices) mounted on these electronic devices are increasingly required to be smaller and more functional. Has been. Development of ultra-thin devices such as electronic tags is also progressing.
A three-dimensional mounting module in which a device is extremely thinned and stacked has been proposed as a method for reducing the size and increasing the functionality of the device. As this module, after forming a circuit on the surface of the semiconductor wafer, the back surface is ground to thin the wafer (for example, in the case of a semiconductor wafer having a diameter of 200 mm, the thickness is 100 μm or less), and the circuit is formed on the back surface after grinding. What is supposed to be. A module is also envisaged in which a circuit is formed on the back surface after forming a circuit on the wafer surface, then forming via plugs for connecting the wafer front and back circuits, grinding the back surface to a thickness of 50 μm or less (for example, non-patent References 1 and 2).

ところで、従来から半導体ウェハを薄くするため、ウェハ裏面を研削するバックグラインドが行われているが、ウェハが破損しやすいことから、ウェハを支持体に接着して加工を行うのが一般的である。一方、支持体からウェハを剥離する方法として、支持体とウェハをワックスで接着し、加工後にワックスを加熱軟化させて剥離する方法や、ウェハの縁にスクレーパを押し当てて剥離させる方法が知られている(例えば、特許文献1参照)。   By the way, in order to reduce the thickness of a semiconductor wafer, back grinding is conventionally performed to grind the back surface of the wafer. However, since the wafer is easily damaged, it is common to perform processing by bonding the wafer to a support. . On the other hand, as a method of peeling the wafer from the support, there are known a method in which the support and the wafer are bonded with wax, and the wax is heated and softened after processing to peel off, and a method in which the scraper is pressed against the edge of the wafer and peeled off. (For example, refer to Patent Document 1).

しかし、ウェハが薄くなるにつれて、上記した剥離方法ではウェハの破損を防止できなくなってきた。このため、支持体とウェハをUV硬化樹脂で接着し、加工後にUV光を照射して樹脂の接着力を弱めてウェハを剥離する技術や、支持体である保持プレートを湾曲させてウェハを剥離させる技術が報告されている(例えば、特許文献2、3参照)。   However, as the wafer becomes thinner, the above-described peeling method cannot prevent the wafer from being damaged. For this reason, the support and the wafer are bonded with UV curable resin, and after processing, the wafer is peeled off by irradiating UV light to weaken the adhesive strength of the resin, and the holding plate as the support is bent. The technique to make is reported (for example, refer patent document 2, 3).

特開平11−111824号公報JP-A-11-111824 特開2003−129011号公報JP 2003-129011 A 特開2002−76101号公報JP 2002-76101 A 新エネルギー・産業技術総合開発機構委託事業「超高密度電子SI技術の研究開発 エネルギー使用合理化技術開発」 H14年度成果報告書New Energy and Industrial Technology Development Organization commissioned project “Research and development of ultra-high density electronic SI technology Development of technology for rationalizing energy use” FY2014 results report セミ・ジャパン(SEMI Japan)、「薄型チップ実装の現状」講演予稿集, SEMICON Japan2002, 千葉, 2002年12月Semi-Japan (SEMI Japan), "Preliminary presentation of thin chip packaging" lecture, SEMICON Japan 2002, Chiba, December 2002

しかしながら、上記特許文献1記載の技術の場合、スクレーパ(刃)がウェハとプレートの間の両面テープに入り込んで貼り付き、ウェハをゆがめて破損させる可能性が高い。又、特許文献2記載の技術の場合、UV硬化前の樹脂の接着力も充分でなく、加工時にウェハが剥離したり、樹脂の種類によってはガスが発生する不具合がある。又、上記特許文献3記載の技術の場合、支持体にウェハが追随して湾曲し、破損する恐れがある。特に、ウェハ厚みが薄くなるとウェハの破損が生じ易くなる。   However, in the case of the technique described in Patent Document 1, there is a high possibility that the scraper (blade) enters and adheres to the double-sided tape between the wafer and the plate and distorts and breaks the wafer. Further, in the case of the technique described in Patent Document 2, the adhesive strength of the resin before UV curing is not sufficient, and there is a problem that the wafer is peeled off during processing or gas is generated depending on the type of resin. In the case of the technique described in Patent Document 3, there is a risk that the wafer follows the support and bends and breaks. In particular, when the wafer thickness is reduced, the wafer is easily damaged.

本発明は上記の課題を解決するためになされたものであり、ウェハを支持体から剥離する際、ウェハの破損を防止可能な半導体ウェハの剥離方法および剥離装置の提供を目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor wafer peeling method and a peeling apparatus that can prevent the wafer from being damaged when the wafer is peeled from the support.

上記した目的を達成するために、本発明の半導体ウェハの剥離方法は、支持体に第1の貼着材を介して貼着された半導体ウェハに対し、該半導体ウェハの貼着面と反対側の面に第2の貼着材を貼着し、該第2の貼着材側を凹状に撓ませて前記半導体ウェハを前記支持体から剥離する方法であって、前記第1の貼着材のヤング率をE1、その厚みをh1とし、前記第2の貼着材のヤング率をE2、その厚みをh2としたとき、E1×h1>E2×h2の関係を満たすことを特徴とする。
このようにすると、ウェハ、第1の貼着材、及び第2の貼着材からなる構造体を曲げた際の応力分布を考えた場合、面方向の応力が0となる中立面がウェハの中心より第1の貼着材側へ移行するため、ウェハの面方向の引張応力が低減し、ウェハの破損が防止される。
In order to achieve the above-described object, the semiconductor wafer peeling method of the present invention is the opposite side of the semiconductor wafer attachment surface to the semiconductor wafer attached to the support via the first attachment material. A second adhesive material is attached to the surface of the substrate, the second adhesive material side is bent in a concave shape, and the semiconductor wafer is peeled off from the support, wherein the first adhesive material When the Young's modulus is E1, the thickness is h1, the Young's modulus of the second adhesive is E2, and the thickness is h2, the relationship of E1 × h1> E2 × h2 is satisfied.
In this case, when considering the stress distribution when the structure composed of the wafer, the first adhesive material, and the second adhesive material is bent, the neutral surface where the stress in the plane direction is 0 is the wafer. Therefore, the tensile stress in the surface direction of the wafer is reduced, and damage to the wafer is prevented.

本発明によれば、ウェハを支持体から剥離する際のウェハの破損を防止することができる。   According to the present invention, it is possible to prevent the wafer from being damaged when the wafer is peeled from the support.

以下、本発明に係る半導体ウェハの剥離方法の実施の形態について、図面を参照して説明する。   Embodiments of a semiconductor wafer peeling method according to the present invention will be described below with reference to the drawings.

図1は、半導体ウェハを取扱う態様の一例を示す。この図において、(半導体)ウェハ30の表面に回路を形成した後、該表面を貼着材(接着剤や両面粘着シート等)28を介して支持体20に貼着し、ウェハ裏面に各種処理を施す。支持体20は、剛性を有する例えばガラス板等からなり、ウェハ30を補強して破損を防止する。支持体20は適宜吸着ステージ22に保持されている。吸着ステージ22は多孔質のセラミックス等からなり、外部の吸引機構を介して真空吸引することにより、ステージ上の支持体20の吸着保持および吸着解除を行う。
そして、ウェハ裏面にバックグラインドや回路形成を行った後、ウェハ30を支持体20から剥離し、ダイシングを行う。
FIG. 1 shows an example of a mode for handling a semiconductor wafer. In this figure, after a circuit is formed on the surface of a (semiconductor) wafer 30, the surface is attached to a support 20 via an adhesive material (adhesive, double-sided pressure-sensitive adhesive sheet, etc.) 28, and various treatments are performed on the back surface of the wafer. Apply. The support 20 is made of, for example, a glass plate having rigidity, and reinforces the wafer 30 to prevent breakage. The support 20 is appropriately held by the suction stage 22. The suction stage 22 is made of porous ceramics or the like, and sucks and holds the support 20 on the stage and releases the suction by vacuum suction through an external suction mechanism.
Then, after back grinding and circuit formation are performed on the back surface of the wafer, the wafer 30 is peeled off from the support 20 and dicing is performed.

次に、本発明の実施形態に係る半導体ウェハの剥離方法について、図2〜図4を参照して説明する。   Next, a semiconductor wafer peeling method according to an embodiment of the present invention will be described with reference to FIGS.

図2は、本実施形態に係る半導体ウェハの剥離を行う手順を示す。まず、所定の剥離装置(例えばテープマウンタ)の吸着ステージ22上に支持体20が保持され、次に、ウェハ30上面に、リングフレーム24に周縁を支持された円形のダイシングテープ26が貼着される(図2(a))。リングフレーム24の下面にはコの字状のアーム4が配置され、アーム4が所定の支点を中心に上方に回動することにより、ウェハ30が上方へ引上げられ、支持体から剥離される。
このとき、ダイシングテープ26側が凹状に撓み、ダイシングテープ26、ウェハ30、及び両面粘着シート28が一体となって支持体20から剥離される(図2(b))。なお、通常、両面粘着シート28は基材フィルムの両面に弱粘着層とUV硬化樹脂層とをそれぞれ備えているが、UV硬化樹脂層の方が硬質で接着強度が弱い。従って、剥離は支持体20に面したUV硬化樹脂層側で一般に進行し、ダイシングテープ26、ウェハ30、及び両面粘着シート28が一体となって剥離するものと考えてよい。
FIG. 2 shows a procedure for peeling the semiconductor wafer according to the present embodiment. First, the support 20 is held on the suction stage 22 of a predetermined peeling device (for example, a tape mounter), and then a circular dicing tape 26 whose periphery is supported by the ring frame 24 is attached to the upper surface of the wafer 30. (FIG. 2A). A U-shaped arm 4 is disposed on the lower surface of the ring frame 24. When the arm 4 rotates upward about a predetermined fulcrum, the wafer 30 is pulled upward and peeled off from the support.
At this time, the dicing tape 26 side is bent concavely, and the dicing tape 26, the wafer 30, and the double-sided pressure-sensitive adhesive sheet 28 are integrally peeled from the support 20 (FIG. 2B). In general, the double-sided pressure-sensitive adhesive sheet 28 includes a weak adhesive layer and a UV curable resin layer on both sides of the base film, but the UV curable resin layer is harder and has a lower adhesive strength. Therefore, the peeling generally proceeds on the side of the UV curable resin layer facing the support 20, and it may be considered that the dicing tape 26, the wafer 30, and the double-sided pressure-sensitive adhesive sheet 28 are peeled together.

ここで、本発明においては、上記第1の貼着材(両面粘着シート28)のヤング率をE1、その厚みをh1とし、前記第2の貼着材(ダイシングテープ26)のヤング率をE2、その厚みをh2としたとき、
E1×h1>E2×h2
の関係を満たすことを必要とする。
Here, in the present invention, the Young's modulus of the first adhesive material (double-sided pressure-sensitive adhesive sheet 28) is E1, its thickness is h1, and the Young's modulus of the second adhesive material (dicing tape 26) is E2. When the thickness is h2,
E1 × h1> E2 × h2
It is necessary to satisfy the relationship.

この理由について、図3、図4を参照して説明する。図3は、図2(b)の剥離領域の部分拡大図である。図3において、ダイシングテープ26は基材26Aと接着層26Bとを積層してなり、両面粘着シート28は基材28Aの両面にそれぞれ接着層26B、26Cとを積層してなっている。そして、ダイシングテープ26、ウェハ30、及び両面粘着シート28がともに上側が凹状になって曲げられている。   The reason for this will be described with reference to FIGS. FIG. 3 is a partially enlarged view of the peeling region in FIG. In FIG. 3, the dicing tape 26 is formed by laminating a base material 26A and an adhesive layer 26B, and the double-sided pressure-sensitive adhesive sheet 28 is formed by laminating adhesive layers 26B and 26C on both surfaces of the base material 28A. The dicing tape 26, the wafer 30, and the double-sided pressure-sensitive adhesive sheet 28 are bent so that the upper side is concave.

ここで、一般的な物体(梁)を曲げたときの断面内応力分布を図4に示す。曲げられた物体は、凹面側が縮み(面方向に圧縮応力が負荷され)、凸面側が伸び(面方向に引張応力が負荷され)るが、物体内部には面方向応力が0の(伸びも縮みもしない)中立面が形成される。又、圧縮応力や引張応力は、物体の表層側に行くほど(中立面から離れるほど)大きくなる。   Here, the stress distribution in a cross section when a general object (beam) is bent is shown in FIG. The bent object shrinks on the concave side (compressed with a compressive stress in the surface direction) and expands on the convex side (a tensile stress is applied in the surface direction), but the stress in the surface direction is 0 inside the object (the elongation also shrinks). A neutral plane is formed. In addition, the compressive stress and the tensile stress increase as it goes to the surface layer side of the object (away from the neutral surface).

そして、本発明において、ダイシングテープ26、ウェハ30、及び両面粘着シート28の積層体を多層梁とみなすと、多層梁を曲げたときに生じる中立面の位置y0は下記式1のように表すことができる。
ここで、添字iは、多層梁の各層を示し(例えば、上記図3の場合、層26Aがi=1、層26Bがi=2、・・・、層28Cがi=6)、nは層の数を示す。又、Eは各層のヤング率、Aは各層の平面積、b(x)は図3のS点から剥離側へ向かう距離(奥行き)、hは各層の厚み、を示す。
なお、式1の計算に当たり、図3に示す剥離界面Rより左側では支持体20と多層梁とを一体とみなして無視し、Rより右側の領域について、構造力学的計算を行う。又、S点は、剥離前の多層梁の右端位置を示す。
In the present invention, when the laminated body of the dicing tape 26, the wafer 30, and the double-sided pressure-sensitive adhesive sheet 28 is regarded as a multilayer beam, a neutral surface position y0 generated when the multilayer beam is bent is expressed by the following formula 1. be able to.
Here, the suffix i indicates each layer of the multi-layer beam (for example, in the case of FIG. 3 above, the layer 26A is i = 1, the layer 26B is i = 2,..., The layer 28C is i = 6), and n is Indicates the number of layers. E i is the Young's modulus of each layer, A i is the plane area of each layer, b (x) is the distance (depth) from the point S to the peeling side in FIG. 3, and h i is the thickness of each layer.
In the calculation of Expression 1, the support 20 and the multilayer beam are regarded as one unit on the left side from the peeling interface R shown in FIG. 3 and ignored, and the structural mechanical calculation is performed on the region on the right side of R. Moreover, S point shows the right end position of the multilayer beam before peeling.

そして、n=6の場合(図3の場合)、上記式1は、
のように式変形される。この式2は、各層において(E×h)で表される物理量同士を加算又は減算してゆくと、圧縮応力と引張応力が釣り合う位置に中立面が存在することを示している。
And when n = 6 (in the case of FIG. 3), the above equation 1 is
The expression is transformed as follows. Formula 2 shows that when a physical quantity represented by (E × h) is added or subtracted in each layer, a neutral plane exists at a position where compressive stress and tensile stress are balanced.

このことを単純化したモデルを図5に示す。この図において、ウェハの下層を貼着材1、上層を貼着材2とし、貼着材1のヤング率をE1、厚みをh1とし、貼着材2のヤング率をE2、その厚みをh2とする。
このとき、中立面の位置は、(E1×h1)と(E2×h2)の値の大小によって決まり、E1×h1=E2×h2のとき、中立面はウェハの中心厚に位置する。
一方、E1×h1>E2×h2の場合、中立面はウェハの中心厚より貼着材1側に移行し、E1×h1<E2×h2の場合、中立面はウェハの中心厚より貼着材2側に移行する。又、中立面より貼着材1側では引張応力が負荷され、中立面より貼着材2側では圧縮応力が負荷され、
A simplified model of this is shown in FIG. In this figure, the lower layer of the wafer is the adhesive material 1, the upper layer is the adhesive material 2, the Young's modulus of the adhesive material 1 is E1, the thickness is h1, the Young's modulus of the adhesive material 2 is E2, and the thickness is h2. And
At this time, the position of the neutral plane is determined by the values of (E1 × h1) and (E2 × h2). When E1 × h1 = E2 × h2, the neutral plane is located at the center thickness of the wafer.
On the other hand, in the case of E1 × h1> E2 × h2, the neutral surface moves to the adhesive material 1 side from the center thickness of the wafer, and in the case of E1 × h1 <E2 × h2, the neutral surface is pasted from the center thickness of the wafer. It moves to the dressing 2 side. In addition, a tensile stress is applied on the adhesive material 1 side from the neutral surface, and a compressive stress is applied on the adhesive material 2 side from the neutral surface.

ところで、ウェハは、圧縮応力よりも引張応力がかかる方が壊れやすい。従って、中立面を貼着材1側(凸面側)へ移行させることにより、ウェハにかかる引張応力を低減し、ウェハを破損しにくくすることができる。この場合、ウェハの面方向には主として圧縮応力がかかることになるが、圧縮応力はウェハの破損を招き難いので好ましい。
従って、本発明においては、
E1×h1>E2×h2 (3)
と規定する。例えば、硬質で厚い貼着材1をウェハと支持体の間に貼付し、比較的軟質又は厚みの薄い貼着材2をウェハの上側に貼付することで、中立面をウェハの下側に移行させることができる。なお、好ましくは、E1×h1>1.3×E2×h2とすると、中立面がウェハより外側(凸面側)へ移行するので、ウェハにかかる引張応力を確実に低減することができる。
By the way, a wafer is more easily broken when it is subjected to tensile stress than compressive stress. Therefore, by shifting the neutral surface to the sticking material 1 side (convex surface side), the tensile stress applied to the wafer can be reduced and the wafer can be hardly damaged. In this case, a compressive stress is mainly applied in the surface direction of the wafer, but the compressive stress is preferable because it hardly causes damage to the wafer.
Therefore, in the present invention,
E1 × h1> E2 × h2 (3)
It prescribes. For example, a hard and thick adhesive material 1 is applied between the wafer and the support, and a relatively soft or thin adhesive material 2 is applied to the upper side of the wafer so that the neutral surface is on the lower side of the wafer. Can be migrated. Preferably, if E1 × h1> 1.3 × E2 × h2, the neutral surface moves outward (convex surface) from the wafer, so that the tensile stress applied to the wafer can be reliably reduced.

次に、上記第1の貼着材(半導体ウェハ用貼着シート)の具体例について説明する。第1の貼着材を硬質にするためには、基材として、無機微粒子又は金属微粒子が配合された合成樹脂フィルムを用いることが好ましい。無機微粒子としては、シリコン(Si)、セラミックスの微粒子が挙げられる。又、上記無機微粒子や金属微粒子を配合すると、ヤング率が高くなる他、基材の熱膨張係数を小さくし、熱伝導度が高くなるので、温度上昇時のウェハと第1の貼着材との熱膨張率の差を低くし、熱応力の発生を抑制できる。又、基材の熱伝導度が高くなると、支持体とウェハとの間の温度差を低減することができる。   Next, a specific example of the first adhesive material (adhesive sheet for semiconductor wafer) will be described. In order to make the first adhesive material hard, it is preferable to use a synthetic resin film in which inorganic fine particles or metal fine particles are blended as a base material. Examples of the inorganic fine particles include silicon (Si) and ceramic fine particles. In addition, when the inorganic fine particles and metal fine particles are blended, the Young's modulus is increased, the thermal expansion coefficient of the base material is decreased, and the thermal conductivity is increased. The difference in coefficient of thermal expansion can be reduced, and the generation of thermal stress can be suppressed. Moreover, when the thermal conductivity of the base material increases, the temperature difference between the support and the wafer can be reduced.

上記第2の貼着材(半導体ウェハ用貼着シート)としては、ポリオレフィン又はポリ塩化ビニルを基材とするものが挙げられ、この基材を用いることで、第2の貼着材を軟質にすることができる。   As said 2nd adhesive material (adhesion sheet for semiconductor wafers), what uses polyolefin or polyvinyl chloride as a base material is mentioned, By using this base material, a 2nd adhesive material is made soft. can do.

半導体ウェハの取扱い(ハンドリング)の一例を示す模式図である。It is a schematic diagram which shows an example of handling (handling) of a semiconductor wafer. 本発明の実施形態に係る半導体ウェハの剥離方法を示す工程図である。It is process drawing which shows the peeling method of the semiconductor wafer which concerns on embodiment of this invention. 図2(b)の剥離領域の部分拡大図である。It is the elements on larger scale of the peeling area | region of FIG.2 (b). 物体(梁)を曲げたときの断面内応力分布を示す図である。It is a figure which shows the stress distribution in a cross section when an object (beam) is bent. 図4を単純化したモデルを示す図である。It is a figure which shows the model which simplified FIG.

符号の説明Explanation of symbols

20 支持体
26 第2の貼着材(ダイシングテープ)
28 第1の貼着材(両面粘着シート)
30 (半導体)ウェハ
20 Support 26 Second Adhesive Material (Dicing Tape)
28 1st adhesive material (double-sided adhesive sheet)
30 (Semiconductor) Wafer

Claims (1)

支持体に第1の貼着材を介して貼着された半導体ウェハに対し、該半導体ウェハの貼着面と反対側の面に第2の貼着材を貼着し、該第2の貼着材側を凹状に撓ませて前記半導体ウェハを前記支持体から剥離する方法であって、前記第1の貼着材のヤング率をE1、その厚みをh1とし、前記第2の貼着材のヤング率をE2、その厚みをh2としたとき、
E1×h1>E2×h2
の関係を満たすことを特徴とする半導体ウェハの剥離方法。
A second adhesive material is adhered to a surface opposite to the adhesion surface of the semiconductor wafer to the semiconductor wafer adhered to the support via the first adhesive material, and the second adhesive A method of peeling the semiconductor wafer from the support by bending the adhesive material side into a concave shape, wherein the first adhesive material has a Young's modulus of E1, its thickness is h1, and the second adhesive material Where Young's modulus is E2 and its thickness is h2.
E1 × h1> E2 × h2
A semiconductor wafer peeling method characterized by satisfying the relationship:
JP2004173322A 2004-06-11 2004-06-11 Exfoliation method of semiconductor wafer Ceased JP2005353859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004173322A JP2005353859A (en) 2004-06-11 2004-06-11 Exfoliation method of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004173322A JP2005353859A (en) 2004-06-11 2004-06-11 Exfoliation method of semiconductor wafer

Publications (1)

Publication Number Publication Date
JP2005353859A true JP2005353859A (en) 2005-12-22

Family

ID=35588058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004173322A Ceased JP2005353859A (en) 2004-06-11 2004-06-11 Exfoliation method of semiconductor wafer

Country Status (1)

Country Link
JP (1) JP2005353859A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009139126A1 (en) * 2008-05-12 2009-11-19 日東電工株式会社 Pressure-sensitive adhesive sheet, method of processing adherend with the pressure-sensitive adhesive sheet, and apparatus for stripping pressure-sensitive adhesive sheet
JP2013504178A (en) * 2009-09-01 2013-02-04 エーファウ・グループ・ゲーエムベーハー Apparatus and method for peeling a product substrate from a carrier substrate
JP2015013337A (en) * 2013-07-04 2015-01-22 リンテック株式会社 Transportation method and transportation device
JP2015146456A (en) * 2010-04-23 2015-08-13 エーファウ・グループ・ゲーエムベーハー Device and method for separating product substrate from carrier substrate
JP2018169372A (en) * 2017-03-30 2018-11-01 リンテック株式会社 Calculation system, calculation method, winding method, and wound roll body
KR20190041412A (en) * 2017-10-12 2019-04-22 가부시기가이샤 디스코 Method for grinding workpiece

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003338474A (en) * 2002-05-21 2003-11-28 Lintec Corp Machining method of brittle member
JP2004146761A (en) * 2002-08-28 2004-05-20 Lintec Corp Protective structure for semiconductor wafer, protective method for semiconductor wafer, lamination protecting sheet used for the same, and method for processing semiconductor wafer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003338474A (en) * 2002-05-21 2003-11-28 Lintec Corp Machining method of brittle member
JP2004146761A (en) * 2002-08-28 2004-05-20 Lintec Corp Protective structure for semiconductor wafer, protective method for semiconductor wafer, lamination protecting sheet used for the same, and method for processing semiconductor wafer

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8337656B2 (en) 2008-05-12 2012-12-25 Nitto Denko Corporation Pressure-sensitive adhesive sheet, method of processing adherend with the pressure-sensitive adhesive sheet, and apparatus for stripping pressure-sensitive adhesive sheet
WO2009139126A1 (en) * 2008-05-12 2009-11-19 日東電工株式会社 Pressure-sensitive adhesive sheet, method of processing adherend with the pressure-sensitive adhesive sheet, and apparatus for stripping pressure-sensitive adhesive sheet
EP2706561B1 (en) * 2009-09-01 2017-04-05 EV Group GmbH Method for concentrically releasing a product substrate (e.g., a semiconductor wafer) from a support substrate by deformation of a flexible film mounted on a frame
JP2013504178A (en) * 2009-09-01 2013-02-04 エーファウ・グループ・ゲーエムベーハー Apparatus and method for peeling a product substrate from a carrier substrate
EP2706562A3 (en) * 2009-09-01 2014-09-03 EV Group GmbH Device and method for releasing a semiconductor wafer from a carrier substrate by tilting a film frame
EP2290679B1 (en) * 2009-09-01 2016-05-04 EV Group GmbH Device and method for releasing a product substrate (e.g., a semiconductor wafer) from a support substrate by deformation of a flexible film mounted on a frame
JP2015146456A (en) * 2010-04-23 2015-08-13 エーファウ・グループ・ゲーエムベーハー Device and method for separating product substrate from carrier substrate
US9381729B2 (en) 2010-04-23 2016-07-05 Ev Group Gmbh Device for detaching a product substrate off a carrier substrate
US9457552B2 (en) 2010-04-23 2016-10-04 Ev Group Gmbh Method for detaching a product substrate off a carrier substrate
JP2015013337A (en) * 2013-07-04 2015-01-22 リンテック株式会社 Transportation method and transportation device
JP2018169372A (en) * 2017-03-30 2018-11-01 リンテック株式会社 Calculation system, calculation method, winding method, and wound roll body
KR20190041412A (en) * 2017-10-12 2019-04-22 가부시기가이샤 디스코 Method for grinding workpiece
JP2019075407A (en) * 2017-10-12 2019-05-16 株式会社ディスコ Grinding method of workpiece
JP7025171B2 (en) 2017-10-12 2022-02-24 株式会社ディスコ Grinding method for workpieces
TWI773838B (en) * 2017-10-12 2022-08-11 日商迪思科股份有限公司 Grinding method of workpiece
KR102535551B1 (en) * 2017-10-12 2023-05-22 가부시기가이샤 디스코 Method for grinding workpiece

Similar Documents

Publication Publication Date Title
JP5196838B2 (en) Manufacturing method of chip with adhesive
TWI509734B (en) Treating method for brittle member
JP2008103493A (en) Method and apparatus for picking up chip
TW200727446A (en) Stack type semiconductor device manufacturing method and stack type electronic component manufacturing method
JP2003309221A5 (en)
TW201231291A (en) Laminate and separation method of same
JP2010222021A (en) Adhesive holding tray
JP2006032506A (en) Method and device for peeling semiconductor wafer
JP5328422B2 (en) Electronic component holder
JP4271409B2 (en) Processing method for brittle materials
JP2005353859A (en) Exfoliation method of semiconductor wafer
JP2006032488A (en) Electronic component holder and its using method
JP2001102430A (en) Wafer support base with dust covering film and manufacturing method thereof
JP2011238815A (en) Adhesive sheet and semiconductor wafer handling method
JP5704602B2 (en) Thin semiconductor device manufacturing method and support for brittle member
JP4781874B2 (en) Support plate peeling method
JP2007180252A (en) Semiconductor device manufacturing method
TWI302023B (en) Adhesive film for semiconductor
JP4342340B2 (en) Manufacturing method of semiconductor device
JP4615475B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2005340390A (en) Device and method for manufacturing semiconductor device
JP2012115911A (en) Substrate grinding method and semiconductor element manufactured by using the same
JP5795272B2 (en) Method for manufacturing ceramic element
JP2010108987A (en) Die-bond dicing sheet
KR20080074601A (en) Multifunctional die attach film and semiconductor packaging method using the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070427

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20091028

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091102

A045 Written measure of dismissal of application

Free format text: JAPANESE INTERMEDIATE CODE: A045

Effective date: 20100323