JP2005353669A - Structure having bump and manufacturing method thereof - Google Patents

Structure having bump and manufacturing method thereof Download PDF

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JP2005353669A
JP2005353669A JP2004169981A JP2004169981A JP2005353669A JP 2005353669 A JP2005353669 A JP 2005353669A JP 2004169981 A JP2004169981 A JP 2004169981A JP 2004169981 A JP2004169981 A JP 2004169981A JP 2005353669 A JP2005353669 A JP 2005353669A
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substrate
bump
electrode
pad
bonding
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JP2005353669A5 (en
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Masatake Akaike
正剛 赤池
Haruto Ono
治人 小野
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Canon Inc
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Canon Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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Abstract

<P>PROBLEM TO BE SOLVED: To manufacture an electronic circuit and an MEMS on different substrates, to electrically bond the wiring circuit electrodes of the substrates, and to integrate both the substrates simultaneously. <P>SOLUTION: A method for manufacturing the substrates having a bump has a process for preparing a first substrate in which a plastically deformed material is filled into a groove for forming the bump, and a second substrate having a pad containing the plastically deformed material; a process for overlapping the surface of the first substrate in which the plastically deformed material is filled and the surface of the second substrate having the pad so that they oppose each other, applying a load to both the substrates, and bonding the plastically deformed material to the pad; and a process for transferring the plastically deformed material filled into the groove to the second surface by peeling off the first and second substrates, and forming the bump on the second substrate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は異なる基板にそれぞれ設けた微小な（マイクロ）回路電極同士、すなわちバンプとパッド間の回路電極同士の接合を行う方法に関するものである。   The present invention relates to a method of joining minute (micro) circuit electrodes provided on different substrates, that is, joining circuit electrodes between bumps and pads.

近年、ＭＥＭＳ（Ｍｉｃｒｏ−Ｅｌｅｃｔｏｒｉｃ−Ｍｉｃｒｏ−Ｓｙｓｔｅｍ）の多機能化と小型軽量化にともなって、素子自体が複雑化しており製作が困難になってきている。このため、電子回路とＭＥＭＳをそれぞれ異なる基板に作製し、この後両基板の配線回路電極同士を電気的に接合し、同時に両基板を一体化する必要性が高まっている。   In recent years, with the increase in functionality and reduction in size and weight of MEMS (Micro-Electronic-Micro-System), the elements themselves have become more complicated and difficult to manufacture. For this reason, there is a growing need to fabricate electronic circuits and MEMS on different substrates, and then electrically connect the wiring circuit electrodes of both substrates, and simultaneously integrate both substrates.

しかしながら、基板間の接合において、両基板に形成した微小な多数の回路電極同士を全て同時に歩留まり良く接合することは困難であった。   However, in bonding between substrates, it has been difficult to bond a large number of minute circuit electrodes formed on both substrates simultaneously with a high yield.

特許文献１において、面実装型半導体パッケージングとして半田ボールから成るバンプ、及びこのバンプ上面に粒状の高融点金属を散在させたバンプの両者間を対向し、対向バンプ間を押圧して、粒状金属でバンプ表面の酸化膜を突き破り、加熱によって接合している。   In Patent Document 1, a bump made of solder balls as a surface-mounting type semiconductor packaging and a bump in which granular refractory metal is scattered on the upper surface of the bump are opposed to each other, and the opposed bumps are pressed to form a granular metal. In this way, the oxide film on the bump surface is broken through and bonded by heating.

特許文献２において、面実装型半導体パッケージングにおいて、ワークの電極上に半田ボールを搭載した後、半田ボールを加熱・溶融・固化させてバンプを形成し、そして該半田ボールを濡れ性良くワークの電極上に付着させるために、真空吸着された導電性ボールを容器の底面に着地させて該導電性ボールの下面に一括してフラックスを付着させ、かつワークの電極上に品質の良いバンプを有するバンプ付ワークを作業性良く製造できるとしている。
特開平９−１６７７７３号 特開平９−２７０４４２号 In Patent Document 2, in surface mounting type semiconductor packaging, after mounting a solder ball on a workpiece electrode, the solder ball is heated, melted and solidified to form a bump, and the solder ball is formed with good wettability. In order to adhere to the electrode, the vacuum-adsorbed conductive ball is landed on the bottom surface of the container, the flux is adhered to the bottom surface of the conductive ball, and the work electrode has a high-quality bump. Bumped workpieces can be manufactured with good workability.
JP-A-9-167773 JP-A-9-270442

しかしながら、上述した特許文献１に開示している低融点金属であるＩｎボールを用いているので、半球状のバンプを形成することは容易であり、かつバンプとパッド間の接合もＩｎ−Ｐｄ−Ａｕの合金化によって確実に接合できるとしている。しかしながら、Ｉｎを一旦溶融して半球状のバンプを形成しているため、微細寸法のバンプを形成することは容易ではなかった。   However, since the In ball, which is a low melting point metal disclosed in Patent Document 1 described above, is used, it is easy to form a hemispherical bump, and the bonding between the bump and the pad is also In-Pd-. It is said that it can be reliably joined by the alloying of Au. However, since In is once melted to form a hemispherical bump, it is not easy to form a fine-sized bump.

また、上述した特許文献２では、導電性ボールを加熱・溶融・固化させて形成し、この後該一括して導電性ボールの下面にフラックスを付着して接合性を上げているが、加熱・溶融過程を有しているため、接合後室温までの降温過程で被接合体間での線膨張係数差に起因する内部応力による歪を生じ、寸法精度に影響を及ぼすことが考えられた。   Further, in Patent Document 2 described above, the conductive balls are formed by heating, melting, and solidifying, and then the flux is attached to the lower surface of the conductive balls in a lump to improve the bondability. Since it has a melting process, it is considered that distortion due to internal stress caused by the difference in linear expansion coefficient between the joined bodies occurs in the temperature lowering process to room temperature after joining, and affects the dimensional accuracy.

そこで、本発明は塑性変形する材料がバンプを形成するための溝に充填された第１の基板と前記塑性変形する材料を含むパッドを備えた第２の基板を用意する工程と、前記塑性変形する材料が充填された第１の基板の面と前記パッドを備えた前記第２の基板の面とを対向して重なり合わせ、両基板に荷重を印加することによって、前記塑性変形する材料と前記パットとを接合する工程と、前記第１の基板と前記第２の基板を引き剥がすことによって、前記第２の基板に前記溝に充填された前記塑性変形する材料が移着し、前記第２の基板にバンプを形成する工程とを備えるバンプを有する基板の製造方法を提供する。すなわち、上記の本方法によって基板間の電極間接合を可能にすることが出来る。   Therefore, the present invention provides a step of preparing a first substrate in which a material for plastic deformation is filled in a groove for forming a bump and a second substrate including a pad containing the material for plastic deformation, and the plastic deformation The surface of the first substrate filled with the material to be filled and the surface of the second substrate having the pad are overlapped with each other, and a load is applied to both the substrates to thereby apply the plastic deformation material and the The step of bonding a pad, and the first substrate and the second substrate are peeled off, whereby the plastically deformed material filled in the groove is transferred to the second substrate, and the second substrate is transferred to the second substrate. And a step of forming a bump on the substrate. That is, inter-electrode bonding between substrates can be made possible by the above-described method.

本発明をより具体的に説明する。   The present invention will be described more specifically.

図１、図２、図３、図４、図５、図６、図７は本発明の特徴を良く表す図面であり、同図において、１は第一のＳｉ基板、２は第一のＳｉ基板１に形成した溝孔、３は第一のＳｉ基板１の溝孔２に形成した電極バンプ、４は第二のＳｉ基板、５は第二のＳｉ基板４に形成したバンプ取り出し用パッド、６は両基板間の両側から印加する印加荷重、７は両基板を引き剥がすための引き剥がし荷重、８は第三のＳｉ基板、９は第三のＳｉ基板に形成した電極パッドである。   1, 2, 3, 4, 5, 6, and 7 show the features of the present invention. In FIG. 1, 1 is a first Si substrate, and 2 is a first Si substrate. Slots formed in the substrate 1, 3 is an electrode bump formed in the slot 2 of the first Si substrate 1, 4 is a second Si substrate, 5 is a bump extraction pad formed on the second Si substrate 4, 6 is an applied load applied from both sides between both substrates, 7 is a peeling load for peeling off both substrates, 8 is a third Si substrate, and 9 is an electrode pad formed on the third Si substrate.

上記構成において、第一のＳｉ基板１の一方の表面にフォトレジスト工程及びＲＩＥ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）を用いて溝孔２を形成し、さらにフォトレジスト工程とＡｕメッキ工程を経て図２に見るようにＡｕからなる電極バンプ３を形成し、さらにフォトレジスト工程と蒸着を用いた成膜工程を経て第二のＳｉ基板４にＡｕから成るバンプ取り出し用パッド５を形成し、この後第一のＳｉ基板１と第二のＳｉ基板４を相対向して、図４に見るように両Ｓｉ基板の両側から印加荷重６を印加することによって、第一のＳｉ基板上の電極バンプ３と第二のＳｉ基板のバンプ取り出し用パッド５を直接接合し、さらにこの後、図５に見るように引き剥がし荷重７を作用して該電極バンプ３を第二のＳｉ基板のバンプ取り出し用パッド５上に移着させる。すなわち転写させる。この接合・移着工程によって、第二のＳｉ基板４の上に電極バンプ３を形成した。一方、第三のＳｉ基板８に蒸着を用いた成膜によって電極パッド９を形成する。この後、図６に見るように第二のＳｉ基板４と第三のＳｉ基板８を相対向して、整合し、電極バンプ３と電極パッド９が互いに重畳した状態で両基板を両側から印加荷重６を印加することによって、該電極バンプ３と該電極パッド９を直接接合した（図７）。そして、第二のＳｉ基板４及び第三のＳｉ基板８上に形成した引き出し電極（図示なし）を用いて該電極バンプ３と電極パッド９との間の電気的導通を確認した。   In the above configuration, a groove 2 is formed on one surface of the first Si substrate 1 by using a photoresist process and RIE (Reactive Ion Etching), and further, a photoresist process and an Au plating process are performed, as shown in FIG. A bump bump 5 made of Au is formed on the second Si substrate 4 through a photoresist process and a film forming process using vapor deposition, and then the first Si is formed. The substrate 1 and the second Si substrate 4 are opposed to each other, and an applied load 6 is applied from both sides of the both Si substrates as shown in FIG. The bump removal pad 5 of the Si substrate is directly joined, and then, as shown in FIG. 5, a peeling load 7 is applied to remove the electrode bump 3 from the second Si substrate. It is transferred onto the pad 5 for use. That is, it is transferred. Electrode bumps 3 were formed on the second Si substrate 4 by this bonding / transfer process. On the other hand, the electrode pad 9 is formed on the third Si substrate 8 by film formation using vapor deposition. Thereafter, as shown in FIG. 6, the second Si substrate 4 and the third Si substrate 8 are opposed to each other and aligned, and both substrates are applied from both sides in a state where the electrode bump 3 and the electrode pad 9 overlap each other. By applying a load 6, the electrode bump 3 and the electrode pad 9 were directly joined (FIG. 7). Then, electrical conduction between the electrode bump 3 and the electrode pad 9 was confirmed using lead electrodes (not shown) formed on the second Si substrate 4 and the third Si substrate 8.

本実施例において、密着層なしで直接にＡｕから成る電極バンプ３を第一のＳｉ基板１上に形成したため、Ｓｉとの剥離性が良く、このため第一のＳｉ基板１の該電極バンプ３を第二のＳｉ基板４のバンプ取り付け用パッド５へ転写することが容易に可能であった。   In this embodiment, since the electrode bump 3 made of Au directly without an adhesion layer is formed on the first Si substrate 1, the peelability from Si is good, and thus the electrode bump 3 of the first Si substrate 1 is good. Can be easily transferred to the bump mounting pad 5 of the second Si substrate 4.

この際、第二のＳｉ基板４のバンプ取り付け用パッド５はＳｉ基板４と密着性の良いＣｒで密着層を形成し（図示なし）、該密着層の上にさらにＡｕを用いて形成したため、引き剥がし荷重を印加した場合においても、第二のＳｉ基板４の表面からの剥離はなかった。これは、Ｃｒ層が、Ｓｉ−Ｏ−Ｃｒの結合を形成するため、Ｓｉ−Ａｕの結合よりも強いと考えられるためである。   At this time, the bump mounting pad 5 of the second Si substrate 4 is formed of Cr having good adhesion with the Si substrate 4 (not shown), and further formed on the adhesion layer using Au. Even when a peeling load was applied, there was no peeling from the surface of the second Si substrate 4. This is because the Cr layer is considered to be stronger than the Si—Au bond because it forms a Si—O—Cr bond.

本実施例において、電極バンプ３、電極パッド９及びバンプ取り出し用パッド５として金属材料のＡｕを用いたが、この他にも塑性変形能を有する金属材料であっても良く、例えばＣｕ、Ａｌ、Ｓｎでも良い。ここで言う塑性変形能とは、ある限界以上の力を加えると連続的に変形し力を除いても変形したままで元に戻らない性質を言う。   In the present embodiment, Au as a metal material is used as the electrode bump 3, the electrode pad 9, and the bump extraction pad 5. However, other metal materials having plastic deformability may be used, for example, Cu, Al, Sn may also be used. The plastic deformability as used herein refers to the property that when a force exceeding a certain limit is applied, the material deforms continuously and remains deformed even if the force is removed.

そして、電極バンプ３とバンプ取り出し用パッド５の接合、及び電極バンプ３と電極パッド９との接合はいずれも室温における常温接合によって行った。   The bonding between the electrode bump 3 and the bump removal pad 5 and the bonding between the electrode bump 3 and the electrode pad 9 were both performed by room temperature bonding at room temperature.

本実施例においては、電極バンプ３、電極バンプ取り出し用パッド５及び電極パッド９のいずれの接合においても、接合前に表面をＡｒイオンプラズマ洗浄を行い、この後常温で接合した。   In this embodiment, in any of the bonding of the electrode bump 3, the electrode bump extraction pad 5 and the electrode pad 9, the surface was cleaned with Ar ion plasma before bonding, and then bonded at room temperature.

本実施例において形成した電極バンプ３は、寸法において高さ５μｍ、直径５μｍの円筒状のバンプであり、電極パッド９は高さ２００ｎｍ、一辺の距離２０μｍの四角状であり、そして電極バンプ３及び電極パッド９は、いずれもピッチ間距離５０μｍの正方マトリックス状に配置（図示なし）されたものである。尚、電極バンプ３の形状は円筒状の他にも、例えば矩形あるいは多角形でも良く、本発明の意図したことになんら変わるものではない。   The electrode bump 3 formed in this example is a cylindrical bump having a height of 5 μm and a diameter of 5 μm, and the electrode pad 9 is a square shape having a height of 200 nm and a distance of 20 μm on one side. The electrode pads 9 are all arranged in a square matrix (not shown) with a pitch distance of 50 μm. In addition to the cylindrical shape, the shape of the electrode bump 3 may be, for example, a rectangular shape or a polygonal shape, and does not change at all as intended by the present invention.

図８、図９、図１０、図１１、図１２、図１３、図１４は本発明の特徴を良く表す図面であり、同図において、１は第一のＳｉ基板、２は第一のＳｉ基板１に形成した溝孔、３は第一のＳｉ基板１の溝孔２に形成した電極バンプ、４は第二のＳｉ基板、５は第二のＳｉ基板４に形成したバンプ取り出し用パッド、６は両基板間を接合させるために該基板の両側から荷重を印加するための印加荷重、７は該接合後両基板を引き剥がすための引き剥がし荷重、８は第三のＳｉ基板、９は第三のＳｉ基板８に形成した電極パッドである
次に上記構成において、面方位（１００）からなる第一のＳｉ基板１の表面にフォトレジスト工程及び異方性エッチングを用いて図８に見るような溝孔２を形成し、この後さらにフォトレジスト工程及び蒸着を用いた成膜工程によって、図９に見るように該溝孔２にＡｕから成る電極バンプ３を形成し、一方、第二のＳｉ基板４上にフォトレジスト工程及び蒸着を用いた成膜工程によって、図１０に見るようにバンプ取り出し用パッド５を形成し、この後図１１に見るように両Ｓｉ基板を両側から印加荷重６を印加することによって、電極バンプ５とバンプ取り出し用パッド５を直接接合し、そして該直接接合後、該両基板の両側に図１２に見るように引き剥がし荷重７を作用することにより、第二のＳｉ基板４上のバンプ取り出し用パッド５に電極バンプ３を移着させた。成膜後の移着によって、めっき法を用いる場合に比べて、電極を用いないため、さらに微細な形状のバンプを作製することが容易である。すなわち第一のＳｉ基板１の電極バンプ３を第二のＳｉ基板上の電極パッド５に転写した。上記方法による接合・移着を用いて、第二のＳｉ基板４にＡｕからなる電極バンプ３を形成した。そして、第三のＳｉ基板８の上にフォトレジスト工程及び蒸着を用いた成膜工程によって図１３に見るようにＡｕから成る電極バンプ９を形成した。 8, 9, 10, 11, 12, 13, and 14 show the features of the present invention. In FIG. 8, 1 is a first Si substrate, and 2 is a first Si substrate. Slots formed in the substrate 1, 3 is an electrode bump formed in the slot 2 of the first Si substrate 1, 4 is a second Si substrate, 5 is a bump extraction pad formed on the second Si substrate 4, 6 is an applied load for applying a load from both sides of the substrate to bond the two substrates, 7 is a peeling load for peeling the two substrates after the bonding, 8 is a third Si substrate, and 9 is This is an electrode pad formed on the third Si substrate 8 Next, in the above configuration, the surface of the first Si substrate 1 having the plane orientation (100) is subjected to a photoresist process and anisotropic etching, as shown in FIG. Such a groove 2 is formed, and then a photoresist process and vapor deposition are further used. As shown in FIG. 9, the electrode bump 3 made of Au is formed in the groove hole 2 as shown in FIG. 9, while the photoresist process and the deposition process using vapor deposition are performed on the second Si substrate 4. As shown in FIG. 10, a bump take-out pad 5 is formed, and thereafter, as shown in FIG. After the direct bonding, the electrode bumps 3 are transferred to the bump removal pads 5 on the second Si substrate 4 by applying a peeling load 7 on both sides of the both substrates as shown in FIG. I let you. Compared to the case of using a plating method, transfer after film formation makes it easier to produce bumps having a finer shape because no electrode is used. That is, the electrode bump 3 of the first Si substrate 1 was transferred to the electrode pad 5 on the second Si substrate. Electrode bumps 3 made of Au were formed on the second Si substrate 4 using bonding / transfer by the above method. Then, as shown in FIG. 13, electrode bumps 9 made of Au were formed on the third Si substrate 8 by a photoresist process and a film forming process using vapor deposition.

上記方法によって、第二のＳｉ基板４への移着工程により形成した電極バンプ３と第三のＳｉ基板８に形成した電極バンプ９を図１３に見るように相対向して整合し、該電極バンプ３と該電極パッド９が互いに重畳した状態で、該Ｓｉ基板間を両側から印加荷重６で印加し、該電極バンプ３と電極パッド９を直接接合した。すなわち、この接合工程によって第二のＳｉ基板４と第三のＳｉ基板８の基板同士の接合、すなわち基板間電極間接合が可能になった。   By the above method, the electrode bump 3 formed by the transfer process to the second Si substrate 4 and the electrode bump 9 formed on the third Si substrate 8 are aligned to face each other as shown in FIG. With the bump 3 and the electrode pad 9 superimposed on each other, the Si substrate was applied with an applied load 6 from both sides to directly bond the electrode bump 3 and the electrode pad 9 together. That is, the bonding process enables bonding between the second Si substrate 4 and the third Si substrate 8, that is, bonding between the electrodes between the substrates.

そして、上記基板間電極間接合後、第二のＳｉ基板４及び第三のＳｉ基板８上に形成した引き出し電極（図示なし）を用いて電極バンプ３と電極パッド９との間の電気的導通をテスタで確認した。   After the inter-electrode bonding, the electrical continuity between the electrode bump 3 and the electrode pad 9 using the lead electrode (not shown) formed on the second Si substrate 4 and the third Si substrate 8 is used. Was confirmed with a tester.

本実施例において、密着層なしで直接にＡｕから成る電極バンプ３を第一のＳｉ基板１上に形成したため、Ｓｉとの剥離性が良く、このため第一のＳｉ基板１から該電極バンプ３を第二のＳｉ基板４に転写することが容易に可能であった。この際、第二のＳｉ基板４の電極引き出し用パッド５はＳｉ基板４と密着性の良いＴｉを密着層（図示なし）として形成し、該密着層の上にＡｕを形成したため、引き剥がし荷重７を印加した場合においても、第二のＳｉ基板４の表面からの剥離はなかった。   In this embodiment, since the electrode bump 3 made of Au directly without an adhesion layer is formed on the first Si substrate 1, the peelability from Si is good, so that the electrode bump 3 from the first Si substrate 1 is good. Could be easily transferred to the second Si substrate 4. At this time, the electrode drawing pad 5 of the second Si substrate 4 is formed of Ti having good adhesion with the Si substrate 4 as an adhesion layer (not shown), and Au is formed on the adhesion layer. Even when 7 was applied, there was no peeling from the surface of the second Si substrate 4.

本実施例において、電極バンプ３、電極パッド９及びバンプ取り出し用パッド５として金属材料のＡｕを用いたが、この他にも塑性変形能を有する金属材料であっても良く、例えばＡｌ、Ｃｕ、Ｓｎでも良い。Ａｌの場合は、超真空の半導体プロセスの工程の中でも使用することができ、要求される条件によって、使いわけることができる。   In the present embodiment, Au, which is a metal material, is used as the electrode bump 3, the electrode pad 9, and the bump extraction pad 5. However, other metal materials having plastic deformability may be used, for example, Al, Cu, Sn may also be used. In the case of Al, it can be used even in the process of an ultra-vacuum semiconductor process, and can be used depending on required conditions.

そして、電極バンプ３とバンプ取り出し用パッド５の接合、及び電極バンプ３と電極パッド９との接合はいずれも常温接合による直接接合によって行った。   The bonding between the electrode bump 3 and the bump take-out pad 5 and the bonding between the electrode bump 3 and the electrode pad 9 were both performed by direct bonding at room temperature.

本実施例において、電極バンプ３、電極バンプ取り出し用パッド５及び電極パッド９のいずれの組み合わせの場合の接合においても、接合前に表面をＡｒイオンプラズマ洗浄を行い、該洗浄後、室温で接合した。   In this example, in the case of any combination of the electrode bump 3, the electrode bump extraction pad 5, and the electrode pad 9, the surface was cleaned with Ar ion plasma before bonding, and then bonded at room temperature after the cleaning. .

本実施例において形成した電極バンプ３は、寸法において高さ１μｍ、一辺が約２μｍの四角形状のバンプであり、電極パッド９は、寸法において厚さ２００ｎｍ、一辺が２０μｍの四角形であり、電極バンプ３及び電極パッド９はいずれもピッチ間距離３０μｍの正方マトリックス状に配置されたものである。   The electrode bump 3 formed in this example is a square bump having a height of 1 μm and a side of about 2 μm. The electrode pad 9 is a square having a thickness of 200 nm and a side of 20 μm. 3 and the electrode pad 9 are both arranged in a square matrix with a pitch distance of 30 μm.

尚、電極バンプ形状は四角状の他にも、例えば円形状あるいは多角形でも良く、本発明の意図したことになんら変わるものではない。   In addition to the square shape, the electrode bump shape may be, for example, a circular shape or a polygonal shape, and does not change at all as intended by the present invention.

以上説明したように本発明は、第一のＳｉ基板に設けた溝孔にＡｕを形成し、第二のＳｉ基板にＡｕから成るバンプ取り付け用パッドを形成し、この後両Ｓｉ基板に荷重を印加することによって、溝孔の該Ａｕと該取り付け用バンプを直接接合し、この後該両Ｓｉ基板の引き剥し工程で第二のＳｉ基板の該バンプ取り付け用パッド面に移着した該Ａｕを新たに電極バンプとし、さらに第三のＳｉ基板にＡｕからなる電極パッドを形成し、この後第二のＳｉ基板と第三のＳｉ基板とを相対向して整合し、重畳した状態で両基板の両側から荷重を印加して該電極バンプと該電極パッドとを常温接合することにより、基板間電極間接合を可能にする。該電極バンプの寸法、配置及び個数は、該溝孔の寸法、配置及び個数に依存する。   As described above, in the present invention, Au is formed in the groove provided in the first Si substrate, bump mounting pads made of Au are formed on the second Si substrate, and then a load is applied to both Si substrates. By applying this, the Au in the groove and the mounting bump are directly bonded, and then the Au transferred to the bump mounting pad surface of the second Si substrate in the peeling process of both the Si substrates. A new electrode bump is formed, and an electrode pad made of Au is formed on the third Si substrate. After that, the second Si substrate and the third Si substrate are aligned and opposed to each other, and both substrates are overlapped. By applying a load from both sides of the substrate and bonding the electrode bump and the electrode pad at room temperature, the inter-electrode bonding between substrates can be performed. The size, arrangement and number of the electrode bumps depend on the size, arrangement and number of the groove holes.

従って、該溝孔を微少寸法に及び高密度に形成することによって、該電極バンプを該溝孔と同様に微少寸法に及び高密度に設けることが出来る。   Therefore, the electrode bumps can be provided in a minute size and a high density in the same manner as the groove holes by forming the groove holes in a minute size and a high density.

本発明の実施例１の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 1 of the present invention 本発明の実施例１の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 1 of the present invention 本発明の実施例１の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 1 of the present invention 本発明の実施例１の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 1 of the present invention 本発明の実施例１の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 1 of the present invention 本発明の実施例１の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 1 of the present invention 本発明の実施例１の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 1 of the present invention 本発明の実施例２の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 2 of the present invention 本発明の実施例２の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 2 of the present invention 本発明の実施例２の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 2 of the present invention 本発明の実施例２の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 2 of the present invention 本発明の実施例２の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 2 of the present invention 本発明の実施例２の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 2 of the present invention 本発明の実施例２の関わる基板間の配線間常温接合におけるバンプ製造方法及び接合方法Bump manufacturing method and bonding method in room temperature bonding between wirings related to Example 2 of the present invention

符号の説明Explanation of symbols

１、４、８ Ｓｉ基板
２ 溝孔
３ 電極バンプ
５ バンプ取付用パッド
６ 印加荷重
７ 引き剥がし荷重
９ 電極パッド 1, 4, 8 Si substrate 2 Groove hole 3 Electrode bump 5 Bump mounting pad 6 Applied load 7 Peeling load 9 Electrode pad

Claims (5)

塑性変形する材料がバンプを形成するための溝に充填された第１の基板と前記塑性変形する材料を含むパッドを備えた第２の基板を用意する工程と、
前記塑性変形する材料が充填された第１の基板の面と前記パッドを備えた前記第２の基板の面とを対向して重なり合わせ、両基板に荷重を印加することによって、前記塑性変形する材料と前記パットとを接合する工程と、
前記第１の基板と前記第２の基板を引き剥がすことによって、前記第２の基板に前記溝に充填された前記塑性変形する材料が移着し、前記第２の基板にバンプを形成する工程とを備えるバンプを有する基板の製造方法。 Providing a first substrate filled with grooves for forming plastic bumps with a plastically deformable material and a second substrate including a pad containing the plastically deformed material;
The surface of the first substrate filled with the plastically deforming material and the surface of the second substrate having the pad are overlapped with each other, and the plastic deformation is performed by applying a load to both the substrates. Joining the material and the pad;
The step of peeling the first substrate and the second substrate to transfer the plastically deformable material filled in the groove to the second substrate and forming bumps on the second substrate. The manufacturing method of the board | substrate which has a bump provided with these. 前記塑性変形する材料が、少なくともＡｕ、Ａｌ、Ｃｕ、Ｓｎの何れか１種類である請求項１記載の製造方法。   The manufacturing method according to claim 1, wherein the plastically deforming material is at least one of Au, Al, Cu, and Sn. 前記溝を有する第１の基板の前記溝が、エッチングによって形成される請求項１又は２記載の製造方法。   The manufacturing method according to claim 1, wherein the groove of the first substrate having the groove is formed by etching. 前記塑性変形する材料が、面心立方晶の結晶構造を備える材料である請求項１から３のいずれか記載の製造方法。   The manufacturing method according to claim 1, wherein the plastically deformable material is a material having a face-centered cubic crystal structure. 配線を備える基板上に、前記配線と電気的に接続し、塑性変形する材料を含有するバンプを複数備えることを特徴とするバンプを有する構造体。   A structure having a bump, comprising a plurality of bumps containing a material that is electrically connected to the wiring and is plastically deformed on a substrate including the wiring.
JP2004169981A 2004-06-08 2004-06-08 Structure having bump and manufacturing method thereof Pending JP2005353669A (en)

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