JP2005352559A - Data transfer method in multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems wherein transfer time is proportional to the volume of data in the case of data transfer between processors using a serial communication method, and complicated hardware is required for arbitration of memory access in the case of data transfer between processors via a shared memory. <P>SOLUTION: When transferring data between a CPU-A 102 and a CPU-B 103 via the shared memory 101, the CPU-A 102 makes the CPU-B 103 not access simultaneously by setting a versatile input and output terminal 105 connecting between an output terminal of the CPU-A 102 and an input terminal of the CPU-B 103 active when the CPU-A 102 accesses to the shared memory 101. The CPU-B 103 makes the CPU-A 102 not access simultaneously by setting a versatile input and output terminal 106 connecting between an output terminal of the CPU-B 103 and an input terminal of the CPU-A 102 active when the CPU-B 103 accesses to the shared memory 101. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transfer method in a multiprocessor system.

  In a conventional multiprocessor system, since a serial communication method is used as a data transfer method between processors, a transfer time proportional to the amount of data is required (for example, see Patent Document 1 or 2).

In addition, when data is transferred between processors using a shared memory arranged on the same system bus as the multiprocessor, it is necessary to configure a circuit for arbitrating writing to and reading from the memory by hardware ( For example, see Patent Document 3 or 4.)
JP 2001-268142 A (FIGS. 12 and 18) Japanese Patent Laid-Open No. 2002-152052 (FIGS. 10 to 10, FIGS. 11 to 14) JP-A-11-102348 (FIG. 1) Japanese Patent Laid-Open No. 5-20278 (FIG. 1)

  Since the serial communication method requires a transfer time in proportion to the data amount, it has been necessary to redesign the system considering the transfer speed when the transfer data amount is increased by expanding the system function. Furthermore, in order to prevent data destruction caused by disturbances such as noise superimposed on the signal line, it is necessary to detect errors in the transferred data, such as confirming data coincidence multiple times and adding parity data. There was a problem that it took time.

  Further, in the case of using a shared memory, it is necessary to configure the means for arbitrating access to the memory from each processor by complex hardware, and further, software design corresponding to the arbitration means is necessary.

  An object of the present invention is to provide a data transfer method in a multiprocessor system that can realize data transfer between processors in a short time and does not require a memory access arbitration means constituted by complex hardware.

  A data transfer method in a multiprocessor system according to the present invention is a data transfer method in a multiprocessor system in which data is transferred between a first processor and a second processor via a shared memory, wherein the first processor transfers data. A first memory access prohibition signal is output to the second processor while the shared memory is being accessed, and the second processor receives the first memory access prohibition signal while the shared memory is being input. The second processor outputs a second memory access prohibition signal to the first processor while accessing the shared memory for data transfer, and the second processor Is characterized in that access to the shared memory is prohibited while the second memory access prohibition signal is input.

  According to the present invention, it is possible to perform memory access arbitration with a simple configuration in which data is transferred between processors via a shared memory and a memory access prohibition signal is exchanged between the processors. Therefore, data transfer can be realized in a short time, and it is not necessary to configure the memory access arbitration means with complex hardware.

  Further, in the present invention, when each of the first and second processors becomes a data transmission side processor, the transfer data including the data to be actually transferred is written in the shared memory, and the transfer data is actually When the transfer data specification information for specifying the data to be transferred is stored in the shared memory and becomes a processor on the data receiving side, the data is actually transferred from the shared memory based on the transfer data specification information stored in the shared memory. The power data may be read out.

  In this way, by using transfer data designation information (for example, information on the start address and data size of data to be actually transferred), the transfer start position and the transfer data amount can be designated, and only changed data can be designated. In addition, it is possible to control the transfer from data with high priority, and the transfer can be made efficient.

  In the present invention, the general-purpose output terminal of the first processor is connected to the general-purpose input terminal of the second processor, and the first memory access prohibition signal is output from the general-purpose output terminal of the first processor to the second The general-purpose input terminal of the second processor is connected to the general-purpose output terminal of the second processor and the general-purpose input terminal of the first processor, and the second memory access prohibition signal is output from the general-purpose output terminal of the second processor. Then, it may be inputted to the general-purpose input terminal of the first processor.

  In this way, a memory access prohibition signal can be exchanged between processors with a simple configuration in which a general-purpose input terminal and a general-purpose output terminal are connected between processors.

  Further, in this case, at least one of the general-purpose input terminal of the second processor to which the first memory access prohibition signal is input and the general-purpose input terminal of the first processor to which the second memory access prohibition signal is input is an interrupt input. A terminal is preferred.

  As described above, by using the interrupt terminal on the input side of the memory access prohibition signal of each processor and performing processing by the interrupt handler, the response performance at the control timing can be improved.

  Further, one of the first and second processors starts outputting the memory access prohibition signal to the other processor immediately before accessing the shared memory, and within a predetermined time after starting the output. When the memory access prohibition signal from the other processor is input, the output of the memory access prohibition signal to the other processor may be stopped and the access to the shared memory may be stopped.

  Thus, when the first and second processors try to access the shared memory almost simultaneously, the access of one processor can be stopped and the other processor can be preferentially accessed. Simultaneous access to the shared memory by the two processors can be avoided, and a multi-master system becomes possible.

  In the present invention, the first and second processors are any two of the three or more processors that share the shared memory and are connected in series, and the first and second processors are in accordance with instructions from the first processor. When data is transferred between the second processors, the first memory access prohibition signal output from the first processor is input to all the processors other than the first processor through the connection between the processors, and the first processor The processor receiving the memory access prohibition signal prohibits access to the shared memory, and the second memory access prohibition signal output from the second processor is connected to the second processor by connection between the processors. Input to the processor connected to the first processor and the first processor, and second memory access prohibited The processor that is inputting the signal prohibits access to the shared memory, and the second memory access prohibition signal is generated when the second processor and the second processor are connected between the second processor and the first processor. The signal may be output from the second processor when the first memory access prohibition signal to the processor is released.

  As a result, memory access is achieved with a simple configuration in which data is transferred between any two of three or more processors connected in series via a shared memory, and a memory access prohibition signal is exchanged between the processors. Arbitration can be performed, data transfer can be realized in a short time, and the memory access arbitration means does not need to be configured with complex hardware.

  As described above, according to the present invention, stable data can be transferred efficiently, and a memory access arbitration unit configured with complicated hardware is unnecessary, and a general system configuration independent of hardware is realized. In addition, a multiprocessor system that exchanges data between processors via a shared memory can be configured easily and inexpensively. In addition, since a general-purpose system configuration is possible, software can be reused, and software productivity can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a data transfer method according to Embodiment 1 of the present invention. The data transfer method according to the first embodiment includes a shared memory 101, a CPU-A 102, a CPU-B 103, an address and data bus 104, a general-purpose input / output terminal 105, and a general-purpose input / output terminal 106.

  The shared memory 101 is an area for holding data to be transferred or holding commands for requesting writing and reading of transfer data from the CPU-A 102 to the CPU-B 103 or from the CPU-B 103 to the CPU-A 102. is there.

  The CPU-A 102 and the CPU-B 103 are processors and are connected to the shared memory 101 via the address and data bus 104 so that they can exchange data with each other.

  The general-purpose input / output terminal 105 connects the output terminal of the CPU-A 102 and the input terminal of the CPU-B 103, and the CPU-A 102 activates the general-purpose input / output terminal 105 while the CPU-A 102 writes a command in the command area. In order to notify the CPU-B 103 not to refer to the command area being written by the CPU-A 102, that is, to notify the CPU-B 103 not to simultaneously read the same address as the CPU-A 102 writes. belongs to.

  The general-purpose input / output terminal 106 connects the output terminal of the CPU-B 103 and the input terminal of the CPU-A 102, and the CPU-B 103 activates the general-purpose input / output terminal 106 while the CPU-B 103 writes a command in the command area. In order to notify the CPU-A 102 not to refer to the command area being written by the CPU-B 103, that is, to notify the CPU-A 102 not to simultaneously read the same address as the CPU-B 103 writes. belongs to.

  FIG. 2 is a memory map diagram of the shared memory showing an example of the shared memory mapping of the data transfer method according to the first embodiment of the present invention.

  An example of shared memory mapping of the data transfer method according to the first embodiment includes a transmission / reception command area 201, a status state area 202 indicating a control state for a command, a CPU-A write area 203 for the CPU-A 102 to write data, and a CPU -B103 has a CPU-B write area 204 for writing data.

  The transmission / reception command area 201 is an area for passing a command for reading or writing to a data transfer partner processor.

  The status state area 202 is an area for passing a status state indicating that the processor on the command receiving side has successfully processed the command to the command transmitting side processor.

  When error processing or handshake processing is not performed, the status state area 202 may not be used.

  The CPU-A writing area 203 is for holding data to be transferred to the CPU-B.

  The CPU-B writing area 204 is for holding data to be transferred to the CPU-A.

  Next, the data transfer procedure will be described in detail with reference to FIG. 3 or FIG.

  FIG. 3 is a timing chart when transferring data from the CPU-A 102 to the CPU-B 103 in the data transfer method according to the first embodiment of the present invention.

  3 is a timing chart in the case of transferring data from the CPU-A 102 to the CPU-B 103 in the data transfer method according to the first embodiment. The timing chart 301 or 303 in which the CPU-A 102 controls the memory is shown in FIG. There are sections 302 or 304 for controlling the memory, and these states can be distinguished by the internal state of the CPU-A 102 or the CPU-B 103. The mode indicating the internal state of the CPU-A 102 on the master side includes an IDLE mode indicating a state in which data is not being transferred, a CMD_SET mode indicating a state in which a command or data to be transmitted is written to the shared memory 101, and a slave CPU- The WIAT mode indicates a state in which the B 103 waits for the completion of processing according to the command, and the STS_CHK mode indicates a state in which status information from the CPU-B 103 serving as a slave is confirmed. On the other hand, the mode indicating the internal state of the CPU-B 103 on the slave side includes an IDLE mode indicating a state where data transfer is not being performed, and a CMD_GET indicating a state where a command from the CPU-A 102 serving as the master is received and necessary processing is performed. Consists of modes. Since a series of control units composed of the control sections 301, 302, 303, and 304 can be managed from the internal state of the CPU-A 102 on the master side from the transfer start to the end, the internal state of the CPU-B 103 is a series of control units. Even between control units, control can be performed in the IDLE mode without distinguishing between the control sections 301 and 303.

  In the control section 301, the CPU-A 102 sets the general-purpose output terminal 105 to active, and notifies the CPU-B 103 that the shared memory 101 is being accessed. The CPU-A 102 sets data to be transmitted to the CPU-B 103 in the CPU-A write area 203 and sets a reception request command in the transmission / reception command area 201 so that the CPU-B 103 receives data. The setting is completed by setting the output terminal 105 to non-active (CPU-A: CMD_SET mode).

  In the control section 302, when detecting that the general-purpose output terminal 105 has changed from active to non-active, the CPU-B 103 sets the general-purpose output terminal 106 to active and refers to the command set in the transmission / reception command area 201. Confirm that the command is a reception request command. The CPU-B 103 fetches the set data into the CPU-A writing area 203 and sets the reading completion to the transfer status state area 202 when the processing is completed. Note that the transfer status state area 202 may be the same area as the transmission / reception command area 201 when there is no need to hold a command.

  The CPU-B 103 completes by setting the general-purpose output terminal 106 to non-active (CPU-A: WAIT mode, CPU-B: CMD_GET mode).

  In the control section 303, when the CPU-A 102 detects that the general-purpose output terminal 106 has changed from active to non-active, the CPU-A 102 sets the general-purpose output terminal 105 to active, and sets the status state set in the transfer status state area 202. Refer to and confirm that the reading is complete. The CPU-A 102 discards the reception request command set in the transmission / reception command area 201, and sets the general-purpose output terminal 105 to non-active to complete (CPU-A: STS_CHK mode).

  In the control section 304, when detecting that the general-purpose output terminal 105 has changed from active to non-active, the CPU-B 103 sets the general-purpose output terminal 106 to active and refers to the command set in the transmission / reception command area 201. . If it is confirmed that the command is not set, the CPU-B 103 sets the general-purpose output terminal 106 to non-active and completes. Upon detecting that the general-purpose output terminal 106 has changed from active to non-active, the CPU-A 102 transitions from the STS_CHK mode to the IDLE mode.

  Further, when the CPU-B 103 cannot receive data correctly, the CPU-A 102 can be notified by setting a reception error in the transfer status state area 202.

  At this time, when the CPU-A 102 confirms that the reception has not been completed in the control section 303, the CPU-A 102 does not discard the reception request command set in the transmission / reception command area 201, and sends data to the CPU-B 103. , The reception request command is set in the transmission / reception command area 201, the general-purpose output terminal 105 is set to non-active, and the processing from the control section 302 can be performed sequentially thereafter. .

  FIG. 4 is a timing chart when the CPU-A 102 of the data transfer method according to the first embodiment of the present invention receives data from the CPU-B 103.

  In the control section 401, the CPU-A 102 sets the general-purpose output terminal 105 to active and notifies the CPU-B 103 that the shared memory 101 is being accessed. The CPU-A 102 sets a transmission request command in the transmission / reception command area 201 so as to transmit data to the CPU-B 103, sets the general-purpose output terminal 105 to non-active, and completes (CPU-A: CMD_SET mode).

  In the control section 402, when detecting that the general-purpose output terminal 105 has changed from active to non-active, the CPU-B 103 sets the general-purpose output terminal 106 to active and refers to the command set in the transmission / reception command area 201. Confirm that it is a send request command. The CPU-B 103 writes the requested data in the CPU-B writing area 204, and when the processing is completed, the writing completion is set in the transfer status state area 202. Note that the transfer status state area 202 may be the same area as the transmission / reception command area 201 when there is no need to hold a command.

  The CPU-B 103 completes by setting the general-purpose output terminal 106 to non-active (CPU-A: WAIT mode, CPU-B: CMD_GET mode).

  In the control section 403, when the CPU-A 102 detects that the general-purpose output terminal 106 has changed from active to non-active, the CPU-A 102 sets the general-purpose output terminal 105 to active, and sets the status state set in the transfer status state area 202. With reference to confirming that the writing is completed, the data received from the CPU-B 103 is fetched from the CPU-B writing area 204. The CPU-A 102 discards the transmission request command set in the transmission / reception command area 201 and completes the general-purpose output terminal 105 by setting it to non-active (CPU-A: STS_CHK mode).

  In the control section 404, when detecting that the general-purpose output terminal 105 has changed from active to non-active, the CPU-B 103 sets the general-purpose output terminal 106 to active and refers to the command set in the transmission / reception command area 201. . If it is confirmed that the command is not set, the CPU-B 103 sets the general-purpose output terminal 106 to non-active and completes. Upon detecting that the general-purpose output terminal 106 has changed from active to non-active, the CPU-A 102 transitions from the STS_CHK mode to the IDLE mode.

  Further, when the CPU-B 103 cannot transmit data correctly, the CPU-A 102 can be notified by setting a transmission error in the transfer status state area 202.

  At this time, if the CPU-A 102 confirms that the writing has not been completed in the control section 403, the CPU-A 102 does not discard the transmission request command set in the transmission / reception command area 201, and sends data to the CPU-B 103. Then, the transmission request command is set in the transmission / reception command area 201, the general-purpose output terminal 105 is set to non-active, and the processing from the control section 402 can be performed sequentially thereafter. .

  Further, in the shared memory 101, in addition to the transmission / reception command area 201 and the transfer status state area 202, a data head address 205 and a transmission / reception data size 206 for controlling the CPU-A writing area 203 and the CPU-B writing area 204 are provided. As a result, the transfer start position and the transfer data amount can be designated, and control such as transferring only changed data or data with high priority can be performed, and the transfer can be made efficient.

  In addition, the general-purpose input / output terminal 105 and the general-purpose input / output terminal 106 use an interrupt terminal on each input side and perform processing by the interrupt handler, thereby improving the response performance at the control timing shown in FIG. Can be made.

  As described above, according to the first embodiment, it is possible to efficiently transfer stable data, and there is no need for a memory access arbitration unit configured by complex hardware, and a general-purpose system configuration that does not depend on hardware. And a multiprocessor system for exchanging data between processors via the shared memory 101 can be configured easily and inexpensively. In addition, since a general-purpose system configuration is possible, software can be reused, and software productivity can be improved.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. In the second embodiment, the configuration of the data transfer method is shown in FIGS. 1 and 2 as in the first embodiment. The control timing chart in the second embodiment is almost the same as that in FIGS. 3 to 4 of the first embodiment, but the control at the start of communication is different. FIG. 5 is a timing chart of the data transfer method according to the second embodiment of the present invention.

  In the second embodiment, in order to enable a multi-master system using the CPU-A 102 and the CPU-B 103, a method for taking a countermeasure with software so that the shared memory 101 is not simultaneously accessed will be described with reference to FIG. explain.

  FIG. 5 shows a system in which two processors of CPU-A 102 and CPU-B 103 can serve as a master. At timing 305 or 405 (FIGS. 3 and 4) at which communication is started, CPU-A 102 and CPU-B 103 are simultaneously shared memory. An example in which priority is given to the CPU-A 102 when an access request is issued to 101 is shown. The CPU-A output terminal 504 indicates the output terminal of the CPU-A 102 in the general-purpose input / output terminal 105 in FIG. 1, and the CPU-B output terminal 505 indicates the CPU in the general-purpose input / output terminal 106 in FIG. -Refers to the output terminal of B103.

  First, in the case of FIG. 5A, when the CPU-B 103 performs bus access in the control section 501, after confirming that the CPU-A output terminal 504 is non-active, the CPU-B output terminal 505 Set to active.

  In the control section 502, a sufficient wait is performed.

  In the control section 503, after completing the wait, the CPU-B 103 again refers to the CPU-A output terminal 504. If the CPU-A output terminal 504 is active at this time, the CPU-A 102 is almost at the same time. The CPU-B 103 determines that the bus access has started, sets the CPU-B output terminal 505 to non-active, and stops communication.

  When the CPU-A output terminal 504 is non-active, the CPU-B 103 starts accessing the shared memory as it is.

The time (T _W ) that the CPU-B 103 needs to wait in the control section 502 is the time from when the CPU-B 103 sets the CPU-B output terminal 505 active until the CPU-A 102 can recognize it (T T). _d1 ), from the time (T _d2 ) from when the CPU-A 102 sets the CPU-A output terminal 504 to active until the CPU-B 103 can recognize it,
T _W = T _d1 + T _d2 + α ··· Formula (1)
Can be shown.

  In addition, α is a grace time when considering the rounding of the waveform, and it is desirable to consider in advance.

  As shown in FIG. 5B, the same applies when the CPU-A 102 first sets the CPU-A output terminal 504 to active.

  Next, in the second embodiment, when the CPU-A 102 and the CPU-B 103 issue an access request to the shared memory 101 at the same time, the CPU-A 102 and the CPU-B 103 are controlled with respect to an example in which the CPU-A 102 side is given priority. The method will be described with reference to FIGS. FIG. 6 is a flowchart of control of each of CPU-A (high priority side) and CPU-B (low priority side) according to Embodiment 2 of the present invention. FIG. 7 is a timing chart based on the control flowchart in FIG.

  The communication start conditions of the CPU-A 102 and the CPU-B 103 are set, and the transmission processing of the control section 1001 shown in FIG. 6 is executed at the communication start timing 1005. In FIG. 6, the CPU-B 103 detects that the CPU-A output terminal 504 is active after waiting for a time (Tw) that the CPU-B 103 represented by the above formula (1) needs to wait. Then, the CPU-B output terminal 505 is set to non-active and the process is terminated.

  When the CPU-A 102 uses an interrupt terminal for input to the CPU-B output terminal 505, the CPU-B output terminal 505 in which the CPU-B 103 is active in this example is set to non-active and communication is stopped. The CPU-A 102 detects the interrupt at the timing, but the CPU-A 102 indicates that the CPU-A 102 is in a state (CPU-A: CMD_SET mode) while the CPU-A output terminal 504 is set to active. By determining with a handler or the like, the CPU-A 102 can process it as a dummy interrupt.

  When completing the command setting process and the like, the CPU-A 102 sets the CPU-A output terminal 504 to non-active after transitioning to the WAIT mode. Next, the process of the control section 1002 shown in FIG. 6 is executed. When data is transferred from the CPU-A 102 to the CPU-B 103 in the data transfer method according to the first embodiment of the present invention using FIG. 3 after the command reference state (CMD_GET mode) of the CPU-B 103 indicated in the control section 1002 The same processing as that described in the example is performed.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. FIG. 8 is a block diagram showing the configuration of the data transfer method according to the third embodiment of the present invention. The data transfer method according to the third embodiment includes a shared memory 601, a plurality of processors 602 to 607, general-purpose input / output terminals 608 to 617 that connect the processors in series, and an address and data bus 618. Is done.

  FIG. 9 is a memory map diagram of the shared memory showing an example of the shared memory mapping of the data transfer method according to the third embodiment of the present invention.

  An example of shared memory mapping of the data transfer method according to the third embodiment includes a command issue CPU ID area 701 and a command transmission destination CPU ID area 702 in addition to the example shown in FIG.

  The command issuing CPU ID area 701 is a CPU ID of a processor that sets a command for reading or writing to the transmission / reception command area 201.

  The command transmission destination CPU ID area 702 is a CPU ID for designating a processor on the command receiver side.

  Next, the data transfer procedure will be described in detail with reference to FIG.

  FIG. 10 is a control flowchart in a case where data is transferred from the CPU-C 604 to the CPU-E 606 in the data transfer method according to the third embodiment of the present invention.

  From the CPU-C 604, the CPU-B 603 and the CPU-A 602 are sequentially called the upper direction, and from the CPU-C 604, the CPU-D 605 and the CPU-E 606 are called the lower direction, and the command is issued. Assume that the processor to which the command is issued knows in advance that the processor to which the command is issued ranks higher or lower than itself.

  First, the CPU-C 604 sets the general-purpose output terminals 610 and 614 to be active, and notifies the other processors (CPU-B 603 and CPU-D 605) that the shared memory is being accessed. In response to the fact that the general-purpose terminal is set to active, the CPU-B 603 and CPU-D 605 respectively notify the other processors (CPU-A 602 and CPU-E 606) that the shared memory is being accessed. Notification control is performed in the same manner so that notifications are passed to all connected processors.

  The CPU-C 604 sets the data to be transmitted to the CPU-E 606 in the command issuing side CPU data writing area 703 and sends a reception request command to the transmission / reception command area 201 so that the CPU-E 606 receives the data. An ID that can indicate the CPU-C604 is set in the issuing CPU ID area 701, and an ID that can indicate the CPU-E606 is set in the command transmission destination CPU ID area 702, and the general-purpose output terminal 610 is set. Set to non-active and complete.

  When detecting that the general-purpose output terminal 610 has changed from active to non-active, the CPU-D 605 refers to the ID set in the command transmission destination CPU ID area 702 and determines that the notification is not addressed to itself. The setting is completed by setting the output terminal 611 to non-active.

  When detecting that the general-purpose output terminal 611 has changed from active to non-active, the CPU-E 606 refers to the ID set in the command transmission destination CPU ID area 702 and determines that the notification is addressed to itself. The general-purpose output terminal 616 is set to active, and the command set in the transmission / reception command area 201 is referenced to confirm that it is a reception request command. The CPU-E 606 fetches the set data into the command issuing side CPU data writing area 703 and sets the reading completion to the transfer status state area 202 when the processing is completed.

  The CPU-E 606 sets the general-purpose output terminal 616 to non-active and completes.

  When the CPU-D 605 detects that the general-purpose output terminal 615 has changed from active to non-active, the CPU-D 605 determines that the notification is not addressed to itself by referring to the ID set in the command transmission destination CPU ID area 702. The setting is completed by setting the output terminal 615 to non-active.

  When the CPU-C 604 detects that the general-purpose output terminal 615 has changed from active to non-active, the CPU-C 604 sets the general-purpose output terminal 610 to active and completes reading with reference to the status state set in the transfer status state area 202 Make sure that The CPU-C 604 discards the reception request command set in the transmission / reception command area 201 and indicates the CPU-C 604 set in the command issue CPU ID area 701 and the command transmission destination CPU. The ID that can indicate the CPU-E 606 set in the ID area 702 is discarded, and the general-purpose output terminals 610 and 614 are set to non-active to complete the process.

  The CPU-B 603 and CPU-D 605 refer to the command set in the transmission / reception command area 201 in the same procedure as in the first embodiment in response to the general-purpose terminals 614 and 610 being set to non-active. Alternatively, an ID set in the command transmission destination CPU ID area 702 may be referred to. If it is confirmed that the command or the transmission destination ID is not set, the general-purpose output terminal is sequentially set to non-active and the process is completed. Notification control is performed in the same manner so that notifications are passed to all connected processors.

  With the method described above, data can be transferred between any two processors among a plurality of processors connected in series.

  The data transfer method in the multiprocessor system according to the present invention does not require a memory access arbitration unit composed of complex hardware, and does not have an arbitration unit because small-scale and easy software control is possible. Stable and efficient data transfer is possible even with a general-purpose microcomputer, which is useful for a multiprocessor system using a general-purpose microcomputer.

The block diagram which shows the structure of the data transfer method which concerns on Embodiment 1 of this invention. The memory map figure of a shared memory which shows an example of the shared memory mapping of the data transfer method which concerns on Embodiment 1 of this invention Master transmission timing chart of an example when CPU-A of the present invention is a master Master reception timing chart of an example when CPU-A of the present invention is used as a master Timing chart of data transfer method according to embodiment 2 of the present invention Control flow chart of data transfer method according to embodiment 2 of the present invention Control timing chart of data transfer method according to embodiment 2 of the present invention The block diagram which shows the structure of the data transfer method which concerns on Embodiment 3 of this invention. The memory map figure of the shared memory which shows an example of the shared memory mapping of the data transfer method concerning Embodiment 3 of this invention Control flow chart illustrating an example in which CPU-C is a master and CPU-E is a slave in the data transfer method according to the third embodiment of the present invention.

Explanation of symbols

101, 601 Shared memory 102, 103, 602-607 Processor (CPU-A to CPU-F)
104, 618 Address and data bus 105, 106, 608 to 617 General-purpose input / output terminals 201 Transmission / reception command area 202 Transfer status status area 203, 703 Command issuing side CPU data writing area 204, 704 Command transmission destination CPU data writing area 205 Data head Address 206 Transmission / reception data size 305, 405, 1005 Communication start timing 504 CPU-A output terminal 505 CPU-B output terminal 701 Command issuing CPU ID area 702 Command transmission destination CPU ID area 1001, 1002, 1003, 1004 Control section 901, 902 , 903, 904 Interrupt edge

Claims (6)

A data transfer method in a multiprocessor system for transferring data between a first processor and a second processor via a shared memory,
While the first processor is accessing the shared memory for transferring the data, the first processor outputs a first memory access prohibition signal to the second processor, and the second processor While the memory access prohibition signal of 1 is being input, access to the shared memory is prohibited,
The second processor outputs a second memory access prohibition signal to the first processor while accessing the shared memory for the data transfer, and the first processor 2. A data transfer method in a multiprocessor system, wherein access to the shared memory is prohibited while two memory access prohibition signals are input. Each of the first and second processors includes:
When becoming a processor on the data transmission side, transfer data specifying data for writing the transfer data including the data to be actually transferred to the shared memory and specifying the data to be actually transferred among the transfer data Is stored in the shared memory,
2. The multiprocessor system according to claim 1, wherein when the processor is a data receiving side processor, the data to be actually transferred is read from the shared memory based on the transfer data designation information stored in the shared memory. Data transfer method. The general-purpose output terminal of the first processor is connected to the general-purpose input terminal of the second processor, and the first memory access prohibition signal is output from the general-purpose output terminal of the first processor and the second processor Input to the general-purpose input terminal of the processor,
The general-purpose output terminal of the second processor is connected to the general-purpose input terminal of the first processor, and the second memory access prohibition signal is output from the general-purpose output terminal of the second processor and the first processor 2. The data transfer method in a multiprocessor system according to claim 1, wherein the data is input to a general-purpose input terminal of the processor.   At least one of the general-purpose input terminal of the second processor to which the first memory access prohibition signal is input and the general-purpose input terminal of the first processor to which the second memory access prohibition signal is input is an interrupt input. 4. The data transfer method in a multiprocessor system according to claim 3, wherein the data transfer method is a terminal.   Either one of the first and second processors starts outputting the memory access prohibition signal to the other processor immediately before accessing the shared memory, and within a predetermined time after starting the output. 5. The memory access prohibiting signal from the other processor is input, and the output of the memory access prohibiting signal to the other processor is stopped and the access to the shared memory is stopped. A data transfer method in the described multiprocessor system. The first and second processors are any two of the three or more processors that share the shared memory and are connected in series;
When performing data transfer between the first and second processors according to an instruction of the first processor,
The first memory access prohibition signal output from the first processor is input to all processors other than the first processor by connection between the processors, and the first memory access prohibition signal is input. The processor prohibits access to the shared memory;
The second memory access prohibition signal output from the second processor is input to the processor connected between the second processor and the first processor by connection between the processors and the first processor. And the processor receiving the second memory access prohibition signal prohibits access to the shared memory,
The second memory access prohibition signal is released from the first memory access prohibition signal to the processor connected between the second processor and the first processor and the second processor. 6. The data transfer method in the multiprocessor system according to claim 1, wherein the data is output from the second processor.

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