JP2005347513A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2005347513A
JP2005347513A JP2004165376A JP2004165376A JP2005347513A JP 2005347513 A JP2005347513 A JP 2005347513A JP 2004165376 A JP2004165376 A JP 2004165376A JP 2004165376 A JP2004165376 A JP 2004165376A JP 2005347513 A JP2005347513 A JP 2005347513A
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circuit board
electrode
semiconductor element
semiconductor device
convex
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Toshiyuki Kojima
俊之 小島
Yasuharu Karashima
靖治 辛島
Koichi Hirano
浩一 平野
Toshiyuki Asahi
俊行 朝日
Tsukasa Shiraishi
司 白石
Seiichi Nakatani
誠一 中谷
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2004165376A priority Critical patent/JP2005347513A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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Abstract

<P>PROBLEM TO BE SOLVED: To make both electrodes 2 and 4 of a semiconductor device accurately positioned. <P>SOLUTION: The semiconductor device is provided with a semiconductor element 1 having an electrode 2 on its one surface, and a circuit board 3 having an electrode 4 on its one surface. In the semiconductor device in which the electrodes 2 and 4 are electrically connected to each other in a state where the one surface of the semiconductor element 1 is faced to the one surface of the circuit board 3, the electrode 2 of the element 1 is formed as a projecting electrode, and the electrode 4 of the board 3 is formed as a recessed electrode. In addition, the inner bottom surface of the recessed electrode 4 is constituted so that the bottom surface may become lower than the main surface of the one surface of the circuit board 3. The projecting electrode 2 of the semiconductor element 1 is electrically connected to the recessed electrode 4 of the circuit board 3 by inserting the electrode 2 into the electrode 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置およびその製造方法に関する。特に、一方面に電極を有する半導体素子の一方面を一方面に電極を有する回路基板の一方面に向き合わせた状態で互いの電極を電気的に接続してなる半導体装置に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device in which electrodes are electrically connected in a state where one surface of a semiconductor element having an electrode on one surface faces one surface of a circuit board having an electrode on one surface.

近年の電子機器の高機能化・小型化に伴って、電子機器を構成する半導体素子の多ピン化および各種部品の小型化が進み、それらを搭載する回路基板の配線数と密度は飛躍的に増加している。特に、半導体素子（半導体チップ）から引き出される端子数が急速に増加したことによって、回路基板（配線基板）の微細化が進んでおり、その結果、微細ピッチ接続技術が重要になっている。また同時に電子機器の小型化を実現するために、小面積で薄く半導体を実装する技術が重要になっている。   As electronic devices have become more sophisticated and smaller in size in recent years, the number of semiconductor elements that make up electronic devices has increased in number and the size of various parts has been reduced. The number and density of circuit boards on which these devices are mounted have dramatically increased. It has increased. In particular, the rapid increase in the number of terminals drawn from a semiconductor element (semiconductor chip) has led to the miniaturization of circuit boards (wiring boards), and as a result, fine pitch connection technology has become important. At the same time, in order to realize miniaturization of electronic devices, a technique for mounting a semiconductor with a small area and a thickness is important.

微細ピッチ・小型化を実現する接続技術として、フィリップチップボンディング法（以下、単にＦＣ法という）がある（例えば特許文献１参照。）。このＦＣ法について、図７（ａ）（ｂ）（ｃ）を参照しながら説明する。なお、図７（ａ）は、ＦＣ法を用いて実装された半導体装置の断面構成を示している。図７（ｂ）は、ＦＣ法を用いた半導体装置の製造方法を示している。図７（ｃ）は、ＦＣ法を用いた課題を示している。   There is a Philip chip bonding method (hereinafter simply referred to as the FC method) as a connection technique for realizing a fine pitch and miniaturization (see, for example, Patent Document 1). The FC method will be described with reference to FIGS. 7 (a), (b), and (c). FIG. 7A shows a cross-sectional configuration of a semiconductor device mounted using the FC method. FIG. 7B shows a method for manufacturing a semiconductor device using the FC method. FIG. 7C shows a problem using the FC method.

図７（ａ）に示すように、ＦＣ法により製造された半導体装置は、一方面に凸状電極２を有する半導体素子１の一方面を一方面に電極１３を有する回路基板３の一方面に向き合わせた状態で互いの電極２，１３を電気的に接続した構成である。半導体素子１と回路基板３との対向間には接合を強化するために樹脂５が介在されている。   As shown in FIG. 7A, the semiconductor device manufactured by the FC method has one surface of a semiconductor element 1 having a convex electrode 2 on one surface and one surface of a circuit board 3 having an electrode 13 on one surface. In this configuration, the electrodes 2 and 13 are electrically connected in a state of facing each other. A resin 5 is interposed between the semiconductor element 1 and the circuit board 3 so as to strengthen the bonding.

この半導体装置の製造方法について図７（ｂ）を用いて説明する。回路基板３の半導体素子１の実装領域に半硬化状の樹脂５を搭載し、半導体素子１の一方面を回路基板３の一方面に向き合わせた状態で半導体素子１の凸状電極２と回路基板３の電極１３とを位置合わせし、その状態で加圧・加熱することにより、半導体素子１の凸状電極２と回路基板３の電極１３を接合するとともに樹脂５を熱硬化させる。
特許第３１５０３４７号 A method for manufacturing this semiconductor device will be described with reference to FIG. A semi-cured resin 5 is mounted on the mounting area of the semiconductor element 1 on the circuit board 3, and the convex electrode 2 of the semiconductor element 1 and the circuit are arranged with one side of the semiconductor element 1 facing one side of the circuit board 3. By aligning with the electrode 13 of the substrate 3 and pressurizing and heating in this state, the convex electrode 2 of the semiconductor element 1 and the electrode 13 of the circuit substrate 3 are joined and the resin 5 is thermoset.
Japanese Patent No. 3150347

上記従来例では、例えば回路基板３の電極１３が隣り合わせに狭いピッチで複数設けられている場合、半導体素子１の凸状電極２も前記同様狭いピッチで複数形成しておく必要があり、そのために、電極１３と凸状電極２とを正確に位置合わせするのが難しい。しかも、半導体素子１の凸状電極２と、回路基板３の電極１３とを加圧する時に、図７（ｃ）に示すように、凸状電極２が電極１３から横に滑り落ちやすい。これらのことから、回路基板３に半導体素子１を正確に実装することが難しい。   In the above conventional example, for example, when a plurality of electrodes 13 of the circuit board 3 are provided adjacent to each other with a narrow pitch, it is necessary to form a plurality of the convex electrodes 2 of the semiconductor element 1 with a narrow pitch as described above. It is difficult to accurately align the electrode 13 and the convex electrode 2. In addition, when the convex electrode 2 of the semiconductor element 1 and the electrode 13 of the circuit board 3 are pressed, the convex electrode 2 is likely to slide sideways from the electrode 13 as shown in FIG. For these reasons, it is difficult to accurately mount the semiconductor element 1 on the circuit board 3.

また、上記従来例では、半導体素子１の素材と回路基板３の素材との線膨張係数に差がある場合、温度変化によって、半導体素子１と回路基板３との対向間隔が大小変化して、凸状電極２と電極１３との接続部に応力が発生しやすくなるため、この接続部の信頼性試験において接続不良が発生するおそれがある。   Further, in the above conventional example, when there is a difference in the linear expansion coefficient between the material of the semiconductor element 1 and the material of the circuit board 3, the facing distance between the semiconductor element 1 and the circuit board 3 changes depending on the temperature change. Since stress is likely to be generated at the connection portion between the convex electrode 2 and the electrode 13, there is a possibility that a connection failure may occur in the reliability test of the connection portion.

本発明は、要するに、半導体素子の電極を凸状とし、回路基板の電極を凹状あるいは貫通孔形状とし、これら凸状電極と凹状電極あるいは貫通孔電極とを半導体素子と回路基板との向き合わせ方向に凹凸嵌合させる形態で電気的に接続している。これにより、回路基板に半導体素子を実装するときに両者が位置ずれしなくなる。また、回路基板と半導体素子とを線膨張係数に差がある素材で形成している場合に、温度変化に伴い回路基板と半導体素子との対向間隔が大小変化しても、凸状電極と凹状電極または貫通孔電極との凹凸嵌合部位に応力が発生しにくくなるので、各電極の接続部で接続不良が発生することを抑制または防止できるようになる。これらの相乗効果として、半導体装置の信頼性が向上する。なお、凹状電極としては、その内底面を回路基板の主表面よりも低い位置にしたものとすることが可能である。また、貫通孔電極は、回路基板に設けた貫通孔に導電処理を行ったもの等とすることが可能である。   In short, in the present invention, the electrode of the semiconductor element is convex, the electrode of the circuit board is concave or through-hole shape, and the convex electrode and the concave electrode or through-hole electrode are aligned in the direction in which the semiconductor element and the circuit board face each other It is electrically connected in a form that is unevenly fitted. Thereby, when mounting a semiconductor element on a circuit board, both do not shift. In addition, when the circuit board and the semiconductor element are formed of materials having a difference in linear expansion coefficient, even if the facing distance between the circuit board and the semiconductor element changes with temperature, the convex electrode and the concave element Since stress is less likely to occur at the concave / convex fitting site with the electrode or the through-hole electrode, it is possible to suppress or prevent the occurrence of poor connection at the connection portion of each electrode. As a synergistic effect, the reliability of the semiconductor device is improved. The concave electrode can have its inner bottom surface positioned lower than the main surface of the circuit board. Further, the through-hole electrode may be one obtained by conducting a conductive treatment on a through-hole provided in the circuit board.

本発明によると、回路基板に半導体素子を実装する時に双方の電極が位置ずれすることを抑制または防止でき、また、両電極の接続部に温度変化に伴う応力が発生しにくくなる等、信頼性の高い半導体装置を提供できる。   According to the present invention, it is possible to suppress or prevent the displacement of both electrodes when mounting a semiconductor element on a circuit board, and it is difficult to generate a stress due to a temperature change at a connection portion of both electrodes. A semiconductor device with high performance can be provided.

本願発明者は、フリップチップボンディング（ＦＣ）法における欠点を考慮した上で鋭意検討を行い、回路基板の電極として凹状電極あるいは貫通孔電極を用いた新規な微細ピッチ接続技術を想到し、本発明に至った。   The inventor of the present application has conducted intensive studies after considering the disadvantages of the flip chip bonding (FC) method, and has come up with a novel fine pitch connection technique using a concave electrode or a through-hole electrode as an electrode of a circuit board. It came to.

以下、図面を参照しながら、本発明の実施の形態を説明する。以下の図面においては、説明の簡潔化のため、実質的に同一の機能を有する構成要素を同一の参照符号で示す。なお、本発明は以下の実施形態に限定されない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of brevity. In addition, this invention is not limited to the following embodiment.

（実施形態１）
図１を参照して、本発明の実施形態１に係る半導体装置を説明する。図１は、実施形態１に係る半導体装置の断面構成を模式的に示している。 (Embodiment 1)
A semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 schematically shows a cross-sectional configuration of the semiconductor device according to the first embodiment.

図１に示した半導体装置は、一方面に凸状電極２を有する半導体素子１と、一方面に凹状電極４を有する回路基板３とを備え、かつ、半導体素子１の一方面を回路基板３の一方面に向き合わせた状態で半導体素子１の凸状電極２を回路基板３の凹状電極４内に挿入することにより互いの電極２，４を電気的に接続した構成である。半導体素子１と回路基板３との対向間には、凸状電極２と凹状電極４の接続を保護するために、樹脂５が介在されている。   The semiconductor device shown in FIG. 1 includes a semiconductor element 1 having a convex electrode 2 on one side and a circuit board 3 having a concave electrode 4 on one side, and the one side of the semiconductor element 1 is circuit board 3. In this state, the electrodes 2 and 4 are electrically connected to each other by inserting the convex electrode 2 of the semiconductor element 1 into the concave electrode 4 of the circuit board 3 in a state of being opposed to the one surface. A resin 5 is interposed between the semiconductor element 1 and the circuit board 3 so as to protect the connection between the convex electrode 2 and the concave electrode 4.

凸状電極２は、半導体素子１の一方面の端部に、図１の紙面奥行き方向に所定ピッチごとに隣り合って複数設けられている。この凸状電極２は、半導体素子１の一方面に形成される配線パターンの端部に形成されるパッド状の電極２ａのうえに、ワイヤーボンディング法、メッキ法などで形成される凸部２ｂを設けたものである。パッド状の電極２ａおよび凸部２ｂは、例えば導電性を有する金属からなる。この導電性を有する金属としては、例えば、金、銅、アルミ、ニッケル、はんだなどとすることができる。   A plurality of convex electrodes 2 are provided adjacent to each other at predetermined pitches in the depth direction of the paper surface of FIG. The convex electrode 2 includes a convex portion 2b formed by a wire bonding method, a plating method, or the like on the pad-shaped electrode 2a formed at the end portion of the wiring pattern formed on one surface of the semiconductor element 1. It is provided. The pad-shaped electrode 2a and the convex portion 2b are made of, for example, a conductive metal. Examples of the conductive metal include gold, copper, aluminum, nickel, and solder.

回路基板３としては、例えば、ビルドアップ基板などが挙げられる。このビルドアップ基板はガラス・エポキシ（エポキシ樹脂含浸ガラス織布）から構成されているコア層７の上に、ビルドアップ層６が形成される構成である。ビルドアップ層６としては、例えばエポキシ樹脂、ガラス・エポキシ、あるいはガラス・アラミド（エポキシ樹脂含浸アラミド不織布）等から構成されている。またその第２の回路基板３の例としては、ガラス・エポキシ基板、全層樹脂ＩＶＨ基板、ポリイミド基板、液晶ポリマ基板、セラミック基板などがあげられる。回路基板３は、図１に示した片面基板の他、両面基板も用いることもでき、あるいは、多層基板を用いることもできる。配線パターンは、例えば、銅箔から構成されている。   Examples of the circuit board 3 include a build-up board. This build-up substrate has a structure in which a build-up layer 6 is formed on a core layer 7 made of glass / epoxy (epoxy resin-impregnated glass woven fabric). The build-up layer 6 is made of, for example, epoxy resin, glass / epoxy, glass / aramid (epoxy resin-impregnated aramid nonwoven fabric), or the like. Examples of the second circuit board 3 include a glass / epoxy board, a full-layer resin IVH board, a polyimide board, a liquid crystal polymer board, and a ceramic board. As the circuit board 3, a double-sided board can be used in addition to the single-sided board shown in FIG. 1, or a multilayer board can be used. The wiring pattern is made of, for example, copper foil.

凹状電極４は、回路基板３の一方面の端部に、図１の紙面奥行き方向に複数個所定ピッチごとに隣り合って複数設けられている。この凹状電極４はその内底面が回路基板３の一方面の主表面より低くなっている。この凹状電極４は、例えば導電性を有する金属からなる。導電性を有する金属としては、例えば、銅、ニッケル、金、アルミ、はんだなどとすることができる。   A plurality of concave electrodes 4 are provided adjacent to each other at a predetermined pitch in the depth direction of the paper surface of FIG. The concave electrode 4 has an inner bottom surface lower than the main surface of one surface of the circuit board 3. The concave electrode 4 is made of, for example, a conductive metal. Examples of the conductive metal include copper, nickel, gold, aluminum, and solder.

樹脂５は、無機フィラーと熱硬化性樹脂とを含む混合物からなる。無機フィラーには、例えば、Ａｌ２Ｏ３、ＭｇＯ、ＢＮ、ＡｌＮまたはＳｉＯ２などを用いることができる。熱硬化性樹脂には、例えば、耐熱性が高いエポキシ樹脂、フェノール樹脂またはシアネート樹脂が好ましい。エポキシ樹脂は、耐熱性が特に高いため特に好ましい。なお、混合物は、さらに分散剤、着色剤、カップリング剤等を含んでいてもよい。なお、無機フィラーや樹脂成分などは特に限定されるものではない。 The resin 5 is made of a mixture containing an inorganic filler and a thermosetting resin. As the inorganic filler, for example, Al 2 O 3 , MgO, BN, AlN, or SiO 2 can be used. As the thermosetting resin, for example, an epoxy resin, a phenol resin, or a cyanate resin having high heat resistance is preferable. Epoxy resins are particularly preferred because of their particularly high heat resistance. The mixture may further contain a dispersant, a colorant, a coupling agent and the like. In addition, an inorganic filler, a resin component, etc. are not specifically limited.

そして、凸状電極２と凹状電極４とを電気的に接続する方法としては、凸状電極２と凹状電極４を直接接合させる方式とすることができる。それ以外には、凸状電極２と凹状電極４とを導電性接着剤、あるいは、はんだを用いて間接的に接合する方式とすることもできる。この導電性接着剤としては、例えば、樹脂中に導電性フィラーを混入したものがあげられる。   As a method for electrically connecting the convex electrode 2 and the concave electrode 4, it is possible to directly join the convex electrode 2 and the concave electrode 4. Other than that, the convex electrode 2 and the concave electrode 4 may be indirectly joined using a conductive adhesive or solder. Examples of the conductive adhesive include those in which a conductive filler is mixed in a resin.

以上説明したように、実施形態１に係る半導体装置では、凸状電極２と凹状電極４とを、半導体素子１と回路基板３との向き合わせ方向に凹凸嵌合させる形態にして電気的に接続している。これにより、回路基板３に半導体素子１を実装するときに両者が位置ずれしなくなる。また、回路基板３と半導体素子１とを線膨張係数に差がある素材で形成している場合に、温度変化に伴い回路基板３と半導体素子１との対向間隔が大小変化しても、凸状電極２と凹状電極４との凹凸嵌合部位に応力が発生しにくくなるので、各電極２，４の接続部で接続不良が発生することを抑制または防止できるようになる。これらの相乗効果として、半導体装置の信頼性が向上する。しかも、凹状電極４の内底面を回路基板３の主表面より低くしているから、凸状電極２と凹状電極４とを位置合わせする作業を簡単に行うことができて、半導体装置全体の薄型化が可能になる。   As described above, in the semiconductor device according to the first embodiment, the convex electrode 2 and the concave electrode 4 are electrically connected in the form of concave and convex fitting in the facing direction of the semiconductor element 1 and the circuit board 3. doing. Thereby, when mounting the semiconductor element 1 on the circuit board 3, both do not shift in position. Further, when the circuit board 3 and the semiconductor element 1 are formed of a material having a difference in linear expansion coefficient, even if the facing distance between the circuit board 3 and the semiconductor element 1 changes with temperature, the convexity is increased. Since stress is less likely to be generated at the concave / convex fitting portion between the electrode 2 and the concave electrode 4, it is possible to suppress or prevent the occurrence of connection failure at the connection portions of the electrodes 2 and 4. As a synergistic effect, the reliability of the semiconductor device is improved. In addition, since the inner bottom surface of the concave electrode 4 is lower than the main surface of the circuit board 3, the operation of aligning the convex electrode 2 and the concave electrode 4 can be easily performed, and the overall thickness of the semiconductor device can be reduced. Can be realized.

次に、上述した実施形態１の半導体装置の製造方法を説明する。   Next, the manufacturing method of the semiconductor device of Embodiment 1 mentioned above is demonstrated.

（１） 半導体素子１上に凸状電極２を形成する方法としては、ワイヤーボンディング法、メッキ法などが挙げられる。   (1) Examples of a method for forming the convex electrode 2 on the semiconductor element 1 include a wire bonding method and a plating method.

（２） 回路基板３に凹状電極４を形成する方法としては、まずコア層７の上に感光性エポキシ樹脂を塗布する（ビルドアップ層６）。次に、予備乾燥を行い、フォトマスクを使用して露光する。露光した部分に対し、溶剤を使用したエッチング装置でビルドアップ層６に穴を開ける。穴があいたら本乾燥して樹脂を硬化させる。引き続き、ビルドアップ層６の表面を過マンガン酸でエッチングし、無電解銅メッキをした後に、全面を電界銅メッキで導体層として必要な厚さまで銅メッキする。その後、サブトラクティブエッチングで凹状電極４及び、配線パターンを形成する。ビルドアップ層を多層構造にする場合は、これらの工程を繰り返す。コア層７の両面にビルドアップ層を配置する場合には、回路基板３の他方面にも上記同様な工程を繰り返す。   (2) As a method of forming the concave electrode 4 on the circuit board 3, first, a photosensitive epoxy resin is applied on the core layer 7 (build-up layer 6). Next, preliminary drying is performed and exposure is performed using a photomask. A hole is made in the build-up layer 6 with an etching apparatus using a solvent in the exposed portion. If there is a hole, dry it and cure the resin. Subsequently, after the surface of the buildup layer 6 is etched with permanganic acid and electroless copper plating is performed, the entire surface is plated with copper to a necessary thickness as a conductor layer by electrolytic copper plating. Thereafter, the concave electrode 4 and the wiring pattern are formed by subtractive etching. When the build-up layer has a multilayer structure, these steps are repeated. When the build-up layer is disposed on both surfaces of the core layer 7, the same process is repeated on the other surface of the circuit board 3.

（３） 回路基板３上の半導体素子１搭載領域に液状の樹脂５を塗布する。   (3) A liquid resin 5 is applied to the semiconductor element 1 mounting region on the circuit board 3.

（４） 凸状電極２と凹状電極４とを接合するように位置あわせをする。   (4) Align so that the convex electrode 2 and the concave electrode 4 are joined.

（５） 半導体素子１を回路基板３に搭載し、この時、半導体素子１の他方面から加圧・加熱を行う。高さばらつきのある凸状電極２や凹状電極４に対し、加圧することで凸状電極２と回路基板３とは安定した接続を得る。また加熱することで、樹脂５が硬化され、凸状電極２と凹状電極４との接続がより強固なものとなる。この加圧、加熱は例えば従来例で説明した図７（ｂ）と同様して行う。このように半導体素子１の凸状電極２を回路基板３の凹状電極４に挿入して凹凸嵌合のような形態にしているために、実装時荷重を加えても、従来例のように半導体素子１側の電極と回路基板３側の電極とで滑って位置ずれするといったことが起きない。よって微細ピッチに対応した半導体装置を安定して製造することができる。   (5) The semiconductor element 1 is mounted on the circuit board 3, and at this time, pressure and heating are performed from the other surface of the semiconductor element 1. The convex electrode 2 and the circuit board 3 are stably connected by applying pressure to the convex electrode 2 and the concave electrode 4 having a variation in height. Further, by heating, the resin 5 is cured, and the connection between the convex electrode 2 and the concave electrode 4 becomes stronger. This pressurization and heating are performed, for example, in the same manner as in FIG. As described above, the convex electrode 2 of the semiconductor element 1 is inserted into the concave electrode 4 of the circuit board 3 so as to have a form of concave / convex fitting. There is no occurrence of slippage between the electrode on the element 1 side and the electrode on the circuit board 3 side. Therefore, the semiconductor device corresponding to the fine pitch can be manufactured stably.

ところで、上記製造方法では、半導体素子１を回路基板３に熱圧着工法で実装する例を挙げたが、半導体素子１の実装時に超音波を加えて、凸状電極２と凹状電極４を接続する超音波接合方式、凸状電極２にはんだ電極を用いたはんだ接合方式、凹状電極４の部分に予めはんだを印刷法あるいはディスペンス法などで塗布しておき、半導体素子１を実装した後、リフロー炉に投入しはんだを溶融することで、凸状電極２と凹状電極４とをはんだを介して接続する方式、さらには凸状電極２の先端あるいは凹状電極４に予め導電性接着剤を塗布しておき、半導体素子１を実装した後、オーブン炉に投入し加熱することで導電性接着剤を硬化させ、凸状電極２と凹状電極４とを導電性接着剤を介して接続する方式等とすることができる。   By the way, although the example which mounts the semiconductor element 1 in the circuit board 3 with the thermocompression bonding method was given in the said manufacturing method, the ultrasonic wave was added at the time of mounting of the semiconductor element 1, and the convex electrode 2 and the concave electrode 4 are connected. An ultrasonic bonding method, a solder bonding method using a solder electrode for the convex electrode 2, solder is applied to the concave electrode 4 in advance by a printing method or a dispensing method, and the semiconductor element 1 is mounted and then a reflow furnace And then melting the solder to connect the convex electrode 2 and the concave electrode 4 via the solder, and further applying a conductive adhesive to the tip of the convex electrode 2 or the concave electrode 4 in advance. After the semiconductor element 1 is mounted, the conductive adhesive is cured by putting it in an oven furnace and heating, and the convex electrode 2 and the concave electrode 4 are connected via the conductive adhesive. be able to.

また、上記（３）で樹脂５を液状として説明したが、半硬化状態でシート状の樹脂を用いてもよい。また、樹脂５は、半導体素子１の実装前に回路基板３に塗布する方法を用いて形成する例を説明したが、半導体素子１を回路基板３に実装した後に、半導体素子１と回路基板３との対向間に注入する方法で形成してもよい。さらに、凸状電極２と凹状電極４の接合が強固な場合には、樹脂５をなくしてもよい。その場合、樹脂５の塗布工程を省けるので工程を簡略化できる。   In the above (3), the resin 5 is described as a liquid, but a sheet-like resin may be used in a semi-cured state. Also, the example in which the resin 5 is formed using the method of applying to the circuit board 3 before mounting the semiconductor element 1 has been described. However, after the semiconductor element 1 is mounted on the circuit board 3, the semiconductor element 1 and the circuit board 3 are formed. You may form by the method of inject | pouring between facing. Further, when the bonding between the convex electrode 2 and the concave electrode 4 is strong, the resin 5 may be omitted. In that case, the application process of the resin 5 can be omitted, so that the process can be simplified.

（実施形態２）
図２（ａ）（ｂ）を参照して、本発明の実施形態２に係る半導体装置を説明する。図２（ａ）（ｂ）は、本実施形態の半導体装置の断面構成を模式的に示している。 (Embodiment 2)
With reference to FIGS. 2A and 2B, a semiconductor device according to Embodiment 2 of the present invention will be described. 2A and 2B schematically show a cross-sectional configuration of the semiconductor device of this embodiment.

図２（ａ）に示した半導体装置は、一方面に凸状電極２を有する半導体素子１と、一方面に貫通孔電極８を有する回路基板３とを備え、かつ、半導体素子１の一方面を回路基板３の一方面に向き合わせた状態で半導体素子１の凸状電極２を回路基板３の貫通孔電極４内に挿入することにより互いの電極２，８を電気的に接続した構成である。半導体素子１と回路基板３との対向間には、凸状電極２と貫通孔電極８の接続を保護するために、樹脂５が介在されている。   The semiconductor device shown in FIG. 2A includes a semiconductor element 1 having a convex electrode 2 on one side and a circuit board 3 having a through-hole electrode 8 on one side, and one side of the semiconductor element 1. With the electrode 2 and 8 electrically connected to each other by inserting the convex electrode 2 of the semiconductor element 1 into the through-hole electrode 4 of the circuit board 3 while facing the one surface of the circuit board 3. is there. A resin 5 is interposed between the semiconductor element 1 and the circuit board 3 so as to protect the connection between the convex electrode 2 and the through-hole electrode 8.

凸状電極２は、半導体素子１の一方面の端部に、図２（ａ）の紙面奥行き方向に所定ピッチごとに隣り合って複数設けられている。この凸状電極２は、半導体素子１の一方面に形成される配線パターンの端部に形成されるパッド状の電極２ａのうえに、ワイヤーボンディング法、メッキ法などで形成される凸部２ｂを設けたものである。パッド状の電極２ａおよび凸部２ｂは、例えば導電性を有する金属からなる。この導電性を有する金属としては、例えば、金、銅、アルミ、ニッケル、はんだなどとすることができる。   A plurality of convex electrodes 2 are provided adjacent to each other at predetermined pitches in the depth direction of the paper surface of FIG. The convex electrode 2 includes a convex portion 2b formed by a wire bonding method, a plating method, or the like on the pad-shaped electrode 2a formed at the end portion of the wiring pattern formed on one surface of the semiconductor element 1. It is provided. The pad-shaped electrode 2a and the convex portion 2b are made of, for example, a conductive metal. Examples of the conductive metal include gold, copper, aluminum, nickel, and solder.

回路基板３としては、例えば、ポリイミド基板、液晶ポリマ基板、ガラス・エポキシ基板、ビルドアップ基板、全層樹脂ＩＶＨ基板、セラミック基板などがあげられる。この回路基板３は、片面基板、両面基板、多層基板を用いることもできる。回路基板３の一方面には配線パターン９が設けられており、この配線パターンの端部に貫通孔電極８が形成されている。配線パターン９は、例えば、銅箔から構成されている。   Examples of the circuit board 3 include a polyimide substrate, a liquid crystal polymer substrate, a glass / epoxy substrate, a build-up substrate, a full-layer resin IVH substrate, and a ceramic substrate. The circuit board 3 can be a single-sided board, a double-sided board, or a multilayer board. A wiring pattern 9 is provided on one surface of the circuit board 3, and a through-hole electrode 8 is formed at an end of the wiring pattern. The wiring pattern 9 is made of copper foil, for example.

貫通孔電極８は、回路基板３に厚み方向に貫通して設けられており、図２（ａ）の紙面奥行き方向に所定ピッチごとに隣り合わせに複数設けられている。この貫通孔電極８は、例えば導電性を有する金属からなる。導電性を有する金属としては、例えば、銅、ニッケル、金、アルミ、はんだなどとすることができる。   The through-hole electrodes 8 are provided so as to penetrate the circuit board 3 in the thickness direction, and a plurality of the through-hole electrodes 8 are provided adjacent to each other at a predetermined pitch in the depth direction of the paper surface of FIG. The through-hole electrode 8 is made of a conductive metal, for example. Examples of the conductive metal include copper, nickel, gold, aluminum, and solder.

樹脂５は、無機フィラーと熱硬化性樹脂とを含む混合物からなる。無機フィラーには、例えば、Ａｌ２Ｏ３、ＭｇＯ、ＢＮ、ＡｌＮまたはＳｉＯ２などを用いることができる。熱硬化性樹脂には、例えば、耐熱性が高いエポキシ樹脂、フェノール樹脂またはシアネート樹脂が好ましい。エポキシ樹脂は、耐熱性が特に高いため特に好ましい。なお、混合物は、さらに分散剤、着色剤、カップリング剤等を含んでいてもよい。なお、無機フィラーや樹脂成分などは特に限定されるものではない。 The resin 5 is made of a mixture containing an inorganic filler and a thermosetting resin. As the inorganic filler, for example, Al 2 O 3 , MgO, BN, AlN, or SiO 2 can be used. As the thermosetting resin, for example, an epoxy resin, a phenol resin, or a cyanate resin having high heat resistance is preferable. Epoxy resins are particularly preferred because of their particularly high heat resistance. The mixture may further contain a dispersant, a colorant, a coupling agent and the like. In addition, an inorganic filler, a resin component, etc. are not specifically limited.

そして、凸状電極２と貫通孔型電極８とを電気的に接続する方法としては、凸状電極２と貫通孔型電極８を直接接合させる方式とすることができる。それ以外には、凸状電極２と貫通孔電極８の間に導電性接着剤、あるいは、はんだを介して間接的に接合する方式とすることができる。この導電性接着剤としては、例えば、樹脂中に導電性フィラーを混入したものがあげられる。   And as a method of electrically connecting the convex electrode 2 and the through-hole type electrode 8, it can be set as the system which joins the convex electrode 2 and the through-hole type electrode 8 directly. Other than that, it is possible to adopt a system in which the convex electrode 2 and the through-hole electrode 8 are indirectly joined via a conductive adhesive or solder. Examples of the conductive adhesive include those in which a conductive filler is mixed in a resin.

以上説明した実施形態２の半導体装置では、凸状電極２が貫通孔電極８に半導体素子１と回路基板３とを向き合わせる方向から挿入される形態で接続している。これにより、回路基板３に半導体素子１を実装するときに両者が位置ずれしなくなる。また、回路基板３と半導体素子１とを線膨張係数に差がある素材で形成している場合に、温度変化に伴い回路基板３と半導体素子１との対向間隔が大小変化しても、凸状電極２と貫通孔電極８との凹凸嵌合部位に応力が発生しにくくなるので、各電極２，８の接続部で接続不良が発生することを抑制または防止できるようになる。これらの相乗効果として、半導体装置の信頼性が向上する。   In the semiconductor device of the second embodiment described above, the convex electrode 2 is connected to the through-hole electrode 8 in such a manner that it is inserted from the direction in which the semiconductor element 1 and the circuit board 3 face each other. Thereby, when mounting the semiconductor element 1 on the circuit board 3, both do not shift in position. Further, when the circuit board 3 and the semiconductor element 1 are formed of a material having a difference in linear expansion coefficient, even if the facing distance between the circuit board 3 and the semiconductor element 1 changes with temperature, the convexity is increased. Since stress is less likely to occur at the concave / convex fitting portion between the electrode 2 and the through-hole electrode 8, it is possible to suppress or prevent the occurrence of poor connection at the connecting portions of the electrodes 2 and 8. As a synergistic effect, the reliability of the semiconductor device is improved.

ところで、上記半導体装置において、図２（ｂ）に示すように、凸状電極２の長さが回路基板３の厚みより長いものを用いて、凸状電極２を回路基板３の他方面にまで突き出させた構造とすることができる。この構造の場合、フローはんだ法などにより、回路基板３の他方面から突き出た凸状電極２部分をはんだ接続することで、接続をより強固なものにできる。   By the way, in the semiconductor device, as shown in FIG. 2B, the convex electrode 2 is extended to the other surface of the circuit board 3 by using the one having a length of the convex electrode 2 longer than the thickness of the circuit board 3. The protruding structure can be obtained. In the case of this structure, the connection can be made stronger by soldering the protruding electrode 2 portion protruding from the other surface of the circuit board 3 by a flow soldering method or the like.

次に、図３（ａ）（ｂ）を参照して、上述した実施形態２に係る半導体装置の製造方法を説明する。   Next, with reference to FIGS. 3A and 3B, a method of manufacturing the semiconductor device according to the second embodiment will be described.

（１） 半導体素子１上に凸状電極２を形成する方法としては、ワイヤーボンディング法、メッキ法などが挙げられる。   (1) Examples of a method for forming the convex electrode 2 on the semiconductor element 1 include a wire bonding method and a plating method.

（２） 回路基板３に貫通孔電極８を形成する方法としては、回路基板３の必要な箇所に、ドリル、パンチ、レーザ、ドライエッチング、ウェットエッチング等で回路基板３の厚み方向に貫通する孔を開ける。この貫通する孔の内周壁面および開口部分に、導体をメッキ法などにより被覆することにより貫通孔電極８を得る。メッキ法の一例としては、無電解銅メッキをした後に、全面を電界銅メッキで導体層として必要な厚さまで銅メッキする。その後、サブトラクティブエッチングで貫通孔電極８及び、配線パターン９を形成する。   (2) As a method of forming the through-hole electrode 8 in the circuit board 3, a hole penetrating in the thickness direction of the circuit board 3 by a drill, punch, laser, dry etching, wet etching, or the like at a necessary portion of the circuit board 3. Open. The through-hole electrode 8 is obtained by covering the inner peripheral wall surface and the opening of the through-hole with a conductor by plating or the like. As an example of the plating method, after electroless copper plating, the entire surface is plated with copper to the required thickness as a conductor layer by electrolytic copper plating. Thereafter, the through-hole electrode 8 and the wiring pattern 9 are formed by subtractive etching.

引き続き図３（ａ）に示すように、
（３） 回路基板３上の半導体素子１搭載領域に液状の樹脂５を塗布する。 Continuing as shown in FIG.
(3) A liquid resin 5 is applied to the semiconductor element 1 mounting region on the circuit board 3.

（４） 凸状電極２と貫通孔電極８とを接合するように位置あわせをする。   (4) Align so that the convex electrode 2 and the through-hole electrode 8 are joined.

（５） 半導体素子１を回路基板３に搭載し、この時、半導体素子１の他方面から加圧・加熱を行う。加圧することで凸状電極２は貫通孔電極８内に挿入される。また加熱することで、樹脂５が熱硬化され、凸状電極２と貫通孔電極８との接続がより強固なものとなる。このように半導体素子１の凸状電極２を回路基板３の貫通孔電極８に挿入して凹凸嵌合のような形態にしているために、実装時荷重を加えても、従来例のように半導体素子１側の電極と回路基板３側の電極とで滑って位置ずれするといったことが起きない。よって微細ピッチに対応した半導体装置を安定して製造することができる。   (5) The semiconductor element 1 is mounted on the circuit board 3, and at this time, pressure and heating are performed from the other surface of the semiconductor element 1. The convex electrode 2 is inserted into the through-hole electrode 8 by applying pressure. Further, by heating, the resin 5 is thermoset, and the connection between the convex electrode 2 and the through-hole electrode 8 becomes stronger. Thus, since the convex electrode 2 of the semiconductor element 1 is inserted into the through-hole electrode 8 of the circuit board 3 so as to form a concave-convex fitting, even if a load during mounting is applied, There is no possibility that the electrode on the semiconductor element 1 side and the electrode on the circuit board 3 side slip and are displaced. Therefore, the semiconductor device corresponding to the fine pitch can be manufactured stably.

ところで、上記製造方法では、半導体素子１を回路基板３に熱圧着工法で実装する例を挙げたが、半導体素子１の実装時に超音波を加えて、凸状電極２と貫通孔電極８を接続する超音波接合方式、凸状電極２にはんだ電極を用いたはんだ接合方式、貫通孔電極８の部分に予めはんだを印刷法あるいはディスペンス法などで塗布しておき、半導体素子１を実装した後、リフロー炉に投入し、はんだを溶融することで、凸状電極２と貫通孔電極８とをはんだを介して接続する方式、さらには凸状電極２の先端あるいは貫通孔電極８に予め導電性接着剤を塗布しておき、半導体素子１を実装した後、オーブン炉に投入し加熱することで導電性接着剤を硬化させ、凸状電極２と貫通孔電極８とを導電性接着剤を介して接続する方式等とすることができる。   In the above manufacturing method, the semiconductor element 1 is mounted on the circuit board 3 by the thermocompression bonding method. However, an ultrasonic wave is applied when the semiconductor element 1 is mounted to connect the convex electrode 2 and the through-hole electrode 8. After the semiconductor element 1 is mounted, the ultrasonic bonding method, the solder bonding method using a solder electrode for the convex electrode 2, solder is applied in advance to the through hole electrode 8 by a printing method or a dispensing method, etc. A method of connecting the convex electrode 2 and the through-hole electrode 8 via the solder by pouring into a reflow furnace and melting the solder, and further conductive bonding in advance to the tip of the convex electrode 2 or the through-hole electrode 8 After the agent is applied and the semiconductor element 1 is mounted, the conductive adhesive is cured by putting it in an oven furnace and heating, and the convex electrode 2 and the through-hole electrode 8 are connected via the conductive adhesive. Can be connected system etc. .

また、上記（３）で樹脂５を液状として説明したが、半硬化状態でシート状の樹脂を用いてもよい。また、樹脂５は、半導体素子１の実装前に回路基板３に塗布する方法を用いて形成する例を説明したが、半導体素子１を回路基板３に実装した後に、半導体素子１と回路基板３との対向間に注入する方法で形成してもよい。さらに、凸状電極２と貫通孔電極８の接合が強固な場合には、樹脂５をなくしてもよい。その場合、樹脂５の塗布工程を省けるので工程を簡略化できる。   In the above (3), the resin 5 is described as a liquid, but a sheet-like resin may be used in a semi-cured state. Also, the example in which the resin 5 is formed using the method of applying to the circuit board 3 before mounting the semiconductor element 1 has been described. However, after the semiconductor element 1 is mounted on the circuit board 3, the semiconductor element 1 and the circuit board 3 are formed. You may form by the method of inject | pouring between facing. Furthermore, when the bonding between the convex electrode 2 and the through-hole electrode 8 is strong, the resin 5 may be omitted. In that case, the application process of the resin 5 can be omitted, so that the process can be simplified.

この他、凸状電極２の長さが回路基板３の厚さよりも長いものを用い、凸状電極２が回路基板３の反対面にまで突き抜けるように加圧しながら実装を行うと図２（ｂ）に示したような、凸状電極２が回路基板３の反対面まで突き抜けた構造を作製できる。実装後、フローはんだ法により、凸状電極２において回路基板３の他方面へ突き出た部分をはんだ接続することで、接続をより強固なものにできる。   In addition, when the convex electrode 2 is longer than the thickness of the circuit board 3 and mounted so that the convex electrode 2 penetrates to the opposite surface of the circuit board 3 and is mounted, FIG. A structure in which the convex electrode 2 penetrates to the opposite surface of the circuit board 3 as shown in FIG. After mounting, by connecting the portion of the convex electrode 2 protruding to the other surface of the circuit board 3 by a flow solder method, the connection can be made stronger.

（実施形態３）
図４を参照して、本発明の実施形態３に係る半導体装置を説明する。図４は、実施形態３の半導体装置の断面構成を模式的に示している。 (Embodiment 3)
A semiconductor device according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 4 schematically shows a cross-sectional configuration of the semiconductor device of the third embodiment.

図４に示した半導体装置は、半導体素子１の一方面を回路基板３の一方面に向き合わせた状態で半導体素子１の凸状電極２を回路基板３の貫通孔電極８内に挿入することにより互いの電極２，８を電気的に接続した構成であり、さらに、図２（ｂ）で示した構造と同様に、凸状電極２を回路基板３の他方面にまで突き出させているとともに、回路基板３の他方面に所定厚みの樹脂５を介して新たな第２の半導体素子１０を貼り合わせて、この第２の半導体素子１０に凸状電極２において回路基板３の他方面に突き出ている部分の少なくとも一つを接続している構造になっている。   In the semiconductor device shown in FIG. 4, the convex electrode 2 of the semiconductor element 1 is inserted into the through-hole electrode 8 of the circuit board 3 with one side of the semiconductor element 1 facing the one side of the circuit board 3. The electrodes 2 and 8 are electrically connected to each other, and the convex electrode 2 is projected to the other surface of the circuit board 3 as in the structure shown in FIG. Then, a new second semiconductor element 10 is bonded to the other surface of the circuit board 3 via a resin 5 having a predetermined thickness, and the second semiconductor element 10 protrudes from the other surface of the circuit board 3 at the convex electrode 2. It is the structure which has connected at least one of the part which is.

この実施形態３において、各構成部材の詳細については実施形態２で説明したものと同様なので説明を省略する。   In the third embodiment, the details of the constituent members are the same as those described in the second embodiment, and a description thereof will be omitted.

このような二つの半導体素子１，１０を用いる例としては、例えばロジックとメモリとの組み合わせ、メモリとメモリとの組み合わせ、さらにはロジックとロジックとの組み合わせ等がある。例えば、ロジックとメモリとの組み合わせの場合、半導体素子１と第２の半導体素子１０とが単一の凸状電極２によって短い距離で接続されているために、信号のやり取りがスムーズになり、高機能な半導体装置を提供できる。また、単一の凸状電極２で接続しているので、厚みが薄い半導体装置を提供できる。   Examples of using such two semiconductor elements 1 and 10 include a combination of logic and memory, a combination of memory and memory, and a combination of logic and logic. For example, in the case of a combination of logic and memory, the semiconductor element 1 and the second semiconductor element 10 are connected by a single convex electrode 2 at a short distance. A functional semiconductor device can be provided. Moreover, since it connects with the single convex electrode 2, a thin semiconductor device can be provided.

また同時に、凸状電極２を貫通孔電極８に挿入する形で接続しているので、上記実施形態１，２と同様に、両電極２，８の位置合わせが簡単かつ正確に行えるという効果や、半導体素子１と回路基板３との線膨張係数の差に基づく両電極２，８の接続不良が発生しにくくなるという効果が得られ、半導体装置の信頼性が向上する。   At the same time, since the convex electrode 2 is connected so as to be inserted into the through-hole electrode 8, as in the first and second embodiments, the effect that the electrodes 2 and 8 can be easily and accurately aligned, In addition, an effect that connection failure between the electrodes 2 and 8 based on the difference in linear expansion coefficient between the semiconductor element 1 and the circuit board 3 is less likely to occur is obtained, and the reliability of the semiconductor device is improved.

なお、半導体素子１と凸状電極２との接合、凸状電極２と貫通孔電極８との接合、ならびに凸状電極２と第２の半導体素子１０との接合が、それぞれ強固な場合には、樹脂５は無くてもよい。また、凸状電極２において回路基板３から突き出た部分を第２の半導体素子１０に接続した構成について説明したが、第２の半導体素子１０が第２の半導体装置であってもよい。   When the bonding between the semiconductor element 1 and the convex electrode 2, the bonding between the convex electrode 2 and the through-hole electrode 8, and the bonding between the convex electrode 2 and the second semiconductor element 10 are strong, respectively. The resin 5 may be omitted. Moreover, although the structure which connected the part protruded from the circuit board 3 in the convex electrode 2 to the 2nd semiconductor element 10 was demonstrated, the 2nd semiconductor element 10 may be a 2nd semiconductor device.

次に、図５（ａ）（ｂ）を参照して、上述した実施形態３の製造方法を説明する。   Next, with reference to FIGS. 5A and 5B, the manufacturing method of the above-described third embodiment will be described.

半導体素子１に凸状電極２を形成する方法と、回路基板３に貫通孔電極８を形成する方法は実施形態２に記載した方法と同じとするので説明を省略する。   Since the method for forming the convex electrode 2 on the semiconductor element 1 and the method for forming the through-hole electrode 8 on the circuit board 3 are the same as those described in the second embodiment, the description thereof is omitted.

そして、図５（ａ）に示すように、まず、回路基板３において半導体素子１の搭載領域、および第２の半導体素子１０の搭載領域に液状の樹脂５を塗布する。この後、凸状電極２と貫通孔電極８および第２の半導体素子１０を接合するように位置あわせをし、図５（ｂ）に示すように、第２の半導体素子１０を受けた状態で、半導体素子１の他方面側から加圧と加熱を行う。加圧することで凸状電極２は貫通孔電極８を突き出て第２の半導体素子１０の一方面に到達し、第２の半導体素子１０に接合する。これにより、半導体素子１、回路基板３、第２の半導体素子１０は電気的に接続される。また加熱することで、樹脂５が熱硬化され、凸状電極２と貫通孔電極８との接続および凸状電極２と両半導体素子１，１０との接続がより強固なものとなる。このように二つの半導体素子１，１０を個別に実装するのではなく、一括して実装していれば、製造コストの削減が可能となる。   Then, as shown in FIG. 5A, first, a liquid resin 5 is applied to the mounting region of the semiconductor element 1 and the mounting region of the second semiconductor element 10 on the circuit board 3. After that, the convex electrode 2, the through-hole electrode 8 and the second semiconductor element 10 are aligned so that the second semiconductor element 10 is received as shown in FIG. Then, pressurization and heating are performed from the other surface side of the semiconductor element 1. By applying pressure, the convex electrode 2 protrudes from the through-hole electrode 8, reaches one surface of the second semiconductor element 10, and is joined to the second semiconductor element 10. Thereby, the semiconductor element 1, the circuit board 3, and the second semiconductor element 10 are electrically connected. Also, by heating, the resin 5 is thermoset, and the connection between the convex electrode 2 and the through-hole electrode 8 and the connection between the convex electrode 2 and both the semiconductor elements 1 and 10 become stronger. Thus, if the two semiconductor elements 1 and 10 are not mounted individually but are mounted together, the manufacturing cost can be reduced.

ところで、上記製造方法では、半導体素子１と第２の半導体素子１０とを回路基板３に熱圧着工法で実装する例を挙げたが、超音波を加えて凸状電極２と貫通孔電極８とを接続するとともに凸状電極２と第２の半導体素子１０とを接続する超音波接合方式、凸状電極２にはんだ電極を用いたはんだ接合方式とすることができる。   By the way, in the above manufacturing method, the example in which the semiconductor element 1 and the second semiconductor element 10 are mounted on the circuit board 3 by the thermocompression bonding method has been described. However, by applying ultrasonic waves, the convex electrode 2 and the through-hole electrode 8 And an ultrasonic bonding method in which the convex electrode 2 and the second semiconductor element 10 are connected, and a solder bonding method in which a solder electrode is used for the convex electrode 2.

また、上記製造方法では樹脂５を液状として説明したが、半硬化状態でシート状の樹脂を用いてもよい。また、樹脂５は、半導体素子１および第２の半導体素子１０の実装前に回路基板３に塗布する方法を用いて説明したが、半導体素子１および第２の半導体素子１０を回路基板３に実装した後に、半導体素子１および第２の半導体素子１０と回路基板３との各対向間に注入する方法で形成してもよい。さらに、凸状電極２と貫通孔電極８およびそれぞれの半導体素子との接合が強固な場合には、樹脂５をなくしてもよい。その場合、樹脂５の塗布工程を省けるので工程を簡略化できる。   Moreover, although the said manufacturing method demonstrated resin 5 as a liquid, you may use sheet-like resin in a semi-hardened state. Further, the resin 5 has been described using the method of applying the resin 5 to the circuit board 3 before the semiconductor element 1 and the second semiconductor element 10 are mounted. However, the semiconductor element 1 and the second semiconductor element 10 are mounted on the circuit board 3. After that, the semiconductor element 1 and the second semiconductor element 10 and the circuit board 3 may be formed by being injected between the opposing surfaces. Furthermore, the resin 5 may be omitted when the bonding between the convex electrode 2 and the through-hole electrode 8 and each semiconductor element is strong. In that case, the application process of the resin 5 can be omitted, so that the process can be simplified.

この他、半導体素子１の他方面側から荷重と加熱を与えると同時に、第２の半導体素子１０の他方面側からも加熱することができ、その場合、プロセスの短時間化が可能となる。さらに、半導体素子１および第２の半導体素子１０の実装時に、半導体素子１の裏面から同時に超音波を加えて、凸状電極２と貫通孔電極８および第２の半導体素子１０とを接続する方式でもよい。   In addition, a load and heating can be applied from the other surface side of the semiconductor element 1, and at the same time, heating can be performed from the other surface side of the second semiconductor element 10. In this case, the process can be shortened. Further, when the semiconductor element 1 and the second semiconductor element 10 are mounted, an ultrasonic wave is simultaneously applied from the back surface of the semiconductor element 1 to connect the convex electrode 2 to the through-hole electrode 8 and the second semiconductor element 10. But you can.

（実施形態４）
図６（ａ）を参照して、本発明の実施形態４に係る半導体装置を説明する。図６（ａ）は、実施形態４の半導体装置の断面構成を模式的に示している。 (Embodiment 4)
A semiconductor device according to Embodiment 4 of the present invention will be described with reference to FIG. FIG. 6A schematically shows a cross-sectional configuration of the semiconductor device of the fourth embodiment.

図６（ａ）に示す半導体装置は、実施形態２に述べた構造を基本としたものであり、これに加え回路基板３をフレキシブル基板とし、半導体素子１の他方面に第２の回路基板１１の一方面を向き合わせた状態で接着剤などで取り付け、この第２の回路基板１１の一方面に有する電極１１ａをフレキシブル基板からなる回路基板３の電極８ａに導電性材料１２を介して電気的に接続している。この回路基板３の電極８ａは、貫通孔電極８に図示しない配線パターンを通じて電気的に接続されている。つまり、半導体素子１の凸状電極２と第２の回路基板１１の電極１１ａとをフレキシブル基板からなる回路基板３で中継して電気的に接続した構成になっている。   The semiconductor device shown in FIG. 6A is based on the structure described in the second embodiment. In addition to this, the circuit board 3 is a flexible board, and the second circuit board 11 is provided on the other surface of the semiconductor element 1. The electrode 11a having one surface of the second circuit board 11 is electrically attached to the electrode 8a of the circuit board 3 made of a flexible substrate through the conductive material 12 with the one surface of the second circuit board 11 being attached with an adhesive or the like. Connected to. The electrode 8a of the circuit board 3 is electrically connected to the through-hole electrode 8 through a wiring pattern (not shown). In other words, the convex electrode 2 of the semiconductor element 1 and the electrode 11a of the second circuit board 11 are relayed and electrically connected by the circuit board 3 made of a flexible board.

このように回路基板３をフレキシブル基板とすることで第２の回路基板１１などへの接続が簡単に対応できるようになる等、いろんな態様での実装が幅広く行うことが可能になる。もちろん実施形態２で述べた効果も兼ね備えている。   Thus, by using the circuit board 3 as a flexible board, the connection to the second circuit board 11 and the like can be easily accommodated, and various mountings can be performed widely. Of course, it also has the effect described in the second embodiment.

フレキシブル基板からなる回路基板３としては、例えば、ポリイミド基板、液晶ポリマ基板、ガラス・エポキシ基板、ビルドアップ基板、全層樹脂ＩＶＨ基板などがあげられる。また、このフレキシブル基板からなる回路基板３は、両面基板、多層基板を用いることができる。図示しないが回路基板３に形成される配線パターンは、例えば、銅箔から構成することができる。このフレキシブル基板からなる回路基板３の厚みは、十分な柔軟性を確保するうえで、例えば１００μｍ以下とするのが好ましい。   Examples of the circuit board 3 made of a flexible substrate include a polyimide substrate, a liquid crystal polymer substrate, a glass / epoxy substrate, a build-up substrate, and a full-layer resin IVH substrate. The circuit board 3 made of this flexible board can be a double-sided board or a multilayer board. Although not shown, the wiring pattern formed on the circuit board 3 can be made of, for example, copper foil. The thickness of the circuit board 3 made of this flexible substrate is preferably set to 100 μm or less, for example, in order to ensure sufficient flexibility.

第２の回路基板１１としては、例えば、ガラス・エポキシ基板、ビルドアップ基板、全層樹脂ＩＶＨ基板、ポリイミド基板、液晶ポリマ基板、セラミック基板などがあげられる。また、第２の回路基板１１は、片面基板、両面基板、多層基板を用いることもできる。この第２の回路基板１１に形成される電極１１ａは、例えば、銅箔から構成されている。   Examples of the second circuit board 11 include a glass / epoxy board, a build-up board, a full-layer resin IVH board, a polyimide board, a liquid crystal polymer board, and a ceramic board. The second circuit board 11 can be a single-sided board, a double-sided board, or a multilayer board. The electrode 11a formed on the second circuit board 11 is made of, for example, copper foil.

導電性材料１２は、例えば導電性を有する金属、あるいは導電性接着剤、あるいは導電性金属＋導電性接着剤などとすることができる。この導電性を有する金属としては、例えば、はんだ、金、銅、アルミ、ニッケル、はんだなどを用いることができる。また、導電性接着剤としては、樹脂中に導電性フィラーを混入したものがあげられる。   The conductive material 12 can be, for example, a conductive metal, a conductive adhesive, or a conductive metal + conductive adhesive. For example, solder, gold, copper, aluminum, nickel, solder, or the like can be used as the conductive metal. Moreover, as a conductive adhesive, what mixed the conductive filler in resin is mention | raise | lifted.

半導体素子１の他方面と第２の回路基板１１の一方面とを固定するための接着剤として、例えば熱伝導率の高い接着剤などを用いれば、半導体素子１の放熱性が向上し、高機能な半導体装置を提供できる。   If, for example, an adhesive having a high thermal conductivity is used as an adhesive for fixing the other surface of the semiconductor element 1 and the one surface of the second circuit board 11, the heat dissipation of the semiconductor element 1 is improved. A functional semiconductor device can be provided.

その他の構成材料に関しては実施形態２と同様なので説明は省略する。   Since other constituent materials are the same as those in the second embodiment, the description thereof is omitted.

ここで、図６（ａ）に示した半導体装置の製造方法を説明する。   Here, a manufacturing method of the semiconductor device shown in FIG.

半導体素子１に凸状電極２を形成する方法と、回路基板３に貫通孔電極８を形成する方法は実施形態２に記載した方法と同じとするので説明を省略する。凸状電極２と貫通孔電極８を接続する方法についても実施形態２に記載した方法と同じとするので説明を省略する。   Since the method for forming the convex electrode 2 on the semiconductor element 1 and the method for forming the through-hole electrode 8 on the circuit board 3 are the same as those described in the second embodiment, the description thereof is omitted. Since the method for connecting the convex electrode 2 and the through-hole electrode 8 is the same as that described in the second embodiment, the description thereof is omitted.

そして、フレキシブル基板からなる回路基板３と第２の回路基板１１とを接続する方法としては、例えば予めクリームはんだを第２の回路基板１１あるいは回路基板３の所定位置にディスペンス法あるいは印刷により塗布した後、回路基板３を位置あわせして第２の回路基板１１に搭載する。その後、リフロー炉に投入することで加熱し、はんだを溶融させて回路基板３と第２の回路基板１１とを電気的に接続する。回路基板３を第２の回路基板１１に接続するほかの例としては、予め導電性接着剤を第２の回路基板１１あるいは回路基板３の所定位置にディスペンス法あるいは印刷により塗布した後、回路基板３を位置あわせして第２の回路基板１１に搭載する。その後、リフロー炉あるいはオーブンに投入し、加熱することで導電性接着剤を硬化させて回路基板３と第２の回路基板１１とを電気的に接続する方法がある。なお、半導体素子１の裏面と第２の回路基板１１とを固定する必要がある場合には次のような方法がある。回路基板３を第２の回路基板１１に搭載する前に、第２の回路基板１１の半導体素子１の搭載領域あるいは半導体素子１の裏面にディスペンス法あるいは印刷法により接着剤を塗布しておき、半導体素子１と第２の回路基板１１とを接着する工程を含んでもよい。これにより半導体素子１は、第２の回路基板１１に固定され安定する。また半導体素子１の放熱性も良好になる。接着剤の種類としては熱硬化型を選択した場合は、半導体素子１を第２の回路基板１１に搭載後、加熱することで接着剤を硬化させる。   As a method for connecting the circuit board 3 made of a flexible substrate and the second circuit board 11, for example, cream solder is applied in advance to the second circuit board 11 or a predetermined position of the circuit board 3 by a dispensing method or printing. Thereafter, the circuit board 3 is aligned and mounted on the second circuit board 11. Thereafter, the circuit board 3 and the second circuit board 11 are electrically connected by heating them by putting them in a reflow furnace and melting the solder. As another example of connecting the circuit board 3 to the second circuit board 11, a conductive adhesive is previously applied to the second circuit board 11 or a predetermined position of the circuit board 3 by a dispensing method or printing, and then the circuit board is used. 3 is aligned and mounted on the second circuit board 11. Thereafter, there is a method in which the circuit board 3 and the second circuit board 11 are electrically connected by putting them into a reflow furnace or oven and curing the conductive adhesive by heating. In addition, when it is necessary to fix the back surface of the semiconductor element 1 and the 2nd circuit board 11, there exists the following method. Before the circuit board 3 is mounted on the second circuit board 11, an adhesive is applied to the mounting area of the semiconductor element 1 on the second circuit board 11 or the back surface of the semiconductor element 1 by a dispensing method or a printing method, A step of bonding the semiconductor element 1 and the second circuit board 11 may be included. Thereby, the semiconductor element 1 is fixed to the second circuit board 11 and stabilized. Also, the heat dissipation of the semiconductor element 1 is improved. When the thermosetting type is selected as the type of adhesive, the adhesive is cured by heating after mounting the semiconductor element 1 on the second circuit board 11.

なお、凸状電極２と貫通孔電極８とを接続する工程と、フレキシブル基板からなる回路基板３と第２の回路基板１１とを接続する工程と、半導体素子１と第２の回路基板１１とを固定する工程とはどの順番を先にやっても良い。   In addition, the process of connecting the convex electrode 2 and the through-hole electrode 8, the process of connecting the circuit board 3 which consists of a flexible substrate, and the 2nd circuit board 11, and the semiconductor element 1 and the 2nd circuit board 11 Any order may be performed first with the process of fixing.

なお、この製造方法において、第２の回路基板１１より上の基本構造については実施形態２に述べた構造を用いて説明したが、基本構造は実施形態１に述べた構造であり、これに加え回路基板３をフレキシブル基板とした構成であってもよい。   In this manufacturing method, the basic structure above the second circuit board 11 has been described using the structure described in the second embodiment, but the basic structure is the structure described in the first embodiment. The circuit board 3 may be a flexible board.

（実施形態５）
図６（ｂ）を参照して、本発明の実施形態５に係る半導体装置を説明する。図６（ｂ）は、実施形態５の半導体装置の断面構成を模式的に示している。 (Embodiment 5)
With reference to FIG. 6B, a semiconductor device according to Embodiment 5 of the present invention will be described. FIG. 6B schematically shows a cross-sectional configuration of the semiconductor device of the fifth embodiment.

図６（ｂ）に示す半導体装置は、図６（ａ）に示した半導体素子１とフレキシブル基板からなる回路基板３との組品を、２段あるいはそれ以上に繰り返し積み重ねる構成にしている。このようにすれば、多機能な半導体装置とすることが可能となる。   The semiconductor device shown in FIG. 6B has a configuration in which the assembly of the semiconductor element 1 and the circuit board 3 made of a flexible substrate shown in FIG. 6A is repeatedly stacked in two or more stages. In this way, a multifunctional semiconductor device can be obtained.

なお、多段に積み重ねられる半導体素子１はその下側に位置するフレキシブル基板からなる回路基板３の他方面に例えば接着剤などで固定されていてもよい。このように半導体素子１と回路基板３とを固定した場合、振動に強い構造にできる。   In addition, the semiconductor elements 1 stacked in multiple stages may be fixed to the other surface of the circuit board 3 made of a flexible board positioned below the semiconductor element 1 with, for example, an adhesive. Thus, when the semiconductor element 1 and the circuit board 3 are fixed, it can be set as a structure strong against a vibration.

ここで、図６（ｂ）に示した半導体装置の製造方法を説明する。   Here, a method for manufacturing the semiconductor device shown in FIG. 6B will be described.

半導体素子１に凸状電極２を形成する方法、回路基板３に貫通孔電極８を形成する方法、ならびに凸状電極２と貫通孔電極８を接続する方法は実施形態２に記載した方法と同じとするので説明を省略する。   The method of forming the convex electrode 2 on the semiconductor element 1, the method of forming the through-hole electrode 8 on the circuit board 3, and the method of connecting the convex electrode 2 and the through-hole electrode 8 are the same as those described in the second embodiment. Therefore, the description is omitted.

フレキシブル基板からなる回路基板３を第２の回路基板１１に多段に積層していく方法としては、例えば、上記図６（ａ）に示す半導体装置の製造方法を繰り返す方法がある。もう一つの例としては、予め第２の回路基板１１あるいは各々の回路基板３（フレキシブル基板）の所定の位置にクリームはんだをディスペンス法あるいは印刷により塗布した後、各々の回路基板３（フレキシブル基板）を位置あわせして第２の回路基板１１に搭載する。その後、リフロー炉に投入することで加熱し、一括してはんだを溶融させて回路基板３（フレキシブル基板）と回路基板１１とを電気的に接続する。各々の回路基板３（フレキシブル基板）を回路基板１１に接続する他の例としては、予め第２の回路基板１１あるいは各々の回路基板３（フレキシブル基板）の所定の位置に導電性接着剤をディスペンス法あるいは印刷法により塗布した後、各々の回路基板３（フレキシブル基板）を位置あわせして第２の回路基板１１に搭載する。その後リフロー炉あるいはオーブンに投入し、加熱することで一括して導電性接着剤を硬化させ各々の回路基板３（フレキシブル基板）と第２の回路基板１１とを電気的に接続する方法がある。   As a method of stacking the circuit board 3 made of a flexible substrate on the second circuit board 11 in multiple stages, for example, there is a method of repeating the semiconductor device manufacturing method shown in FIG. As another example, after applying cream solder to a predetermined position of the second circuit board 11 or each circuit board 3 (flexible board) in advance by a dispensing method or printing, each circuit board 3 (flexible board). Are aligned and mounted on the second circuit board 11. Then, it heats by throwing into a reflow furnace, fuse | melts solder collectively, and electrically connects the circuit board 3 (flexible board | substrate) and the circuit board 11. FIG. As another example of connecting each circuit board 3 (flexible board) to the circuit board 11, a conductive adhesive is dispensed in advance at a predetermined position of the second circuit board 11 or each circuit board 3 (flexible board). After applying by the printing method or the printing method, each circuit board 3 (flexible board) is aligned and mounted on the second circuit board 11. After that, there is a method in which the conductive adhesive is cured in a lump by putting it in a reflow oven or oven and heating to electrically connect each circuit board 3 (flexible board) and the second circuit board 11.

なお、半導体素子１の他方面を第２の回路基板１１に固定する必要がある場合は、上記図６（ａ）に示す半導体装置の製造方法と同様な方法で固定する。各々の半導体素子１の他方面と各々の回路基板３（フレキシブル基板）とを接続する必要がある場合には、半導体素子１の他方面あるいは回路基板３（フレキシブル基板）の所定位置に接着剤を塗布しておき両者を接続・固定する。   In addition, when it is necessary to fix the other surface of the semiconductor element 1 to the 2nd circuit board 11, it fixes by the method similar to the manufacturing method of the semiconductor device shown to the said Fig.6 (a). When it is necessary to connect the other surface of each semiconductor element 1 and each circuit board 3 (flexible substrate), an adhesive is applied to the other surface of the semiconductor element 1 or a predetermined position on the circuit board 3 (flexible substrate). Apply and fix them together.

また、図６（ｂ）に示す半導体装置において、第２の回路基板１１より上の基本構造については実施形態２に述べた構造を用いて説明したが、基本構造は実施形態１に述べた構造であり、これに加え回路基板３をフレキシブル基板とした構成であってもよい。   In the semiconductor device shown in FIG. 6B, the basic structure above the second circuit board 11 has been described using the structure described in the second embodiment, but the basic structure is the structure described in the first embodiment. In addition to this, the circuit board 3 may be a flexible board.

なお、図６（ａ）（ｂ）で説明した構成において、回路基板３の貫通孔電極８を実施形態１で示した凹状電極４とすることができる。   6A and 6B, the through-hole electrode 8 of the circuit board 3 can be the concave electrode 4 shown in the first embodiment.

（実施形態６）
図６（ｃ）を参照して、本発明の実施形態６に係る半導体装置を説明する。図６（ｃ）は、実施形態６の半導体装置の断面構成を模式的に示している。 (Embodiment 6)
A semiconductor device according to Embodiment 6 of the present invention will be described with reference to FIG. FIG. 6C schematically shows a cross-sectional configuration of the semiconductor device of the sixth embodiment.

図６（ｃ）に示す半導体装置は、図４に示す実施形態３の構成を基本構成として、回路基板３をフレキシブル基板とし、半導体素子１の他方面を第２の回路基板１１の一方面に向き合わせて取り付け、この第２の回路基板１１にフレキシブル基板からなる回路基板３を電気的に接続した構成にしている。この場合、実施形態３で述べた効果を得ることができる。しかも、この形態において、半導体素子１とフレキシブル基板からなる回路基板３と第２の半導体素子１０との組品を、２段あるいはそれ以上に繰り返し積み重ねる構成にすることができる。このようにすれば、多機能な半導体装置とすることが可能となる。   The semiconductor device shown in FIG. 6C is based on the configuration of the third embodiment shown in FIG. 4, the circuit board 3 is a flexible board, and the other surface of the semiconductor element 1 is on one surface of the second circuit board 11. The circuit board 3 made of a flexible board is electrically connected to the second circuit board 11 so as to face each other. In this case, the effect described in the third embodiment can be obtained. Moreover, in this embodiment, the assembly of the semiconductor element 1, the circuit board 3 made of a flexible substrate, and the second semiconductor element 10 can be repeatedly stacked in two or more stages. In this way, a multifunctional semiconductor device can be obtained.

ここで、図６（ｃ）に示した半導体装置の製造方法を説明する。   Here, a manufacturing method of the semiconductor device shown in FIG.

半導体素子１に凸状電極２を形成する方法、回路基板３に貫通孔電極８を形成する方法、ならびに半導体素子１の凸状電極２と回路基板３の貫通孔電極８および第２の半導体素子１０とを接続する方法については、実施形態３に記載した方法と同じとするので説明を省略する。   Method of forming convex electrode 2 on semiconductor element 1, method of forming through-hole electrode 8 on circuit board 3, and convex electrode 2 of semiconductor element 1, through-hole electrode 8 of circuit board 3 and second semiconductor element Since the method for connecting 10 is the same as that described in the third embodiment, the description thereof is omitted.

フレキシブル基板からなる回路基板３と第２の回路基板１１とを接続する方法については、図６（ａ）に示す実施形態４の製造方法と同じとするので説明を省略する。但し、半導体素子１の他方面を第２の回路基板１１に固定する必要がある場合は、図６（ａ）に示す実施形態４の製造方法と同じ方法で固定する。なお、第２の回路基板１１の上の部分を繰り返し重ねていく多段積層構成にする方法としては、図６（ｂ）に示す実施形態５の製造方法と同じ方法とすることができる。   The method for connecting the circuit board 3 made of a flexible substrate and the second circuit board 11 is the same as the manufacturing method of the fourth embodiment shown in FIG. However, when it is necessary to fix the other surface of the semiconductor element 1 to the second circuit board 11, it is fixed by the same method as the manufacturing method of the fourth embodiment shown in FIG. In addition, as a method of making the multistage laminated structure which repeats the upper part of the 2nd circuit board 11, it can be set as the same method as the manufacturing method of Embodiment 5 shown in FIG.6 (b).

ところで、図６（ａ）〜（ｃ）に示した半導体装置では、半導体素子１，１０とフレキシブル基板からなる回路基板３との対向間に実施形態２、３でも述べた樹脂５を介在させていないが、この樹脂を介在させることで、半導体素子１，１０とフレキシブル基板からなる回路基板３との接合を強化し、信頼性を向上させることも可能である。   Incidentally, in the semiconductor device shown in FIGS. 6A to 6C, the resin 5 described in the second and third embodiments is interposed between the semiconductor elements 1 and 10 and the circuit board 3 made of a flexible substrate. However, by interposing this resin, it is possible to enhance the bonding between the semiconductor elements 1 and 10 and the circuit board 3 made of a flexible substrate and improve the reliability.

微細ピッチ接続技術を用いた小型の半導体装置およびその製造方法を提供することができる。   A small semiconductor device using a fine pitch connection technique and a method for manufacturing the same can be provided.

本発明の実施形態１に係る半導体装置の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施形態２に係る半導体装置の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施形態２の製造方法を説明する図である。It is a figure explaining the manufacturing method of Embodiment 2 of this invention. 本発明の実施形態３に係る半導体装置の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施形態３の製造方法を説明する図である。It is a figure explaining the manufacturing method of Embodiment 3 of this invention. 本発明の実施形態４，５，６に係る半導体装置の構成を模式的に示す断面図である。It is sectional drawing which shows typically the structure of the semiconductor device which concerns on Embodiment 4,5,6 of this invention. 従来の半導体装置の実装構成、製造方法、問題点を示した図である。It is the figure which showed the mounting structure, manufacturing method, and problem of the conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体素子
２ 凸状電極
３ 回路基板
４ 凹状電極
５ 樹脂
６ ビルドアップ層
７ コア層
８ 貫通孔電極
９ 配線パターン
１０ 第２の半導体素子
１１ 第２の回路基板
１２ 導電材料
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Convex electrode 3 Circuit board 4 Concave electrode 5 Resin 6 Buildup layer 7 Core layer 8 Through-hole electrode 9 Wiring pattern 10 2nd semiconductor element 11 2nd circuit board 12 Conductive material

Claims (12)

一方面に電極を有する半導体素子と、一方面に電極を有する回路基板とを備えかつ前記半導体素子の一方面を前記回路基板の一方面に向き合わせた状態で互いの電極を電気的に接続してなる半導体装置であって、
前記半導体素子の電極を凸状とし、前記回路基板の電極を内底面が前記回路基板の一方面の主表面より低い凹状とし、前記半導体素子の凸状電極を前記回路基板の凹状電極内に挿入して電気的に接続していることを特徴とする半導体装置。 A semiconductor element having an electrode on one side and a circuit board having an electrode on one side, and the electrodes are electrically connected with one side of the semiconductor element facing the one side of the circuit board A semiconductor device comprising:
The electrode of the semiconductor element has a convex shape, the electrode of the circuit board has a concave shape whose inner bottom surface is lower than the main surface of one surface of the circuit board, and the convex electrode of the semiconductor element is inserted into the concave electrode of the circuit board The semiconductor device is electrically connected to each other. 一方面に電極を有する半導体素子と、一方面に電極を有する回路基板とを備えかつ前記半導体素子の一方面を前記回路基板の一方面に向き合わせた状態で互いの電極を電気的に接続してなる半導体装置であって、
前記半導体素子の電極を凸状とし、前記回路基板の電極を貫通孔形状とし、前記半導体素子の凸状電極を前記回路基板の貫通孔電極内に挿入して電気的に接続していることを特徴とする半導体装置。 A semiconductor element having an electrode on one side and a circuit board having an electrode on one side, and the electrodes are electrically connected with one side of the semiconductor element facing the one side of the circuit board A semiconductor device comprising:
The electrode of the semiconductor element is convex, the electrode of the circuit board is a through-hole shape, and the convex electrode of the semiconductor element is inserted into the through-hole electrode of the circuit board and electrically connected. A featured semiconductor device. 前記半導体素子の凸状電極を、前記回路基板の他方面にまで突き出させていることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the convex electrode of the semiconductor element protrudes to the other surface of the circuit board. 前記回路基板の他方面に突き出した凸状電極を、さらに第２の半導体素子あるいは半導体装置に電気的に接続していることを特徴とする請求項３に記載の半導体装置。   4. The semiconductor device according to claim 3, wherein the convex electrode protruding on the other surface of the circuit board is further electrically connected to the second semiconductor element or the semiconductor device. 前記半導体素子と前記回路基板との対向間に、樹脂を介在していることを特徴とする請求項１〜４のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein a resin is interposed between the semiconductor element and the circuit board. 前記回路基板をフレキシブル基板としていることを特徴とする請求項１〜５のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the circuit board is a flexible substrate. 前記半導体素子の他方面に第２の回路基板の一方面を向き合わせた状態で取り付け、この第２の回路基板の一方面に有する電極を前記フレキシブル基板からなる回路基板を介して前記半導体素子の凸状電極に電気的に接続していることを特徴とする請求項６に記載の半導体装置。   The second surface of the semiconductor element is attached to the other surface of the semiconductor element so that the one surface of the second circuit board faces the other surface. The semiconductor device according to claim 6, wherein the semiconductor device is electrically connected to the convex electrode. 一方面に凸状電極を有する半導体素子と、一方面に内底面を前記回路基板の一方面の主表面より低くしてなる凹状電極を有する回路基板とを備えかつ前記半導体素子の一方面を前記回路基板の一方面に向き合わせた状態で互いの電極を電気的に接続してなる半導体装置を製造する方法であって、
前記半導体素子の凸状電極を前記回路基板の凹状電極に挿入して接合する工程を含むことを特徴とする半導体装置の製造方法。 A semiconductor element having a convex electrode on one side, and a circuit board having a concave electrode having an inner bottom surface lower than a main surface of one side of the circuit board on one side, and the one side of the semiconductor element is A method of manufacturing a semiconductor device in which electrodes of each other are electrically connected in a state of facing one side of a circuit board,
A method of manufacturing a semiconductor device, comprising a step of inserting and bonding a convex electrode of the semiconductor element into a concave electrode of the circuit board. 一方面に凸状電極を有する半導体素子と、一方面に内底面を前記回路基板の一方面の主表面より低くしてなる凹状電極を有する回路基板とを備えかつ前記半導体素子の一方面を前記回路基板の一方面に向き合わせた状態で互いの電極を電気的に接続してなる半導体装置を製造する方法であって、
前記半導体素子の電極を凸状に形成する工程と、前記回路基板の電極を凹状にかつ内底面を前記回路基板の一方面の主表面より低くする工程と、前記半導体素子の凸状電極を前記回路基板の凹状電極に挿入して接合する工程とを含むことを特徴とする半導体装置の製造方法。 A semiconductor element having a convex electrode on one side, and a circuit board having a concave electrode having an inner bottom surface lower than a main surface of one side of the circuit board on one side, and the one side of the semiconductor element is A method of manufacturing a semiconductor device in which electrodes of each other are electrically connected in a state of facing one side of a circuit board,
Forming the electrode of the semiconductor element into a convex shape, forming the electrode of the circuit board into a concave shape and lowering the inner bottom surface from the main surface of one surface of the circuit board, and forming the convex electrode of the semiconductor element into the A method of manufacturing a semiconductor device, comprising the step of inserting and joining the concave electrode of the circuit board. 前記回路基板をコア層とその表面に所定厚みのビルドアップ層を積層してなる構成とし、前記回路基板に凹状電極を形成する工程は、前記ビルドアップ層において凹状電極の形成予定部分を除去してコア層の表面を露出させ、この除去した部分の内面および前記除去部分から露出するコア層の表面を導体で被覆することにより当該導体を凹状電極とするものであることを特徴とする請求項９に記載の半導体装置の製造方法。   The circuit board is configured by laminating a core layer and a build-up layer having a predetermined thickness on the surface thereof, and the step of forming a concave electrode on the circuit board includes removing a portion where the concave electrode is to be formed in the build-up layer. The surface of the core layer is exposed, and the inner surface of the removed part and the surface of the core layer exposed from the removed part are covered with a conductor to form the conductor as a concave electrode. A method for manufacturing a semiconductor device according to claim 9. 一方面に凸状電極を有する半導体素子と、一方面に貫通孔電極を有する回路基板とを備えかつ前記半導体素子の一方面を前記回路基板の一方面に向き合わせた状態で互いの電極を電気的に接続してなる半導体装置を製造する方法であって、
前記半導体素子の凸状電極を前記回路基板の貫通孔電極に挿入して接合する工程を含むことを特徴とする半導体素子の製造方法。 A semiconductor element having a convex electrode on one side and a circuit board having a through-hole electrode on one side, and the electrodes are electrically connected with one side of the semiconductor element facing the one side of the circuit board. A method for manufacturing a semiconductor device connected to each other,
A method of manufacturing a semiconductor element, comprising a step of inserting and bonding the convex electrode of the semiconductor element into a through-hole electrode of the circuit board. 一方面に凸状電極を有する半導体素子と、一方面に貫通孔電極を有する回路基板とを備えかつ前記半導体素子の一方面を前記回路基板の一方面に向き合わせた状態で互いの電極を電気的に接続してなる半導体装置を接続する方法であって、
前記半導体素子の電極を凸状に形成する工程と、前記回路基板の電極を該回路基板を貫通した貫通孔形状に形成する工程と、前記半導体素子の凸状電極を前記回路基板の貫通孔電極に挿入して接合する工程とを含むことを特徴とする半導体装置の製造方法。 A semiconductor element having a convex electrode on one side and a circuit board having a through-hole electrode on one side, and the electrodes are electrically connected with one side of the semiconductor element facing the one side of the circuit board. A method of connecting a semiconductor device formed by connecting,
Forming the electrode of the semiconductor element into a convex shape; forming the electrode of the circuit board into a through-hole shape penetrating the circuit board; and forming the convex electrode of the semiconductor element into a through-hole electrode of the circuit board. A method of manufacturing a semiconductor device, comprising the step of:
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