JP2005341370A - Arithmetic coding computing element adopting mq-coder system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic coding computing element adopting the MQ-CODER system used for configuring an image coder or the like adopting the JPEG coding system that continuously carries out arithmetic operations of an augend A to attain high speed arithmetic coding computation. <P>SOLUTION: A first arithmetic means 47 receives a context CX and a symbol D to calculate the augend A, outputs data Qe, BS, Sel, a storage means 48 stores the data Qe, BS, Sel outputted from the first arithmetic means 47, and a second arithmetic means 49 receives the data Qe, BS, Sel stored in the storage means 48 to calculate a code C and byte data B. The first arithmetic means 47 includes two A arithmetic sections 51, 52 and applies parallel processing to a set of contexts CX(2m) and symbols D(2m) and a set of contexts CX(2m+1) and symbols D(2m+1). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an MQ-CODER arithmetic coding arithmetic unit used when configuring a JPEG2000 encoding image encoding device or the like. More specifically, the present invention relates to a technology for speeding up an MQ-CODER arithmetic coding arithmetic unit.

  The MQ-CODER method is used as an arithmetic coding method of JPEG2000. The standards of JPEG2000 are “ISO / IEC15444-1,“ JPEG2000 image coding system Part1: Core coding system, ”15 Dec.2000” and “Yasuyuki Nomizu,“ Next-generation image coding method: JPEG2000, ”Trikes, Feb.2001. Is described in detail.

  FIG. 39 is a circuit diagram showing a main part of an example of a conventional MQ-CODER arithmetic coding arithmetic unit. In FIG. 39, CX is a context, D is a symbol, A is an Augend, C is a code, B is byte data, 1 is an arithmetic unit of MQ-CODER system for calculating A, C and B, and 2 is an arithmetic unit This is a register for renewably storing new A and C calculated in 1.

The conventional MQ-CODER arithmetic coding arithmetic unit shown in FIG. 39 inputs CX and D to the arithmetic unit 1 for each pair, calculates new A and C, and updates the new A and C to the register 2. However, when byte out occurs, the operation of B is performed. Here, the operation of A can be performed once per CX, but the operation of B requires one clock cycle or more. Therefore, when byte out occurs, it is necessary to stop the operation of A until the operation of B is completed.
JP 2003-258648 A

  In the conventional MQ-CODER arithmetic coding arithmetic unit shown in FIG. 39, if byte out occurs, it is necessary to stop the operation of A until the operation of B is completed, so the operation of A is continuously performed. I can't. In addition, A changes every time it is calculated by the calculation unit 1, and the calculation unit 1 uses the changed A for the next calculation of A. Calculations cannot be performed, and even at the fastest speed, only one set of CX and D can be processed in one calculation. These points have hindered speeding up of arithmetic coding operations.

  Patent Document 1 describes a method for avoiding a loop for a shift operation that occurs in an A operation and obtaining A by a single operation. However, in the technique described in Patent Document 1, since the calculation of C is not independent of the calculation of A, the calculation of A is waited to output the calculation result of C. This point is the arithmetic code. This hinders the speeding up of the calculation operation.

  In view of the above, the present invention is an MQ-CODER arithmetic coding arithmetic unit that continuously performs the operation of A, and can speed up the MQ-CODER arithmetic coding operation, An object of the present invention is to provide an MQ-CODER-type arithmetic coding arithmetic unit capable of processing a plurality of sets of CX and D in parallel and further increasing the speed.

  The MQ-CODER arithmetic coding arithmetic unit of the present invention inputs CX and D, calculates A, and outputs an audend arithmetic unit that outputs predetermined data, and stores predetermined data output by the A arithmetic unit. A storage unit and a C calculation unit for calculating C and B by inputting predetermined data stored in the storage unit are provided.

  According to the present invention, the A calculation unit and the C calculation unit are configured independently via the storage unit that stores the predetermined data output from the A calculation unit. Even if the calculation result of C is output, A can be calculated. Therefore, the operation of A can be performed continuously, and the speed of the arithmetic coding operation of the MQ-CODER system can be increased. When the A arithmetic units are connected in multiple stages using A as an input / output value, a plurality of sets of CX and D can be processed in parallel, and further speedup can be achieved.

  1 to 38, the first embodiment to the fourth embodiment of the present invention are based on the MQ-CODER system used when the present invention is configured as a JPEG2000 encoding image encoding apparatus. A case where the present invention is applied to an arithmetic coding arithmetic unit will be described as an example.

(First embodiment)
FIG. 1 is a circuit diagram showing the main part of the first embodiment of the present invention. In FIG. 1, 4 is a first calculation means, 5 is a storage means, and 6 is a second calculation means. The first calculation means 4 inputs CX and D and calculates A, and Qe = recessive symbol probability which is data necessary for the calculation of C, BS = bit shift of A in the renormalization processing circuit at the time of encoding Data indicating whether the quantity, Sel = Qe, is valid or not is output. The storage means 5 stores Qe, BS and Sel output from the first calculation means 4. The second calculation means 6 inputs Qe, BS and Sel stored in the storage means 5 and calculates C and B.

  In the first computing means 4, 7 is an A register and 8 is an A computing unit. The A register 7 stores A (m) in an update manner. However, m is a number indicating the number of a pair of CX and D. The A operation unit 8 inputs CX (m) and D (m) given from the preceding apparatus (not shown) and A (m) stored in the A register 7, and A (m + 1) is inputted by the MQ-CODER method. It is to calculate. A (m + 1) calculated by the A calculating unit 8 is stored in the A register 7 in place of A (m).

  In the storage means 5, reference numerals 9-0, 9-1 and 9-2 indicate three of the registers provided in the storage means 5, and the storage means including the registers 9-0, 9-1 and 9-2. The register 5 has a capacity for storing Qe (m), BS (m), and Sel (m). In the second computing means 6, 10 is a C register and 11 is a C computing unit. The C register 10 stores C in an update manner. The C calculation unit 11 inputs Qe, BS, and Sel stored in the register 9-0 of the storage unit 5 and C stored in the C register 10, and calculates C and B by the MQ-CODER method. C calculated by the C calculation unit 11 is stored in the C register 10 in an update manner.

  FIG. 2 is a circuit diagram of the A operation unit 8. In FIG. 2, 13 is an index memory which inputs CX (m) and outputs index = I (CX (m)) in CX (m). Reference numeral 14 denotes a Qe table circuit which inputs I (CX (m)) output from the index memory 13 and outputs Qe (m) = Qe (I (CX (m))).

  A subtractor 15 subtracts Qe (m) output from the Qe table circuit 14 from A (m) stored in the A register 7. A comparator 16 compares Qe (m) output from the Qe table circuit 14 by 1 bit to the left (Qe (m) << 1) and A (m) stored in the A register 7. In the case of A (m) << (Qe (m) << 1), "1" is output, and in other cases, "0" is output.

  Reference numeral 17 denotes an MPS memory which inputs CX (m) and outputs a dominant symbol = MPS (CX (m)) in CX (m). ExOR circuit 18 performs ExOR processing on MPS (CX (m)) and D (m) output from MPS memory 17, and IsLPS (m) (= encoding is MPS encoding or LPS encoding). Is output).

  An ExOR circuit 19 performs ExOR processing on the output of the comparator 16 and the IsLPS (m) output by the ExOR circuit 18 and outputs Sel (m). Reference numeral 20 denotes a selector, which selects Sel (m) output from the ExOR circuit 19 as selection control data. When Sel (m) = “1”, Qe (m) output from the Qe table circuit 14 is selected. When Sel (m) = “0”, the subtracter 15 selects (A (m) −Qe (m)).

  Reference numeral 21 denotes a RENORME (encoding renormalization) circuit which receives the output of the selector 20 and performs encoding renormalization processing to output A (m + 1) and BS (m). An AND circuit 22 AND-processes SWITCH (I (CX (m))) (= symbol reverse switch) and IsLPS (m) output from the ExOR circuit 18. Reference numeral 23 denotes an ExOR circuit which performs an EXOR process on the MPS (CX (m)) output from the MPS memory 17 and the output of the AND circuit 22 to obtain an NxtMPS (CX (m)) (= dominant symbol necessary for the subsequent bit processing). Is output.

  Reference numeral 24 denotes a next index circuit. I (CX (m)) output from the index memory 13, (A (m) −Qe (m)) output from the subtractor 15, and IsLPS ( m) is input and NxtI (CX (m)) (= index necessary for bit processing in the subsequent stage) is output.

  FIG. 3 is a circuit diagram of a first configuration example of the index memory 13. In FIG. 3, 26-i (where i = 0, 1, 2,..., 18) is a selector, 27-i is an index register, 28 is a selector, and whether or not CX (m) = i. Is selected control data, NxtI (CX (m)) is selected when CX (m) = i, and the output of the index register 27-i when CX (m) ≠ i. Is to select. The index register 27-i stores the output of the selector 26-i. The selector 28 uses CX (m) as the selection control data, and when CX (m) = i, the selector 28 selects the output of the index register 27-i, and the output of the selector 28 is I (CX (m )).

  FIG. 4 is a circuit diagram of a second configuration example of the index memory 13. In the second configuration example of the index memory 13, a circuit 30 for outputting a fixed value "46" is provided instead of the selector 26-18 and the index register 27-18 shown in FIG. The index memory 13 is configured in the same manner as the first configuration example. Similar replacement is possible with the index register 87-18 of FIG. 16 and the index register 162-18 of FIG.

  FIG. 5 is a circuit diagram of a first configuration example of the MPS memory 17. In FIG. 5, 32-i is a selector, 33-i is an MPS register, 34 is a selector, and data indicating whether CX (m) = i is selection control data, and CX (m) = i In this case, NxtMPS (CX (m)) is selected, and when CX (m) ≠ i, the output of the MPS register 33-i is selected. The MPS register 33-i stores the output of the selector 32-i. The selector 34 uses CX (m) as selection control data, and when CX (m) = i, selects the output of the MPS register 33-i.

  FIG. 6 is a circuit diagram of a second configuration example of the MPS memory 17. In the second configuration example of the MPS memory 17, a register 36 for outputting a fixed value “0” is provided instead of the selector 32-18 and the MPS register 33-18 shown in FIG. This is configured similarly to the first configuration example of the memory 16. Similar replacement is also possible in the MPS memory in the second embodiment, the third embodiment, and the fourth embodiment.

  FIG. 7 is a circuit diagram of the next index circuit 24. In FIG. 7, reference numeral 38 denotes a selector. A (m) [15] (the 16th bit of A (m)) is selected control data, and when A (m) [15] = “0”, NMPS ( I (CX (m))) = Update index after MPS encoding is selected, and when A (m) [15] = “1”, I (CX (m)) is selected. Reference numeral 39 denotes a selector, which uses IsLPS (m) as selection control data. When IsLPS (m) = “0”, the output of the selector 38 is selected, and when IsLPS (m) = “1”, NLPS ( I (CX (m))) (= update index after LPS encoding).

  FIG. 8 is a circuit diagram of the C calculation unit 11. In FIG. 8, 41 is a selector, and data SelReg0 (= Sel stored in the register 9-0) indicating whether or not QeReg0 (= Qe stored in the register 9-0) is valid is selected control data. When SelReg0 = "0", QeReg0 is selected, and when SelReg0 = "1", 0 is selected.

  An adder 42 adds the C stored in the C register 10 and the output of the selector 41. A shifter 43 shifts the output of the adder 42 to the left by S0 = Min (CT, BSReg0). However, CT is the value of the byte counter, and BSReg0 is the BS stored in the register 9-0. A byte-out circuit 44 inputs the output Cin of the shifter 43 and calculates B. Reference numeral 45 denotes a selector, and data indicating whether or not BSReg0> = CT is used as selection control data. When BSReg0> = CT, C output from the byte-out circuit 44 is selected, and otherwise. Selects the output of the shifter 43.

  9 to 13 are circuit diagrams showing an operation example of the first embodiment of the present invention. Qe, BS, and Sel writing and reading control with respect to the storage means 5 is performed by a predetermined control circuit (not shown), but Qe, BS, and Sel writing and reading control with respect to the storage means 5 shown in FIGS. Is an example, and other methods can be used.

  FIG. 9 shows a case where CX (0) and D (0) are given to the A arithmetic unit 8 from the preceding apparatus at time t = T0. In this case, the A operation unit 8 inputs A (0) stored in the A register 7 to calculate A (1), and outputs Qe (0), BS (0), and Sel (0). A (1) is updated and stored in the A register 7, and Qe (0), BS (0), and Sel (0) are stored in the register 9-0.

  FIG. 10 shows a case where CX (1) and D (1) are given from the preceding apparatus to the A calculation unit 8 at time t = T1. In this case, the C calculation unit 11 inputs Qe (0), BS (0), Sel (0) stored in the register 9-0 and C (0) stored in the C register 10 and inputs C (1). Calculate. C (1) is stored in the C register 10 in an update manner. On the other hand, the A operation unit 8 inputs A (1) stored in the A register 7 to calculate A (2), and outputs Qe (1), BS (1), and Sel (1). A (2) is updated and stored in the A register 7, and Qe (1), BS (1), and Sel (1) are stored in the register 9-0.

  FIG. 11 shows a case where CX (2) and D (2) are given to the A arithmetic unit 8 from the preceding apparatus at time t = T2. In this case, the C calculation unit 11 inputs Qe (1), BS (1), Sel (1) stored in the register 9-0 and C (1) stored in the C register 10, but at this point Assuming that an out occurs, the C calculating unit 11 calculates B (0), and BS ′ (1) (= BS (1) −BS (0)) obtained by post-processing BS (1) is the register 9-0. Is remembered. C ′ (1) is updated and stored in the C register 10. On the other hand, the A operation unit 8 inputs A (2) output from the A register 7 and calculates A (3), and outputs Qe (2), BS (2), and Sel (2). A (2) is updated and stored in the A register 7, and Qe (2), BS (2), and Sel (2) are stored in the register 9-1.

  FIG. 12 shows a case where CX (3) and D (3) are given from the preceding apparatus to the A operation unit 8 at time t = T3. In this case, the C calculation unit 11 inputs BS ′ (1) stored in the register 9-0 and C ′ (1) stored in the C register 10 and calculates C (2). C (2) is stored in the C register 10 in an update manner. On the other hand, the A calculation unit 8 inputs A (3) output from the A register 7, calculates A (4), and outputs Qe (3), BS (3), and Sel (3). A (4) is updated and stored in the A register 7, and Qe (3), BS (3), and Sel (3) are stored in the register 9-1. Further, Qe (2), BS (2), and Sel (2) stored in the register 9-1 are stored in the register 9-0.

  FIG. 13 shows a case where CX (4) and D (4) are given to the A arithmetic unit 8 from the preceding apparatus at time t = T4. In this case, the C calculation unit 11 inputs Qe (2), BS (2), Sel (2) stored in the register 9-0 and C (2) stored in the C register 10 and inputs C (3). Calculate. C (3) is stored in the C register 10 in an update manner. On the other hand, the A operation unit 8 inputs A (4) output from the A register 7, calculates A (5), and outputs Qe (4), BS (4), and Sel (4). A (5) is stored in the A register 7 in an update manner. Thereafter, the same operation is continued.

  As described above, according to the first embodiment of the present invention, the first calculation means 4 for calculating A and the second calculation means 6 for calculating C and B are output by Qe, Since it is configured independently via the storage means 5 for storing BS and Sel, it is possible to perform the A operation even when byteout occurs or when the C operation result is output. it can. Therefore, the operation of A can be performed continuously, and the speed of the arithmetic coding operation of the MQ-CODER system can be increased.

(Second Embodiment)
FIG. 14 is a circuit diagram showing the main part of the second embodiment of the present invention. In FIG. 14, 47 is a first calculation means, 48 is a storage means, and 49 is a second calculation means. The first calculating means 47 inputs CX and D and calculates A. The storage means 48 stores Qe, BS and Sel necessary for the calculation of C output from the first calculation means 47. The second calculation means 49 inputs Qe, BS and Sel necessary for the calculation of C stored in the storage means 48 and calculates C and B. In the present embodiment, a set of CX (2m) and D (2m) and a set of CX (2m + 1) and D (2m + 1) are given in parallel from a preceding apparatus (not shown).

  In the first calculation means 47, 50 is an A register, and 51 and 52 are A calculation units. The A register 50 stores A (2 m). The A calculation unit 51 inputs CX (2m), D (2m) and A (2m) stored in the A register 50, and calculates A (2m + 1) by the MQ-CODER method. The A calculation unit 52 inputs CX (2m + 1), D (2m + 1) and A (2m + 1) output from the A calculation unit 51, and calculates A (2m + 2) by the MQ-CODER method. A (2m + 2) calculated by the A calculation unit 52 is stored in the A register 50 in place of A (2m).

  In the storage means 48, 53-0 to 53-4 indicate five of the registers provided in the storage means 48. The registers provided in the storage means 48 including the registers 53-0 to 53-4 are Qe ( j), BS (j), and Sel (j). However, j = 2m and 2m + 1.

  In the second calculation means 49, 54 is a C register, and 55 and 56 are C calculation units. The C register 54 stores C. The C calculation unit 55 inputs Qe, BS, and Sel stored in the register 53-0 of the storage unit 48 and C stored in the C register 54, and calculates C and B by the MQ-CODER method. The C calculation unit 56 inputs Qe, BS, Sel stored in the register 53-1 of the storage means 48 and C output from the C calculation unit 55, and calculates C and B by the MQ-CODER method. C calculated by the C calculation unit 56 is stored in the C register 54 in an update manner.

  FIG. 15 is a circuit diagram of the A calculation units 51 and 52. In FIG. 15, in the A calculation unit 51, 58 is an index memory, which inputs CX (2m) and outputs I (CX (2m)). 59 denotes a Qe table circuit which inputs I (CX (2m)) output from the index memory circuit 58 and outputs Qe (2m) = Qe (I (CX (2m))).

  A subtractor 60 subtracts Qe (2m) output from the Qe table circuit 59 from A (2m) stored in the A register 50. 61 is a comparator, which compares Qe (2m) output from the Qe table circuit 59 by 1 bit to the left (Qe (2m) << 1) and A (2m) stored in the A register 50; If A (2m) << (Qe (2m) << 1), "1" is output, otherwise "0" is output.

  Reference numeral 62 denotes an MPS memory which inputs CX (2m) and outputs MPS (CX (2m)). Reference numeral 63 denotes an ExOR circuit, which performs ExOR processing on MPS (CX (2m)) and D (2m) output from the MPS memory 62 and outputs IsLPS (2m).

  Reference numeral 64 denotes an ExOR circuit, which performs ExOR processing on the output of the comparator 61 and IsLPS (2m) output from the ExOR circuit 63 and outputs Sel (2m). 65 is a selector, and Sel (2m) output from the ExOR circuit 64 is used as selection control data. When Sel (2m) = “1”, Qe (2m) output from the Qe table circuit 59 is selected. When Sel (2m) = “0”, the subtracter 60 outputs (A (2m) −Qe (2m)) is selected.

  Reference numeral 66 denotes a RENORME circuit which receives the output of the selector 65, performs encoding renormalization processing, and outputs A (2m + 1) and BS (2m). An AND circuit 67 AND-processes SWITCH (I (CX (2m))) and IsLPS (2m) output from the ExOR circuit 63. Reference numeral 68 denotes an ExOR circuit which performs an EXOR process on the MPS (CX (2m)) output from the MPS memory 62 and the output of the AND circuit 67 and outputs NxtMPS (CX (2m)).

  Reference numeral 69 denotes a next index circuit. I (CX (2m)) output from the index memory 58, output from the subtractor 60 (A (2m) −Qe (2m)), and IsLPS (exit circuit 63 outputs) 2m) is input and NxtI (CX (2m)) is output.

  In the A operation unit 52, reference numeral 70 denotes an index memory which inputs CX (2m + 1) and outputs PreI (CX (2m + 1)) (pre-index). Reference numeral 71 denotes a selector. Data indicating whether CX (2m) = CX (2m + 1) is selected as control data. When CX (2m) = CX (2m + 1), the next index circuit 69 outputs the data. NxtI (CX (2m)) to be selected is selected. Otherwise, PreI (CX (2m + 1)) output from the index memory 70 is selected. The output of the selector 71 is I (CX (2m + 1)).

  A Qe table circuit 72 receives I (CX (2m + 1)) output from the selector 71 and outputs Qe (2m + 1) = Qe (I (CX (2m + 1)). 73 is a subtractor. Yes, Qe (2m + 1) output from the Qe table circuit 72 is subtracted from A (2m + 1) output from the RENORME circuit 66.

  74 is a comparator that compares Qe (2m + 1) output from the Qe table circuit 72 by 1 bit to the left (Qe (2m + 1) << 1) and A (2m + 1) output from the RENORME circuit 66. , A (2m + 1) << (Qe (2m + 1) << 1), "1" is output, otherwise "0" is output. Reference numeral 75 denotes an MPS memory which inputs CX (2m + 1) and outputs PreMPS (CX (2m + 1)).

  Reference numeral 76 denotes a selector. The data indicating whether CX (2m) = CX (2m + 1) is used as selection control data. When CX (2m) = CX (2m + 1), NxtMPS output from the ExOR circuit 68 is output. When (CX (2m)) is selected and CX (2m) ≠ CX (2m + 1), PreMPS (CX (2m + 1)) (predominant symbol) output from the MPS memory 75 is selected. The output of the selector 76 is MPS (CX (2m + 1)).

  Reference numeral 77 denotes an ExOR circuit, which performs ExOR processing on MPS (CX (2m + 1)) and D (2m + 1) output from the selector 76 and outputs IsLPS (2m + 1). Reference numeral 78 denotes an ExOR circuit, which performs ExOR processing on the output of the comparator 74 and IsLSP (2m + 1) output from the ExOR circuit 77 and outputs Sel (2m + 1).

  Reference numeral 79 denotes a selector, and Sel (2m + 1) output from the ExOR circuit 78 is used as selection control data. When Sel (2m + 1) = “1”, Qe (2m + 1) output from the Qe table circuit 72 is selected. When (2m + 1) = “0”, the subtracter 73 selects (A (2m + 1) −Qe (2m + 1)) output. Reference numeral 80 denotes a RENORME circuit which inputs Qe (2m + 1) or (A (2m + 1) −Qe (2m + 1)) output from the selector 79 and performs encoding renormalization processing to obtain A (2m + 2) and BS (2m + 1). Is output.

  An AND circuit 81 AND-processes SWITCH (I (CX (2m + 1))) and IsLPS (2m + 1) output from the ExOR circuit 77. Reference numeral 82 denotes an ExOR circuit which performs ExOR processing on the PreMPS (CX (2m + 1)) output from the MPS memory 75 and the output of the AND circuit 81 and outputs NxtMPS (CX (2m + 1)). 83 is a next index circuit, which is output from the selector 71 (CX (2m + 1)), output from the subtractor 73 (A (2m + 1) −Qe (2m + 1)), and IsLPS (2m + 1) output from the ExOR circuit 77. And NxtI (CX (2m + 1)) is output.

  FIG. 16 is a circuit diagram of a configuration example of the index memories 58 and 70. In the second embodiment of the present invention, the index memories 58 and 70 are integrally formed. In FIG. 16, 85-i and 86-i are selectors, 87-i are index registers, and 88 and 89 are selectors. The selector 85-i uses the data indicating whether or not CX (2m) = i as selection control data. If CX (2m) = i, the selector 85-i selects NxtI (CX (2m)) and CX (2m) = i. 2m) When not i, the output of the index register 87-i is selected.

  The selector 86-i uses the data indicating whether or not CX (2m + 1) = i as selection control data. When CX (2m + 1) = i, the selector 86-i selects NxtI (CX (2m + 1)) and CX (2m + 1) = i. If 2m + 1) ≠ i, the output of the selector 85-i is selected. The index register 87-i stores the output of the selector 86-i. The selector 88 uses CX (2m) as selection control data, and selects the output of the index register 87-i when CX (2m) = i. The selector 89 uses CX (2m + 1) as selection control data, and selects the output of the index register 87-i when CX (2m + 1) = i.

  The MPS memories 62 and 75 are configured in the same manner as the index memories 58 and 70, and instead of NxtI (CX (2m)) and NxtI (CX (2m + 1) shown in FIG. 16, NxtMPS (CX (2m)), NxtMPS ( In this way, MPS (CX (2m + 1)) and PreMPS (CX (2m + 1)) are output instead of I (CX (2m + 1)) and PreI (CX (2m + 1)). Will be.

  FIG. 17 is a circuit diagram of the next index circuits 69 and 83. In FIG. 17, in the next index circuit 69, 90 is a selector, and A (2m) [15] is selected control data, and when A (2m) [15] = “0”, NMPS (I ( CX (2m))) is selected, and when A (2m) [15] = “1”, I (CX (2m)) is selected. Reference numeral 91 denotes a selector, which uses IsLPS (2m) as selection control data. When IsLPS (2m) = “0”, the output of the selector 90 is selected. When IsLPS (2m) = “1”, NLPS (I (CX (2m))) is selected. The output of the selector 91 is NxtI (CX (2m)).

  In the next index circuit 83, reference numeral 92 denotes a selector, and A (2m + 1) [15] is selected as control data. When A (2m + 1) [15] = “0”, NMPS (CX (2m + 1)) When A (2m + 1) [15] = “1”, I (CX (2m + 1)) is selected. Reference numeral 93 denotes a selector, which uses IsLPS (2m + 1) as selection control data. When IsLPS (2m + 1) = “0”, the output of the selector 92 is selected. When IsLPS (2m + 1) = “1”, NLPS ( I (CX (2m + 1))) is selected. The output of the selector 93 is NxtI (CX (2m + 1)).

  FIG. 18 is a circuit diagram of the C calculators 55 and 56. In the C operation unit 55, 94 is a selector, and data SelReg0 (= Sel stored in the register 53-0) indicating whether or not QeReg0 (= Qe stored in the register 53-0) is valid is selected control data. When SelReg0 = “0”, QeReg0 is selected, and when SelReg0 = “1”, 0 is selected. Reference numeral 95 denotes an adder for adding C stored in the C register 10 and the output of the selector 94. A shifter 96 shifts the output of the adder 95 to the left by S0 = Min (CT, BSReg0 + BSReg1). BSReg0 is a BS stored in the register 53-0, and BSReg1 is a BS stored in the register 53-1.

  Reference numeral 97 denotes a selector, and data SelReg1 (= Sel stored in the register 53-1) indicating whether or not QeReg1 (= Qe stored in the register 53-1) is valid is selected control data, and SelReg1 = "0" In the case of "", QeReg1 is selected, and in the case of SelReg1 = "1", 0 is selected. A shifter 98 shifts the output of the selector 97 to the left by S0 = Min (CT-BSReg0, BSReg1). An adder 99 adds the output of the shifter 96 and the output of the shifter 98.

  Reference numeral 100 denotes a selector. The selection control data is data indicating whether or not CT <= BSReg0. When CT <= BSReg0, the output of the shifter 96 is selected. When CT> BSReg0, addition is performed. The output of the device 99 is selected. Reference numeral 101 denotes a byte-out circuit which inputs the output of the selector 100 and calculates B. Reference numeral 102 denotes a selector that uses data indicating whether or not BSReg0 + BSReg1> = CT as selection control data. When BSReg0 + BSReg1> = CT, C is output from the byte-out circuit 101, and when BSReg0 + BSReg0 <CT. Is to select the output of the adder 99.

  19 to 24 are circuit diagrams showing an operation example of the second embodiment of the present invention. The Qe, BS, and Sel write / read control for the storage unit 48 is performed by a predetermined control circuit (not shown), but the Qe, BS, and Sel write / read for the storage unit 48 shown in FIGS. The control is an example, and other methods can be used.

  FIG. 19 shows a case where CX (0) and D (0) are given from the preceding apparatus to the A computing unit 51 and CX (1) and D (1) are given to the A computing unit 52 at time t = T0. Show. In this case, the A operation unit 51 inputs A (0) output from the A register 50, calculates A (1), and outputs Qe (0), BS (0), and Sel (0). A (1) is given to the A operation unit 52, and Qe (0), BS (0), and Sel (0) are stored in the register 53-0. The A calculation unit 52 inputs A (1) output from the A calculation unit 51, calculates A (2), and outputs Qe (1), BS (1), and Sel (1). A (2) is updated and stored in the A register 50, and Qe (1), BS (1), and Sel (1) are stored in the register 53-1.

  FIG. 20 shows a case where CX (2) and D (2) are given to the A computing unit 51 from the preceding apparatus at time t = T1, and CX (3) and D (3) are given to the A computing unit 52. Show. In this case, the C calculation unit 55 inputs Qe (0), BS (0), Sel (0) stored in the register 53-0 and C (0) stored in the C register 54 and inputs C (1). Calculate. The C calculation unit 56 inputs Qe (1), BS (1), Sel (1) stored in the register 53-1, and C (1) calculated by the C calculation unit 55, and calculates C (2). . C (2) is stored in the C register 54 in an update manner.

  On the other hand, the A calculation unit 51 inputs A (2) output from the A register 50 to calculate A (3), and outputs Qe (2), BS (2), and Sel (2). A (3) is given to the A operation unit 52, and Qe (2), BS (2), and Sel (2) are stored in the register 53-0. The A calculation unit 52 inputs A (3) output from the A calculation unit 51, calculates A (4), and outputs Qe (3), BS (3), and Sel (3). A (4) is updated and stored in the A register 50, and Qe (3), BS (3), and Sel (3) are stored in the register 53-1.

  FIG. 21 shows a case where CX (4) and D (4) are given from the preceding apparatus to the A computing unit 51 and CX (5) and D (5) are given to the A computing unit 52 at time t = T2. Show. In this case, the C calculation unit 55 inputs Qe (2), BS (2), Sel (2) stored in the register 53-0 and C (2) stored in the C register 54 and inputs C (3). Calculate. The C calculation unit 56 inputs Qe (3), BS (3), Sel (3) stored in the register 53-1, and C (3) calculated by the C calculation unit 55. If it occurs, the C calculation unit 56 calculates B (0). The post-processed BS ′ (3) is stored in the register 53-0.

  On the other hand, the A operation unit 51 inputs A (4) output from the A register 50, calculates A (5), and outputs Qe (4), BS (4), and Sel (4). A (5) is given to the A operation unit 52, and Qe (4), BS (4), and Sel (4) are stored in the register 53-1. The A calculation unit 52 inputs A (5) output from the A calculation unit 51, calculates A (6), and outputs Qe (5), BS (5), and Sel (5). A (6) is updated and stored in the A register 50, and Qe (5), BS (5), and Sel (5) are stored in the register 53-2.

  FIG. 22 shows a case where CX (6) and D (6) are given from the preceding apparatus to the A computing unit 51 and CX (7) and D (7) are given to the A computing unit 52 at time t = T3. Show. In this case, the C calculation unit 55 inputs BS ′ (3) stored in the register 53-0 and C ′ (3) stored in the C register 54, and calculates C (4). The C calculation unit 56 inputs Qe (4), BS (4), Sel (4) stored in the register 53-1 and C (4) calculated by the C calculation unit 55 and calculates C (5). . C (5) is stored in the C register 54 in an update manner.

  On the other hand, the A calculation unit 51 inputs A (6) output from the A register 50 to calculate A (7), and outputs Qe (6), BS (6), and Sel (6). A (7) is given to the A operation unit 52, and Qe (6), BS (6), and Sel (6) are stored in the register 53-1. The A calculation unit 52 inputs A (7) output from the A calculation unit 51, calculates A (8), and outputs Qe (7), BS (7), and Sel (7). A (8) is updated and stored in the A register 50, and Qe (7), BS (7), and Sel (7) are stored in the register 53-2. Qe (5), BS (5), and Sel (5) stored in the register 53-2 are stored in the register 53-0.

  FIG. 23 shows a case where CX (8) and D (8) are given from the preceding apparatus to the A computing unit 51 and CX (9) and D (9) are given to the A computing unit 52 at time t = T4. Show. In this case, the C calculation unit 55 inputs Qe (5), BS (5), Sel (5) stored in the register 53-0 and C (5) stored in the C register 54. If out occurs, the C calculation unit 55 calculates B (1). The post-processed BS ′ (5) is stored in the register 53-0. C ′ (5) output from the C calculation unit 55 is stored in the C register 54.

  On the other hand, the A calculation unit 51 inputs A (8) output from the A register 50 and calculates A (9), and outputs Qe (8), BS (8), and Sel (8). A (9) is given to the A operation unit 52, and Qe (8), BS (8), and Sel (8) are stored in the register 53-3. The A calculation unit 52 inputs A (9) output from the A calculation unit 51, calculates A (10), and outputs Qe (9), BS (9), and Sel (9). A (10) is updated and stored in the A register 50, and Qe (9), BS (9), and Sel (9) are stored in the register 53-4.

  FIG. 24 shows a case where CX (10) and D (10) are given from the preceding apparatus to the A computing unit 51 and CX (11) and D (11) are given to the A computing unit 52 at time t = T5. Show. In this case, the C calculation unit 55 inputs BS ′ (5) stored in the register 53-0 and C ′ (5) stored in the C register 54 and calculates C (6). The C calculation unit 56 inputs Qe (6), BS (6), Sel (6) stored in the register 53-1, and C (6) calculated by the C calculation unit 56, and calculates C (7). . C (7) is stored in the C register 54. Thereafter, the same operation is continued.

  As described above, according to the second embodiment of the present invention, the first calculation means 47 for calculating A and the second calculation means 49 for calculating C and B are output by Qe, Since it is configured independently via the storage means 48 for storing BS and Sel, the calculation of A is performed even when byte out occurs or when the calculation result of C is output. Can do. Therefore, the operation of A can be performed continuously, and the speed of the arithmetic coding operation of the MQ-CODER system can be increased. In addition, two A calculation units 51 and 52 are provided, and a set of CX (2m) and D (2m) and a set of CX (2m + 1) and D (2m + 1) can be input in parallel, and these can be processed in parallel. Therefore, the speed can be increased as compared with the case of the first embodiment of the present invention.

(Third embodiment)
FIG. 25 is a circuit diagram showing the main part of the third embodiment of the present invention. In FIG. 25, reference numeral 104 denotes first calculation means, 105 denotes storage means, and 106 denotes second calculation means. The first calculating means 104 inputs CX and D and calculates A. The storage unit 105 stores Qe, BS, and Sel necessary for the calculation of C output from the first calculation unit 104. The second calculating means 106 inputs Qe, BS and Sel necessary for calculating C stored in the storage means 105 and calculates C and B. In the present embodiment, a group of CX (3m) and D (3m) and a group of CX (3m + 1) and D (3m + 1) and a group of CX (3m + 2) and D (3m + 2) are arranged in parallel from the preceding apparatus (not shown). Given.

  In the first calculation means 104, 107 is an A register, and 108, 109, and 110 are A calculation units. The A register 107 stores A (3 m). The A calculation unit 108 inputs CX (3m), D (3m) and A (3m) stored in the A register 107, and calculates A (3m + 1) by the MQ-CODER method.

  The A calculation unit 109 inputs CX (3m + 1), D (3m + 1) and A (3m + 1) output from the A calculation unit 108, and calculates A (3m + 2) by the MQ-CODER method. The A calculation unit 110 inputs CX (3m + 2) and D (3m + 2) and A (3m + 2) output from the A calculation unit 109, and calculates A (3m + 3) by the MQ-CODER method. A (3m + 3) calculated by the A calculation unit 110 is stored in the A register 107 in place of A (3m).

  In the storage unit 105, 111-0 to 111-4 indicate five of the registers included in the storage unit 105. The registers included in the storage unit 105 including the registers 111-0 to 111-4 are Qe ( k), BS (k), and Sel (k). However, k = 3m, 3m + 1, 3m + 2.

  In the second calculation means 106, 112 is a C register, and 113, 114, and 115 are C calculation units. The C register 112 stores C. The C calculation unit 113 inputs Qe, BS, and Sel stored in the register 111-0 and C stored in the C register 112, and calculates C and B by the MQ-CODER method.

  The C calculation unit 114 inputs Qe, BS, and Sel stored in the register 111-1 and C output from the C calculation unit 113, and calculates C and B by the MQ-CODER method. The C calculation unit 115 inputs Qe, BS, and Sel stored in the register 111-2 and C output from the C calculation unit 113, and calculates C and B by the MQ-CODER method. C calculated by the C calculation unit 115 is stored in the C register 112 in an update manner.

  FIG. 26 is a circuit diagram of the A arithmetic units 108, 109, and 110. In FIG. 26, in the A operation unit 108, reference numeral 116 denotes an index memory which inputs CX (3m) and outputs I (CX (3m)). Reference numeral 117 denotes a Qe table circuit which inputs I (CX (3m)) output from the index memory circuit 116 and outputs Qe (3m) = Qe (I (CX (3m))).

  A subtractor 118 subtracts Qe (3m) output from the Qe table circuit 117 from A (3m) stored in the A register 107. A comparator 119 compares Qe (3m) output from the Qe table circuit 117 by 1 bit to the left (Qe (3m) << 1) and A (3m) stored in the A register 107. When A (3m) << (Qe (3m) << 1), "1" is output, and otherwise, "0" is output.

  Reference numeral 120 denotes an MPS memory which inputs CX (3m) and outputs MPS (CX (3m)). Reference numeral 121 denotes an ExOR circuit which performs ExOR processing on MPS (CX (3m)) and D (3m) output from the MPS memory 120 and outputs IsLPS (3m). Reference numeral 122 denotes an ExOR circuit that performs ExOR processing on the output of the comparator 119 and IsLPS (3m) output from the ExOR circuit 121 and outputs Sel (3m).

  123 is a selector, and Sel (3m) output from the ExOR circuit 122 is used as selection control data. When Sel (3m) = “1”, Qe (3m) output from the Qe table circuit 117 is selected. When Sel (3m) = “0”, the subtracter 118 selects (A (3m) −Qe (3m)) output. Reference numeral 124 denotes a RENORME circuit which receives the output of the selector 123, performs encoding renormalization processing, and outputs A (3m + 1) and BS (3m).

  An AND circuit 125 AND-processes SWITCH (I (CX (3m))) and IsLPS (3m) output from the ExOR circuit 121. An ExOR circuit 126 performs an EXOR process on the MPS (CX (3m)) output from the MPS memory 120 and the output of the AND circuit 125 and outputs NxtMPS (CX (3m)). Reference numeral 127 denotes a next index circuit, I (CX (3m)) output from the index memory 116, (A (3m) -Qe (3m)) output from the subtractor 118, and IsLPS (exited by the ExOR circuit 121). 3m) is input and NxtI (CX (3m)) is output.

  In the A operation unit 109, reference numeral 128 denotes an index memory which inputs CX (3m + 1) and outputs PreI (CX (3m + 1)). Reference numeral 129 denotes a selector, and data indicating whether or not CX (3m) = CX (3m + 1) is used as selection control data. When CX (3m) = CX (3m + 1), the next index circuit 127 outputs. NxtI (CX (3m + 1)) is selected. When CX (3m) ≠ CX (3m + 1), PreI (CX (3m + 1)) output from the index memory 128 is selected. The output of the selector 129 is I (CX (3m + 1)).

  A Qe table circuit 130 receives I (CX (3m + 1)) output from the selector 129 and outputs Qe (3m + 1) = Qe (I (CX (3m + 1)) 131. Reference numeral 131 denotes a subtractor. Yes, Qe (3m + 1) output from the Qe table circuit 130 is subtracted from A (3m + 1) output from the RENORME circuit 124.

  A comparator 132 compares Qe (3m + 1) output from the Qe table circuit 130 by 1 bit to the left (Qe (3m + 1) << 1) and A (3m + 1) output from the RENORME circuit 124. When A (3m + 1) << (Qe (3m + 1) << 1), "1" is output, and otherwise, "0" is output. Reference numeral 133 denotes an MPS memory that inputs CX (3m + 1) and outputs PreMPS (CX (3m + 1)).

  Reference numeral 134 denotes a selector. The data indicating whether CX (3m) = CX (3m + 1) is used as selection control data. If CX (3m) = CX (3m + 1), the NxtMPS output from the ExOR circuit 126 is output. When (CX (3m)) is selected and CX (3m) ≠ CX (3m + 1), PreMPS (CX (3m + 1)) output from the MPS memory 133 is selected. The output of the selector 134 is MPS (CX (3m + 1)).

  Reference numeral 135 denotes an ExOR circuit, which performs ExOR processing on MPS (CX (3m + 1)) and D (3m + 1) output from the selector 134 and outputs IsLPS (3m + 1). An ExOR circuit 136 performs ExOR processing on the output of the comparator 132 and IsLPS (3m + 1) output from the ExOR circuit 135, and outputs Sel (3m + 1). A selector 137 selects Sel (3m + 1) output from the ExOR circuit 136 as selection control data. When Sel (3m + 1) = “1”, Qe (3m + 1) output from the Qe table circuit 130 is selected. When Sel (3m + 1) = “0”, the subtracter 131 selects (A (3m + 1) −Qe (3m + 1)) output.

  Reference numeral 138 denotes a RENORME circuit, which inputs Qe (3m + 1) or (A (3m + 1) −Qe (3m + 1)) output from the selector 137 and performs encoding renormalization processing to obtain A (3m + 2) and BS (3m + 1). Is output. An AND circuit 139 performs an AND process on SWITCH (I (CX (3m + 1))) and IsLPS (3m + 1) output from the ExOR circuit 135.

  Reference numeral 140 denotes an ExOR circuit which performs ExOR processing on the PreMPS (CX (3m + 1)) output from the MPS memory 133 and the output of the AND circuit 139 and outputs NxtMPS (CX (3m + 1)). Reference numeral 141 denotes a next index circuit, which is I (CX (3m + 1)) output from the selector 129, (A (3m + 1) -Qe (3m + 1)) output from the subtractor 131, and IsLPS (3m + 1) output from the ExOR circuit 135. And NxtI (CX (3m + 1)) is output.

  In the A operation unit 110, reference numeral 142 denotes an index memory which inputs CX (3m + 2) and outputs PreI (CX (3m + 2)). Reference numeral 143 denotes a selector. The data indicating whether CX (3m) = CX (3m + 2) is used as selection control data. When CX (3m) = CX (3m + 2), the next index circuit 127 outputs the data. NxtI (CX (3m + 2)) to be output from the index memory 142 is selected when CX (3m) ≠ CX (3m + 2).

  Reference numeral 144 denotes a selector. The data indicating whether CX (3m + 1) = CX (3m + 2) is used as selection control data. When CX (3m + 1) = CX (3m + 2), the next index circuit 141 outputs the data. NxtI (CX (3m + 1)) to be selected is selected, and when CX (3m) ≠ CX (3m + 1), the output of the selector 143 is selected. The output of the selector 144 is I (CX (3m + 2)).

  A Qe table circuit 145 receives I (CX (3m + 2)) output from the selector 144 and outputs Qe (3m + 2) = Qe (I (CX (3m + 2)). 146 is a subtractor. Yes, Qe (3m + 2) output from the Qe table circuit 145 is subtracted from A (3m + 2) output from the RENORME circuit 138.

  147 is a comparator that compares Qe (3m + 2) output from the Qe table circuit 145 by 1 bit to the left (Qe (3m + 2) << 1) and A (3m + 2) output from the RENORME circuit 138. When A (3m + 2) <(Qe (3m + 2) << 1), “1” is output, and otherwise “0” is output. Reference numeral 148 denotes an MPS memory that inputs CX (3m + 2) and outputs PreMPS (CX (3m + 2)).

  Reference numeral 149 denotes a selector, and data indicating whether CX (3m) = CX (3m + 2) is used as selection control data. If CX (3m) = CX (3m + 2), the NxtMPS output from the ExOR circuit 126 is output. When (CX (3m)) is selected and CX (3m) ≠ CX (3m + 2), PreMPS (CX (3m + 2)) output from the MPS memory 148 is selected.

  Reference numeral 150 denotes a selector. The data indicating whether or not CX (3m + 1) = CX (3m + 2) is used as selection control data. When CX (3m + 1) = CX (3m + 2), the NxtMPS output from the ExOR circuit 140 is output. When (CX (3m + 1)) is selected and CX (3m + 1) ≠ CX (3m + 2), the output of the selector 149 is selected. The output of the selector 150 is MPS (CX (3m + 2)).

  Reference numeral 151 denotes an ExOR circuit that performs ExOR processing on MPS (CX (3m + 2)) and D (3m + 2) output from the selector 150 and outputs IsLPS (3m + 2). An ExOR circuit 152 performs ExOR processing on the output of the comparator 147 and IsLSP (3m + 2) output from the ExOR circuit 151 and outputs Sel (3m + 2). A selector 153 selects Sel (3m + 2) output from the ExOR circuit 152 as selection control data. When Sel (3m + 2) = “1”, Qe (3m + 2) output from the Qe table circuit 145 is selected. When Sel (3m + 2) = “0”, the subtracter 146 selects (A (3m + 2) −Qe (3m + 2)).

  Reference numeral 154 denotes a RENORME circuit which receives the output of the selector 153, performs encoding renormalization processing, and outputs A (3m + 3) and BS (3m + 2). An AND circuit 155 performs an AND process on SWITCH (I (CX (3m + 2))) and IsLPS (3m + 2) output from the ExOR circuit 151. Reference numeral 156 denotes an ExOR circuit, which performs ExOR processing on the PreMPS (CX (3m + 2)) output from the MPS memory 148 and the output of the AND circuit 155 and outputs NxtMPS (CX (3m + 2)).

  Reference numeral 157 denotes a next index circuit, which is output from the selector 144 (CX (3m + 2)), output from the subtractor 146 (A (3m + 2) −Qe (3m + 2)), and IsLPS (3m + 2) output from the ExOR circuit 151. And NxtI (CX (3m + 2)) is output.

  FIG. 27 is a circuit diagram of a configuration example of the index memories 116, 128, and 142. In the third embodiment of the present invention, the index memories 116, 128, 142 are configured as a single unit. In FIG. 27, 159-i, 160-i, 161-i are selectors, 162-i are index registers, and 163, 164, 165 are selectors.

  The selector 159-i uses the data indicating whether or not CX (3m) = i as selection control data. When CX (3m) = i, the selector 159-i selects NxtI (CX (3m)) and CX (3m) = i. 3m) If ≠ i, the output of the index register 162-i is selected. The selector 160-i uses the data indicating whether or not CX (3m + 1) = i as selection control data. When CX (3m + 1) = i, the selector 160-i selects NxtI (CX (3m + 1)) and CX (3m + 1) = i. When 3m + 1) ≠ i, the output of the selector 159-i is selected.

  The selector 161-i uses data indicating whether or not CX (3m + 2) = i as selection control data. If CX (3m + 2) = i, NxtI (CX (3m + 2)) is selected and CX ( When 3m + 2) ≠ i, the output of the selector 160-i is selected. The index register 162-i stores the output of the selector 161-i. The selector 163 selects CX (3m) as the selection control data, and when CX (3m) = i, selects the output of the I register 162-i. The output of the selector 163 is I (CX (3m) ).

  The selector 164 selects CX (3m + 1) as selection control data, and when CX (3m + 1) = i, selects the output of the index register 162-i. The output of the selector 164 is PreI (CX (3m + 1). )). The selector 165 selects CX (3m + 2) as the selection control data, and when CX (3m + 2) = i, selects the output of the index register 162-i. The output of the selector 165 is PreI (CX (3m + 2). )).

  The MPS memories 120, 133, and 148 are configured in the same manner as the index memories 116, 128, and 142, and instead of NxtI (CX (3m)), NxtI (CX (3m + 1), and NxtI (CX (3m + 2)) shown in FIG. , NxtMPS (CX (3m + 1)), NxtMPS (CX (3m + 1)), and NxtMPS (CX (3m + 2)) are input in this way, so that I (CX (3m)), PreI (CX (3m + 1)), PreI Instead of (CX (3m + 2)), MPS (CX (3m)), PreMPS (CX (3m + 1)), and PreMPS (CX (3m + 2)) are output.

  FIG. 28 is a circuit diagram of the next index circuits 127, 141, and 157. In the next index 127, reference numeral 167 denotes a selector, and A (3m) [15] is selected control data. When A (3m) [15] = “0”, NMPS (I (CX (3m)) ) And A (3m) [15] = “1”, I (CX (3m)) is selected. A selector 168 uses IsLPS (3m) as selection control data. When IsLPS (3m) = "0", the output of the selector 167 is selected. When IsLPS (3m) = "1", NLPS (I (CX (3m))) is selected.

  In the next index circuit 141, reference numeral 169 denotes a selector. When A (3m + 1) [15] is selected control data, and A (3m + 1) [15] = “0”, NMPS (I (CX ( 3m + 1))) is selected, and when A (3m + 1) [15] = “1”, I (CX (3m + 1)) is selected. Reference numeral 170 denotes a selector, which uses IsLPS (3m + 1) as selection control data. When IsLPS (3m + 1) = “0”, the output of the selector 169 is selected. When IsLPS (3m + 1) = “1”, NLPS (I (CX (3m + 1))) is selected.

  In the next index circuit 157, reference numeral 171 denotes a selector. When A (3m + 2) [15] is selected control data, and A (3m + 2) [15] = “0”, NMPS (I (CX ( 3m + 2))) and when A (3m + 2) [15] = “1”, I (CX (3m + 2)) is selected. A selector 172 uses IsLPS (3m + 2) as selection control data. When IsLPS (3m + 2) = “0”, the output of the selector 171 is selected. When IsLPS (3m + 2) = “1”, NLPS (I (CX (3m + 2))) is selected.

  FIG. 29 is a circuit diagram of the C calculators 113, 114, and 115. In the C calculation unit 113, 174 is a selector. The selector 174 uses the data SelReg0 (= Sel stored in the register 111-0) indicating whether or not QeReg0 (= Qe stored in the register 111-0) is valid as selection control data, and SelReg0 = “0”. In this case, QeReg0 is selected, and when SelReg0 = "1", 0 is selected.

  Reference numeral 175 denotes an adder that adds C stored in the C register 10 and the output of the selector 175. A shifter 176 shifts the output of the adder 175 to the left by S0 = Min (CT, BSReg0 + BSReg1 + BSReg2). However, BSReg0 is a BS stored in the register 111-0, BSReg1 is a BS stored in the register 111-1, and BSReg2 is a BS stored in the register 111-2.

  Reference numeral 177 denotes a selector. The selector 177 uses the data SelReg1 (= Sel stored in the register 111-1) indicating whether or not QeReg1 (= Qe stored in the register 111-1) is valid as the selection control data, and SelReg1 = “0”. In this case, QeReg1 is selected, and when SelReg1 = "1", 0 is selected. A shifter 178 shifts the output of the selector 177 to the left by S1 = Min (CT-BSReg0, BSReg1 + BSReg2). An adder 179 adds C output from the shifter 176 and output from the shifter 178 and outputs C.

  Reference numeral 180 denotes a selector. The selector 180 uses the data SelReg2 (= Sel stored in the register 111-2) indicating whether or not QeReg2 (= Qe stored in the register 111-2) is valid as the selection control data, and SelReg2 = “0”. In this case, QeReg2 is selected, and when SelReg2 = "1", 0 is selected. A shifter 181 shifts the output of the selector 180 to the left by S2 = Min (CT-BSReg0-BSReg1, BSReg2). Reference numeral 182 denotes an adder which adds C output from the adder 179 and the output of the shifter 181 to output C.

  Reference numerals 183 and 184 denote selectors. The selector 183 uses the data indicating whether or not CT <= BSReg0 as the selection control data. When CT <= BSReg0, the selector 183 selects the output of the shifter 176, and when CT> BSReg0, the selector 184 outputs. To choose. The selector 184 uses the data indicating whether CT <= BSReg0 + BSReg1 as selection control data, selects the output of the adder 179 when CT <= BSReg0 + BSReg1, and outputs the adder 182 when CT> BSReg0 + BSReg1. Is to select.

  A byte-out circuit 185 inputs the output of the selector 183 and calculates B. Reference numeral 186 denotes a selector, and data indicating whether or not BSReg0 + BSReg1 + BSReg2> = CT is selected as control data. If BSReg0 + BSReg1 + BSReg2> = CT, the output C of the byte-out circuit 185 is selected. The output of the adder 182 is selected.

  In the third embodiment of the present invention, the first computing means 104 inputs CX and D and computes A and outputs Qe, BS and Sel, and the storage means 105 The output Qe, BS, and Sel are stored, and the second calculation means 106 inputs Qe, BS, and Sel stored in the storage means 105 and calculates C and B.

  That is, according to the third embodiment of the present invention, the first calculation means 104 for calculating A and the second calculation means 106 for calculating C and B are connected to Qe, BS, Sel output from the first calculation means 104. Therefore, the calculation of A can be performed even when byte out occurs or when the calculation result of C is output. Therefore, the operation of A can be performed continuously, and the speed of the arithmetic coding operation of the MQ-CODER system can be increased.

  Also, three A arithmetic units 108, 109, and 110 are provided, and a group of CX (3m) and D (3m) and a group of CX (3m + 1) and D (3m + 1) and CX (3m + 2) and D (3m + 2) Since the sets are input in parallel and can be processed in parallel, the speed can be increased as compared with the second embodiment of the present invention.

(Fourth embodiment)
FIG. 30 is a circuit diagram showing the main part of the fourth embodiment of the present invention. In FIG. 30, reference numeral 188 denotes first calculation means, 189 denotes storage means, and 190 denotes second calculation means. The first computing means 188 computes A by inputting CX and D. The storage means 189 stores Qe, BS, and Sel necessary for the calculation of C output from the first calculation means 188. The second calculation means 190 inputs Qe, BS and Sel necessary for the calculation of C stored in the storage means 189 and calculates C and B. In the present embodiment, a group of CX (2m) and D (2m) and a group of CX (2m + 1) and D (2m + 1) are given in parallel from a preceding apparatus (not shown).

  In the first calculation means 188, 191 is an A register, and 192 and 193 are A calculation units. The A register 191 stores A (2 m). The A calculation unit 192 inputs CX (2m) and D (2m) and A (2m) stored in the A register 191 and calculates A (2m + 1) by the MQ-CODER method. The A calculation unit 193 inputs CX (2m + 1), D (2m + 1) and A (2m + 1) output from the A calculation unit 192, and calculates A (2m + 2) by the MQ-CODER method. A (2m + 2) calculated by the A calculation unit 193 is stored in the A register 191 in place of A (2m).

  In the storage unit 189, reference numerals 194-0 to 194-4 denote five of the registers included in the storage unit 189. The registers included in the storage unit 189 including the registers 194-0 to 194-4 are Qe ( j), BS (j), and Sel (j). However, j is 2m and 2m + 1.

  In the second calculation means 190, 195 is a C register, 196, 197, and 198 are C calculation units. The C register 195 stores C. The C calculation unit 196 inputs Qe, BS, and Sel stored in the register 194-0 and C stored in the C register 195, and calculates C and B by the MQ-CODER method. The C calculation unit 197 inputs Qe, BS, and Sel stored in the register 194-1 and C output from the C calculation unit 196, and calculates C and B by the MQ-CODER method.

  The C calculation unit 198 inputs Qe, BS, and Sel stored in the register 194-2 and C output from the C calculation unit 197, and calculates C and B by the MQ-CODER method. C calculated by the C calculation unit 198 is stored in the C register 195 in an update manner.

  31 to 38 are circuit diagrams showing an operation example of the fourth embodiment of the present invention. The Qe, BS, and Sel write / read control for the storage unit 189 is performed by a predetermined control circuit (not shown), but the Qe, BS, and Sel write / read for the storage unit 189 shown in FIGS. The control is an example, and other methods can be used.

  FIG. 31 shows a case where CX (0) and D (0) are given from the preceding apparatus to the A computing unit 192 and CX (1) and D (1) are given to the A computing unit 193 at time t = T0. Show. In this case, the A operation unit 192 inputs A (0) output from the A register 191 to calculate A (1), and outputs Qe (0), BS (0), and Sel (0). A (1) is given to the A operation unit 193, and Qe (0), BS (0), and Sel (0) are stored in the register 194-0. The A calculation unit 193 receives A (1) output from the A calculation unit 192, calculates A (2), and outputs Qe (1), BS (1), and Sel (1). A (2) is stored in the A register 191, and Qe (1), BS (1), and Sel (1) are stored in the register 194-1.

  FIG. 32 shows a case where CX (2) and D (2) are given from the preceding apparatus to the A computing unit 192 at the time t = T1, and CX (3) and D (3) are given to the A computing unit 193. Show. In this case, the C operation unit 196 inputs Qe (0), BS (0), Sel (0) stored in the register 194-0 and C (0) stored in the C register 195 and inputs C (1). Calculate. The C calculation unit 197 inputs Qe (1), BS (1), Sel (1) stored in the register 194-1 and C (1) calculated by the C calculation unit 196, and calculates C (2). . C (2) is updated and stored in the C register 195.

  On the other hand, the A calculation unit 192 inputs A (2) output from the A register 191 to calculate A (3), and outputs Qe (2), BS (2), and Sel (2). A (3) is given to the A operation unit 193, and Qe (2), BS (2), and Sel (2) are stored in the register 194-0. The A calculation unit 193 receives A (3) output from the A calculation unit 192, calculates A (4), and outputs Qe (3), BS (3), and Sel (3). A (4) is stored in the A register 191, and Qe (3), BS (3), and Sel (3) are stored in the register 194-1.

  FIG. 33 shows a case where CX (4) and D (4) are given from the preceding apparatus to the A computing unit 192 at the time t = T2, and CX (5) and D (5) are given to the A computing unit 193. Show. In this case, the C calculation unit 196 inputs Qe (2), BS (2), Sel (2) stored in the register 194-0 and C (2) stored in the C register 195 and inputs C (3). Calculate. The C calculation unit 197 inputs Qe (3), BS (3), Sel (3) stored in the register 194-1 and C (3) calculated by the C calculation unit 196. If it occurs, the C calculation unit 197 calculates B (0). The post-processed BS ′ (3) is stored in the register 194-0.

  On the other hand, the A calculation unit 192 inputs A (4) output from the A register 191 to calculate A (5), and outputs Qe (4), BS (4), and Sel (4). A (5) is given to the A operation unit 193, and Qe (4), BS (4), and Sel (4) are stored in the register 194-1. The A calculation unit 193 receives A (5) output from the A calculation unit 192, calculates A (6), and outputs Qe (5), BS (5), and Sel (5). A (6) is stored in the A register 191, and Qe (5), BS (5), and Sel (5) are stored in the register 194-2.

  FIG. 34 shows a case where CX (6) and D (6) are given from the preceding apparatus to the A computing unit 192 and CX (7) and D (7) are given to the A computing unit 193 at time t = T3. Show. In this case, the C calculation unit 196 inputs BS ′ (3) stored in the register 194-0 and C ′ (3) stored in the C register 195, and calculates C (4). The C calculation unit 197 inputs Qe (4), BS (4), Sel (4) stored in the register 194-1 and C (4) calculated by the C calculation unit 196, and calculates C (5). . The C calculation unit 198 inputs Qe (5), BS (5), Sel (5) stored in the register 194-2 and C (5) calculated by the C calculation unit 197 and calculates C (6). . C (6) is stored in the C register 195 in an update manner.

  On the other hand, the A calculation unit 192 inputs A (6) output from the A register 191 to calculate A (7), and outputs Qe (6), BS (6), and Sel (6). A (7) is provided to the A operation unit 193, and Qe (6), BS (6), and Sel (6) are stored in the register 194-0. The A calculation unit 193 receives A (7) output from the A calculation unit 192, calculates A (8), and outputs Qe (7), BS (7), and Sel (7). A (8) is updated and stored in the A register 191, and Qe (7), BS (7), and Sel (7) are stored in the register 194-1.

  FIG. 35 shows a case where CX (8) and D (8) are given from the preceding apparatus to the A computing unit 192 and CX (9) and D (9) are given to the A computing unit 193 at time t = T4. Show. In this case, the C calculation unit 196 inputs Qe (6), BS (6), Sel (6) stored in the register 194-0 and C (6) stored in the C register 195. If out occurs, the C calculation unit 196 calculates B (1). The post-processed BS ′ (6) is stored in the register 194-0. C ′ (6) output from the C calculation unit 196 is stored in the C register 196.

  On the other hand, the A calculation unit 192 inputs A (8) output from the A register 191 to calculate A (9), and outputs Qe (8), BS (8), and Sel (8). A (9) is given to the A operation unit 193, and Qe (8), BS (8), and Sel (8) are stored in the register 194-2. The A calculation unit 193 receives A (9) output from the A calculation unit 192, calculates A (10), and outputs Qe (9), BS (9), and Sel (9). A (10) is updated and stored in the A register 191, and Qe (9), BS (9), and Sel (9) are stored in the register 194-4.

  FIG. 36 shows a case where CX (10) and D (10) are given from the preceding apparatus to the A computing unit 192 and CX (11) and D (11) are given to the A computing unit 193 at time t = T5. Show. In this case, the C calculation unit 196 inputs BS ′ (6) stored in the register 194-0 and inputs C ′ (6) stored in the C register 195 to calculate C (7). The C calculation unit 197 inputs Qe (7), BS (7), Sel (7) stored in the register 194-1 and C (7) calculated by the C calculation unit 196, and calculates C (8). . The C calculation unit 198 inputs Qe (8), BS (8), Sel (8) stored in the register 194-2 and C (8) calculated by the C calculation unit 197, and calculates C (9). . C (9) is stored in the C register 195 in an update manner.

  On the other hand, the A calculation unit 192 inputs A (10) output from the A register 191 to calculate A (11), and outputs Qe (10), BS (10), and Sel (10). A (11) is given to the A operation unit 193, and Qe (10), BS (10), and Sel (10) are stored in the register 194-1. The A calculation unit 193 receives A (11) output from the A calculation unit 192, calculates A (12), and outputs Qe (11), BS (11), and Sel (11). A (12) is stored in the A register 191, and Qe (11), BS (11), and Sel (11) are stored in the register 194-2. Qe (9), BS (9), and Sel (9) stored in the register 194-3 are stored in the register 194-0.

  FIG. 37 shows a case where CX (12) and D (12) are given from the preceding apparatus to the A computing unit 192 and CX (13) and D (13) are given to the A computing unit 193 at time t = T6. Show. In this case, the C calculation unit 196 inputs Qe (9), BS (9), Sel (9) stored in the register 194-0 and C (9) stored in the C register 195, and inputs C (10). Calculate.

  The C calculation unit 197 inputs Qe (10), BS (10), Sel (10) stored in the register 194-1 and C (10) calculated by the C calculation unit 196, and calculates C (11). . The C calculation unit 198 inputs Qe (11), BS (11), Sel (11) stored in the register 194-2 and C (11) calculated by the C calculation unit 197, and calculates C (12). . C (12) is stored in the C register 195 in an update manner.

  On the other hand, the A calculation unit 192 inputs A (12) output from the A register 191 to calculate A (13), and outputs Qe (12), BS (12), and Sel (12). A (13) is given to the A operation unit 193, and Qe (12), BS (12), and Sel (12) are stored in the register 194-0. The A calculation unit 193 receives A (13) output from the A calculation unit 192, calculates A (14), and outputs Qe (13), BS (13), and Sel (13). A (14) is updated and stored in the A register 191, and Qe (13), BS (13), and Sel (13) are stored in the register 194-1.

  FIG. 38 shows a case where CX (14) and D (14) are given from the preceding apparatus to the A computing unit 192 and CX (15) and D (15) are given to the A computing unit 193 at time t = T7. ing. In this case, the C operation unit 196 inputs Qe (12), BS (12), Sel (12) stored in the register 194-0 and C (12) stored in the C register 195, and inputs C (13). Calculate. The C calculation unit 197 inputs Qe (13), BS (13), Sel (13) stored in the register 194-1 and C (13) calculated by the C calculation unit 196, and calculates C (14). To do. C (14) is stored in the C register 195 in an update manner.

  On the other hand, the A operation unit 192 inputs A (14) output from the A register 191 to calculate A (15), and outputs Qe (14), BS (14), and Sel (14). A (15) is given to the A operation unit 193, and Qe (14), BS (14), and Sel (14) are stored in the register 194-0. The A calculation unit 193 receives A (15) output from the A calculation unit 192, calculates A (16), and outputs Qe (15), BS (15), and Sel (15). A (16) is updated and stored in the A register 191, and Qe (15), BS (15), and Sel (15) are stored in the register 194-1.

  As described above, according to the fourth embodiment of the present invention, the first calculation means 188 for calculating A and the second calculation means 190 for calculating C and B are output by Qe, Since it is configured independently via the storage means 189 for storing BS and Sel, the calculation of A is performed even when byteout occurs or when the calculation result of C is output. Can do. Therefore, the operation of A can be performed continuously, and the speed of the arithmetic coding operation of the MQ-CODER system can be increased.

  In addition, two A arithmetic units 192 and 193 are provided, and a set of CX (2m) and D (2m) and a set of CX (2m + 1) and D (2m + 1) can be input in parallel, and these can be processed in parallel. As a result, it is possible to achieve the same speed increase as in the case of the second embodiment of the present invention. Further, since the second calculation means is provided with three C calculation units 196, 197, and 198, which are larger in number than the A calculation unit, if the output of B does not occur for a while after the continuous output of B, the second calculation means is stored. Of the registers in the means 189, two registers can be returned. Therefore, the scale of the storage unit 189 can be made smaller than the storage unit 48 provided in the second embodiment of the present invention.

It is a circuit diagram which shows the principal part of 1st Embodiment of this invention. It is a circuit diagram of the A calculating part with which 1st Embodiment of this invention is provided. It is a circuit diagram of the 1st structural example of the index memory with which 1st Embodiment of this invention is provided. It is a circuit diagram of the 2nd structural example of the index memory with which 1st Embodiment of this invention is provided. It is a circuit diagram of the 1st example of composition of MPS memory with which a 1st embodiment of the present invention is provided. It is a circuit diagram of the 2nd example of composition of MPS memory with which a 1st embodiment of the present invention is provided. It is a circuit diagram of the next index circuit with which 1st Embodiment of this invention is provided. It is a circuit diagram of the C calculating part with which 1st Embodiment of this invention is provided. It is a circuit diagram which shows the operation example of 1st Embodiment of this invention. It is a circuit diagram which shows the operation example of 1st Embodiment of this invention. It is a circuit diagram which shows the operation example of 1st Embodiment of this invention. It is a circuit diagram which shows the operation example of 1st Embodiment of this invention. It is a circuit diagram which shows the operation example of 1st Embodiment of this invention. It is a circuit diagram which shows the principal part of 2nd Embodiment of this invention. It is a circuit diagram of the A calculating part with which 2nd Embodiment of this invention is provided. It is a circuit diagram of the index memory with which 2nd Embodiment of this invention is provided. It is a circuit diagram of the next index circuit with which 2nd Embodiment of this invention is provided. It is a circuit diagram of the C calculating part with which 2nd Embodiment of this invention is provided. It is a circuit diagram which shows the operation example of 2nd Embodiment of this invention. It is a circuit diagram which shows the operation example of 2nd Embodiment of this invention. It is a circuit diagram which shows the operation example of 2nd Embodiment of this invention. It is a circuit diagram which shows the operation example of 2nd Embodiment of this invention. It is a circuit diagram which shows the operation example of 2nd Embodiment of this invention. It is a circuit diagram which shows the operation example of 2nd Embodiment of this invention. It is a circuit diagram which shows the principal part of 3rd Embodiment of this invention. It is a circuit diagram of the A calculating part with which 3rd Embodiment of this invention is provided. It is a circuit diagram of the index memory with which 3rd Embodiment of this invention is provided. It is a circuit diagram of the next index circuit with which 3rd Embodiment of this invention is provided. It is a circuit diagram of the C calculating part with which 3rd Embodiment of this invention is provided. It is a circuit diagram which shows the principal part of 4th Embodiment of this invention. It is a circuit diagram which shows the operation example of 4th Embodiment of this invention. It is a circuit diagram which shows the operation example of 4th Embodiment of this invention. It is a circuit diagram which shows the operation example of 4th Embodiment of this invention. It is a circuit diagram which shows the operation example of 4th Embodiment of this invention. It is a circuit diagram which shows the operation example of 4th Embodiment of this invention. It is a circuit diagram which shows the operation example of 4th Embodiment of this invention. It is a circuit diagram which shows the operation example of 4th Embodiment of this invention. It is a circuit diagram which shows the operation example of 4th Embodiment of this invention. It is a circuit diagram of the principal part of an example of the arithmetic coding arithmetic unit of the conventional MQ-CODER system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Operation part 2 ... Register 4, 47, 104, 188 ... 1st calculation means 5, 48, 105, 189 ... Storage means 6, 49, 106, 190 ... 2nd calculation means 7, 50, 107, 191 ... A Registers 8, 51, 52, 108 to 110, 192, 193... A operation unit 9-x, 53-x, 111-x, 194-x ... Registers 10, 54, 112, 195 ... C registers 11, 55, 56 , 113 to 115, 196 to 198 ... C calculation unit

Claims (5)

An agenda computing unit that inputs a context and a symbol and computes an agenda, and outputs predetermined data;
A storage unit for storing predetermined data output by the audend calculation unit;
An MQ-CODER type arithmetic coding arithmetic unit comprising a code arithmetic unit for inputting predetermined data stored in the storage unit and calculating code and byte data.   2. The MQ according to claim 1, wherein the predetermined data is data indicating whether a recessive symbol probability, a bit shift amount of an augend in re-normalization processing at the time of encoding, and the recessive symbol probability are valid. A coder-type arithmetic coding arithmetic unit.   2. The MQ-CODER arithmetic coding arithmetic unit according to claim 1, wherein the audend arithmetic units are connected in multiple stages using the agenda as input / output values.   2. The MQ-CODER arithmetic coding arithmetic unit according to claim 1, wherein the code arithmetic units are connected in multiple stages using codes as input / output values. 5. The MQ-CODER arithmetic coding arithmetic unit according to claim 4, wherein the number of the code arithmetic units is larger than that of the audend arithmetic units.

Images