JP2005340627A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device along with its manufacturing method capable of releasing electrons that are charged in a gate electrode even in the process before a metal wiring layer is formed, during a manufacturing process. <P>SOLUTION: Near a first element region 14 in which a transistor is formed, being enclosed with an STI part 12, a second element region 15 enclosed with the STI part 12 is formed. AN n+ diffusion layer 16 is formed on the second element region 15, and the n+ diffusion layer 16 and a substrate 11 constitute a pn junction diode. An extension part 18a of the gate electrode covers a part of gate insulating film 17b on the second element region 15, and is connected to the n+ diffusion layer 16 on the second element region 15 through an opening 17c provided to the gate insulating film 17b. The extension 18a of the gate electrode 18 is further connected to a metal wiring formed on an upper layer by the contact that penetrates an interlayer insulating film. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufactured with plasma processing and a manufacturing method thereof.

  In the semiconductor device manufacturing process, some of the electrons generated when the metal wiring layer is formed by plasma etching are charged into the metal wiring layer of the semiconductor device. When a large amount of electrons are charged in the metal wiring connected to the gate electrode of the transistor, a large surge voltage is applied to the gate electrode, and the gate insulating film located under the gate electrode is destroyed or deteriorated, so that the transistor Since the characteristics fluctuate, the manufacturing yield is reduced. In order to avoid this decrease in yield, a path for allowing electrons charged in the metal wiring to escape to the semiconductor substrate is provided, and in order to suppress the peak value of the surge voltage applied to the gate electrode, it is provided between the metal wiring and the gate electrode. There have been proposals for providing a resistor (for example, Patent Documents 1 and 2).

  In the proposals shown in Patent Document 1 and Patent Document 2, a diffusion layer constituting a diode is formed on a semiconductor substrate, and the diffusion layer and the gate electrode are connected via a metal wiring of a metal wiring layer. Thereby, the electrons charged in the metal wiring connected to the gate electrode can be emitted to the semiconductor substrate by plasma etching at the time of forming the metal wiring.

JP-A-8-97416 Japanese Patent Laid-Open No. 2000-1224311

  However, since the gate electrode and the diffusion layer are not electrically connected in the step before forming the metal wiring layer, for example, a contact or a contact hole for connecting the gate electrode and the metal wiring layer is formed. There is no means for emitting electrons charged in the gate electrode by the plasma treatment. For this reason, there is a possibility that the gate insulating film may be broken or the characteristics of the transistor may be changed by plasma treatment when forming a contact or the like.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of emitting electrons charged in a gate electrode even in a process before forming a metal wiring layer in a manufacturing process. And a manufacturing method thereof.

  In a semiconductor device formed on a semiconductor substrate, the semiconductor device of the present invention includes a first element region in which a transistor is formed, and a second element region having a diffusion layer that forms a pn junction diode together with the semiconductor substrate. A gate electrode formed on the first element region to which a control voltage for controlling the operation of the transistor is applied, extending from the first element region The gate electrode connected to the diffusion layer, an interlayer insulating film formed on the gate electrode, and a metal wiring layer formed on the interlayer insulating film, and applying the control voltage to the gate electrode And a contact that penetrates the interlayer insulating film and connects the gate electrode and the metal wiring, and the gate electrode is connected to the metal wiring layer and the front. Characterized in that it is connected to the diffusion layer between the semiconductor substrate.

  According to this, the diffusion layer that forms the pn junction diode together with the semiconductor substrate is provided on the semiconductor substrate, the gate electrode extends from the first element region, and the diffusion layer is formed between the semiconductor substrate and the metal wiring layer. It is connected to the. That is, since the metal wiring of the metal wiring layer is not interposed in the connection between the gate electrode and the diffusion layer as in the prior art, electrons charged in the gate electrode in the process before forming the metal wiring are also transferred to the semiconductor substrate. Can be released.

  In this semiconductor device, the gate electrode may extend from the first element region and cover the diffusion layer in a conductive manner.

  In this semiconductor device, the gate electrode may be connected to the diffusion layer through the contact.

  According to this, the connection between the gate electrode and the diffusion layer is made through the contact for connecting the gate electrode and the metal wiring. That is, it is possible to connect the gate electrode, the metal wiring, and the diffusion layer by one contact, and it is possible to reduce the space required for connecting each.

  In this semiconductor device, an integral conductor film may be formed to cover the top and side surfaces of the gate electrode and the top surface of the diffusion layer, and the gate electrode may be connected to the diffusion layer by the conductor film.

  According to this, since the integral conductor film covering the upper and side surfaces of the gate electrode and the upper surface of the diffusion layer is formed, electrons charged in the gate electrode are reliably emitted to the semiconductor substrate through this conductor film. It becomes possible to do.

  In this semiconductor device, a side wall made of an insulating material is further formed on the side surface of the gate electrode, and an integral conductor covering the upper surface of the gate electrode, the outer surface of the side wall, and the upper surface of the diffusion layer. A film may be formed, and the gate electrode may be connected to the diffusion layer via the conductor film.

  According to this, a side wall made of an insulating material is formed on the side surface of the gate electrode, and an integral conductor film covering the upper surface of the gate electrode, the outer surface of the side wall, and the upper surface of the diffusion layer is formed. Through this conductor film, electrons charged in the gate electrode can be reliably discharged to the semiconductor substrate. Furthermore, since the conductor film is formed on the outer surface of the sidewall, it is not necessary to remove the sidewall in order to form the conductor film for connecting the gate electrode and the diffusion layer.

  In this semiconductor device, the path from the part where the gate electrode is connected to the metal wiring to the part connected to the diffusion layer is from the part where the gate electrode is connected to the metal wiring to the first element region. It is desirable that the route is shorter than the route leading to.

  According to this, the path from the part where the gate electrode is connected to the metal wiring to the part connected to the diffusion layer is shorter than the path from the part where the gate electrode is connected to the metal wiring to the first element region. Therefore, it is possible to suppress the electrons charged in the metal wiring from reaching the first element region, and easily discharge the electrons to the semiconductor substrate through the diffusion layer.

  In this semiconductor device, it is preferable that the gate electrode is connected to the diffusion layer in the middle of a path from a portion connected to the metal wiring to the first element region.

  According to this, since the gate electrode is connected to the diffusion layer in the middle of the path from the portion connected to the metal wiring to the first element region, the electrons charged in the metal wiring are transferred to the first element. This makes it easier to discharge the electrons to the semiconductor substrate through the diffusion layer.

  In this semiconductor device, a high resistance region having a resistance value higher than that of other regions on the gate electrode is provided in the middle of a path from the portion where the gate electrode is connected to the metal wiring to the first element region. It is desirable to be provided.

  According to this, a high resistance region having a resistance value higher than that of other regions on the gate electrode is provided in the middle of the path from the portion where the gate electrode is connected to the metal wiring to the first element region. The peak value of the surge voltage applied to the gate electrode on the first element region by the electrons charged in the metal wiring can be kept low.

  In this semiconductor device, the gate electrode is formed of polysilicon having a silicide film formed on an upper surface, and the high resistance region is provided at a portion extending from the first element region of the gate electrode. It is desirable to have a high resistance value by not forming a silicide film.

  When a semiconductor device is provided with a resistor, a diffusion layer having an electric resistance of a predetermined resistance value is formed on the semiconductor substrate, a long wiring is provided in the metal wiring layer or the gate electrode layer, and the wiring resistance is used, or the gate A method is conceivable in which a large number of contacts are formed between the electrode layer and the metal wiring layer or between different metal wiring layers and the contact resistance is utilized. Since the resistor formed in this manner requires a relatively large area in itself or in a region for connection with the resistor, the space efficiency is deteriorated.

  However, according to this, since the high resistance region is provided in a portion extending from the first element region of the gate electrode, the metal wiring or contact only for connecting the gate electrode and the high resistance region is provided. There is no need to form. Furthermore, since the high resistance region has a high resistance value because the silicide film is not formed on the upper surface, the high resistance region has a stable resistance in a small area as compared with the resistance due to the long wiring and a large number of contacts. Is possible.

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device, wherein the diffusion layer is formed, and the gate electrode covers a part of the diffusion layer so as to be conductive. The method includes a step of forming a gate electrode, a step of forming the interlayer insulating film, a step of forming the contact, and a step of forming the metal wiring.

  According to this, the gate electrode is formed on the semiconductor substrate so as to include a diffusion layer that forms a pn junction diode together with the semiconductor substrate, and a part of the gate electrode is connected to the diffusion layer. Since the metal wiring of the metal wiring layer is not interposed in the connection between the gate electrode and the diffusion layer, the electrons charged in the gate electrode in the process before forming the metal wiring are also emitted to the semiconductor substrate. It becomes possible to do.

  The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing the semiconductor device, the step of forming the interlayer insulating film on the semiconductor substrate on which the diffusion layer and the gate electrode are formed, and the interlayer insulation The film includes a step of forming the contact connectable to both the gate electrode and the diffusion layer, and a step of forming the metal wiring.

  According to this, a diffusion layer which forms a pn junction diode together with the semiconductor substrate is provided on the semiconductor substrate, and the gate electrode and the diffusion layer are connected by the contact. That is, since the metal wiring of the metal wiring layer is not interposed in the connection between the gate electrode and the diffusion layer as in the prior art, electrons charged in the gate electrode in the process before forming the metal wiring are also transferred to the semiconductor substrate. Can be released.

  Further, according to this, the connection between the gate electrode and the diffusion layer is made through a contact for connecting the gate electrode and the metal wiring. As a result, since the gate electrode, the metal wiring, and the diffusion layer are connected by one contact, it is possible to reduce the space required for connecting each.

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device, wherein the upper surface and side surfaces of the gate electrode and the diffusion layer are formed on the semiconductor substrate on which the diffusion layer and the gate electrode are formed. The method includes a step of forming an integral conductor film covering an upper surface, a step of forming the interlayer insulating film, a step of forming the contact, and a step of forming the metal wiring.

  According to this, a diffusion layer that forms a pn junction diode together with the semiconductor substrate is provided on the semiconductor substrate, and the gate electrode and the diffusion layer are integrally formed to cover the upper surface and side surfaces of the gate electrode and the upper surface of the diffusion layer. They are connected by a conductor film. That is, since the metal wiring of the metal wiring layer is not interposed in the connection between the gate electrode and the diffusion layer as in the prior art, electrons charged in the gate electrode in the process before forming the metal wiring are also transferred to the semiconductor substrate. Can be released.

  In this method of manufacturing a semiconductor device, the conductor film is preferably a silicide film.

  According to this, since the silicide film is used as the conductor film, the conductor film can be formed (salicide) in a self-aligned manner, and the conductor film can be easily formed.

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device, the step of forming the sidewall on the semiconductor substrate on which the diffusion layer and the gate electrode are formed, A step of forming an integral conductor film covering the upper surface and the outer surface of the sidewall and the upper surface of the diffusion layer; a step of forming the interlayer insulating film; a step of forming the contact; and And a forming step.

  According to this, a diffusion layer that forms a pn junction diode together with the semiconductor substrate is provided on the semiconductor substrate, and the gate electrode and the diffusion layer are provided on the upper surface of the gate electrode, the outer surface of the sidewall, and the upper surface of the diffusion layer. They are connected by an integral conductor film that covers them. That is, since the metal wiring of the metal wiring layer is not interposed in the connection between the gate electrode and the diffusion layer as in the prior art, electrons charged in the gate electrode in the process before forming the metal wiring are also transferred to the semiconductor substrate. Can be released.

  Furthermore, according to this, since the conductor film is formed on the outer surface of the sidewall, it is not necessary to remove the sidewall in order to form the conductor film.

  In this method of manufacturing a semiconductor device, the step of forming an integral conductor film covering the upper surface of the gate electrode, the outer surface of the sidewalls, and the upper surface of the diffusion layer includes forming a metal on the diffusion layer and the gate electrode. Forming a film; forming a silicide film on the upper surface of the gate electrode and the upper surface of the diffusion layer; and forming a film on the outer surface of the sidewall. Preferably, the method includes a step of forming a masking layer on the formed metal film, a step of removing the metal film at a portion where the masking layer is not formed, and a step of removing the masking layer.

  According to this, since the silicide film is used as the conductor film, the conductor film on the upper surface of the gate electrode and the upper surface of the diffusion layer can be formed in a self-aligned manner (salicide), and the conductor film can be easily formed. Become.

  In this method of manufacturing a semiconductor device, the diffusion layer may be formed simultaneously with the diffusion layer of the transistor after the gate electrode is formed.

  According to this, since the diffusion layer constituting the pn junction diode is formed at the same time as the diffusion layer of the transistor, the manufacturing process can be simplified.

  A method of manufacturing a semiconductor device according to the present invention includes a transistor, a diffusion layer that forms a pn junction diode together with the semiconductor substrate, and a gate electrode to which a control signal for controlling the operation of the transistor is applied. An interlayer insulating film formed on the gate electrode, a metal wiring formed on the interlayer insulating film, and a contact that passes through the interlayer insulating film and connects the gate electrode and the metal wiring. A method of manufacturing a semiconductor device, comprising: a step of connecting the gate electrode and the diffusion layer before the step of forming the metal wiring.

  According to this, the gate electrode and the diffusion layer are connected before the step of forming the metal wiring on the semiconductor substrate provided with the diffusion layer that constitutes the pn junction diode together with the semiconductor substrate. For this reason, if it is after connecting a gate electrode and a diffusion layer, it becomes possible to discharge | release the electron charged to a gate electrode to a semiconductor substrate in the process before forming metal wiring.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device formed on a semiconductor substrate, and includes a first element region in which a transistor is formed and a diffusion layer that forms a pn junction diode together with the semiconductor substrate. A step of forming the diffusion layer on the semiconductor substrate comprising a second element region formed with: extending from the first element region to the second element region; A step of forming a conductive gate electrode, a step of forming an interlayer insulating film on the upper surface of the gate electrode, a step of forming a contact connected to the gate electrode on the interlayer insulating film, Forming a metal wiring connected to the contact on the upper surface of the interlayer insulating film.

  According to this, on the semiconductor substrate provided with the diffusion layer constituting the pn junction diode together with the semiconductor substrate, it extends from the first element region to the second element region including the diffusion layer and is connected to the diffusion layer. After the gate electrode to be formed is formed, the metal wiring is formed. That is, the gate electrode and the diffusion layer are connected before the step of forming the metal wiring. For this reason, if it is after connecting a gate electrode and a diffusion layer, it becomes possible to discharge | release the electron charged to a gate electrode to a semiconductor substrate in the process before forming metal wiring.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing the semiconductor device of the present embodiment, and FIG.

  As shown in FIGS. 1 and 2, an STI (Shallow Trench Isolation) portion 12 as an element isolation portion is formed on a p-type silicon substrate (hereinafter referred to as “substrate”) 11 of the semiconductor device 10. The first element region 14 surrounded by the STI portion 12 is provided with a source / drain region 13 constituting a transistor. In the vicinity of the first element region 14, a second element region 15 that is also surrounded by the STI portion 12 is provided. An n + diffusion layer 16 is formed on the second element region 15, and the n + diffusion layer 16 and the substrate 11 constitute a pn junction diode.

  Gate insulating films 17a and 17b are respectively formed on the upper surfaces of the first element region 14 and the second element region 15, and the gate insulating film 17b on the second element region 15 is provided with an opening 17c. ing. On the upper surface of the first element region 14, the second element region 15, and the STI portion 12 interposed between the two regions, a gate electrode 18 constituting a transistor is formed with gate insulating films 17a and 17b interposed therebetween. Yes.

  The gate electrode 18 includes a portion on the first element region 14 and an extending portion 18 a extending from the first element region 14, and the extending portion 18 a is a gate on the second element region 15. A portion of the insulating film 17b is covered and connected to the n + diffusion layer 16 on the second element region 15 through an opening 17c provided in the gate insulating film 17b. Further, the extending portion 18a of the gate electrode 18 is connected to a metal wiring 24 formed in an upper layer by a contact 23 penetrating the interlayer insulating film 21 (see FIG. 5C). The transistor can be controlled by applying a control voltage via 24.

  A side wall 19 is formed on the side surface of the peripheral edge of the gate electrode 18, and silicide films 20a and 20b are respectively formed on the upper surface of the gate electrode 18 and the upper surface of the n + diffusion layer 16 and outside the side wall 19. Is formed.

  Here, as shown in FIG. 1, the position of the opening 17 c where the gate electrode 18 and the n + diffusion layer 16 are connected is from the contact 23 connecting the gate electrode 18 and the metal wiring 24 along the gate electrode 18. The route from the contact 23 to the opening 17 c is shorter than the route from the contact 23 to the first element region 14.

  FIG. 3 is a circuit diagram showing an equivalent circuit of the semiconductor device 10 of the present embodiment.

  The transistor 110 includes a source / drain region 13 provided in the first element region 14, a gate electrode 18, and a gate insulating film 17 a, and the diode 120 is formed on the second element region 15. It is constituted by a pn junction between the n + diffusion layer 16 and the substrate 11. A signal line 130 corresponding to the metal wiring 24 is connected to the gate of the transistor 110, and a diode 120 for supplying a substrate potential (ground potential) is connected in the middle of this connection. For this reason, when electrons are charged in the middle of the signal line 130 or the path from the signal line 130 to the gate of the transistor 110, the electrons can be discharged to the substrate 11.

Next, a method for manufacturing the semiconductor device 10 will be described with reference to the drawings.
4 and 5 are cross-sectional views showing the method for manufacturing the semiconductor device 10 of the present embodiment, and are cross-sectional views taken along the line AA ′ of the plan view shown in FIG.
As shown in FIG. 4A, an n + diffusion layer 16 is formed on the upper surface of the second element region 15 surrounded by the STI portion 12 on the substrate 11 by ion implantation. Next, as illustrated in FIG. 4B, a gate insulating film 17 b is deposited on the substrate 11. Next, as shown in FIG. 4C, an opening 17c is provided in the gate insulating film 17b on the n + diffusion layer 16 by a photolithography method and a dry etching method so that the n + diffusion layer 16 is exposed.

  Thereafter, as shown in FIG. 5A, a polysilicon film is formed on the substrate 11 and patterned by a photolithography method and a dry etching method to form the gate electrode 18. At this time, the gate electrode 18 and the n + diffusion layer 16 are connected by forming the extended portion 18a of the gate electrode 18 so as to cover the opening 17c and to be in contact with the exposed n + diffusion layer 16. Next, a side wall 19 made of silicon oxide or the like is formed on the side surface of the gate electrode 18, and silicide films 20 a and 20 b are formed in regions outside the side wall 19 on the upper surface of the gate electrode 18 and the upper surface of the n + diffusion layer 16. Form each one. In the source / drain region 13 of the first element region 14, an n− diffusion layer is formed by an ion implantation method after the formation of the gate electrode 18. Further, after the sidewall 19 is formed, the ion implantation method is also used. An n + diffusion layer is formed.

  Next, as shown in FIG. 5B, an interlayer insulating film 21 made of silicon oxide or the like is deposited on the substrate 11 by a CVD method to form a contact 23 connected to the extended portion 18a of the gate electrode 18. The contact hole 22 is formed by dry etching. Thereafter, as shown in FIG. 5C, a contact 23 is filled with a plug made of tungsten or the like to form a contact 23, and a metal film such as aluminum deposited on the interlayer insulating film 21 by a sputtering method is formed. Then, patterning is performed by photolithography and dry etching to form a metal wiring layer including the metal wiring 24 connected to the contact 23.

  Here, the dry etching in the step of forming the contact hole 22 and the step of forming the metal wiring 24 is performed by plasma etching. In the present embodiment, in the step of forming the contact 23 by filling the plug in the contact hole 22, the plug is filled by the plasma CVD method, and then etching back is performed by plasma etching to flatten the upper surface. For this reason, in the process of forming the contact hole 22 and the contact 23, electrons are charged in the extended portion 18a of the gate electrode 18, and in the process of forming the metal wiring 24, electrons are charged in the metal wiring 24.

  In the step of forming the contact hole 22 and the contact 23, as shown in FIG. 5B, since the gate electrode 18 is already connected to the n + diffusion layer 16, the extension portion 18a of the gate electrode 18 is charged. Electrons are emitted to the substrate 11 through a pn junction diode composed of the n + diffusion layer 16 and the substrate 11. Similarly, the electrons charged in the metal wiring 24 in the process of forming the metal wiring 24 pass through the contact 23, the extended portion 18 a of the gate electrode 18, and the pn junction diode composed of the n + diffusion layer 16 and the substrate 11. Through the substrate 11.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present embodiment, the following effects can be obtained.

  According to the present embodiment, the n + diffusion layer 16 that constitutes a pn junction diode together with the substrate 11 is provided on the substrate 11, and the extending portion 18 a of the gate electrode 18 is directly connected to the n + diffusion layer 16. That is, the metal wiring of the metal wiring layer is not interposed in the connection between the gate electrode 18 and the n + diffusion layer 16 as in the prior art. For this reason, electrons charged in the gate electrode 18 in the process before forming the metal wiring 24 such as the process of forming the contact hole 22 and the contact 23 can be emitted to the substrate 11.

  Furthermore, according to the present embodiment, the path from the contact 23 where the gate electrode 18 and the metal wiring 24 are connected to the opening 17 c connected to the n + diffusion layer 16 is from the contact 23 to the first element region 14. Since it is shorter than the route to reach, it is possible to suppress the electrons charged in the metal wiring 24 from reaching the first element region 14 and to discharge the electrons to the substrate 11 through the n + diffusion layer 16.

  Further, according to the present embodiment, the position of the opening 17c where the gate electrode 18 and the n + diffusion layer 16 are connected is the position along the gate electrode 18 from the contact 23 connecting the gate electrode 18 and the metal wiring 24. Since it is in the middle of the path toward the first element region 14, the electrons charged in the metal wiring 24 are prevented from reaching the first element region 14, and the electrons are emitted to the substrate 11 through the n + diffusion layer 16. Easy to do.

(Second Embodiment)
Hereinafter, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a plan view showing the semiconductor device of this embodiment. 7 and 8 are cross-sectional views showing the method of manufacturing the semiconductor device, and are cross-sectional views taken along the line AB of the plan view shown in FIG. Note that the equivalent circuit of the semiconductor device of the present embodiment is the same as the circuit shown in FIG.

  As shown in FIGS. 6 and 8B, an STI portion 12 as an element isolation portion is formed on the substrate 11 of the semiconductor device 10, and the first element region 14 surrounded by the STI portion 12. Includes a source / drain region 13 constituting a transistor. In the vicinity of the first element region 14, a second element region 15 that is also surrounded by the STI portion 12 is provided. An n + diffusion layer 16b is formed on the second element region 15, and the n + diffusion layer 16b and the substrate 11 constitute a pn junction diode.

  On the upper surface of the first element region 14, the second element region 15, and the STI portion 12 interposed between the two regions, a gate electrode 18 constituting a transistor is formed with gate insulating films 17a and 17b interposed therebetween. Yes. The gate electrode 18 includes a portion on the first element region 14 and an extending portion 18 a extending from the first element region 14, and the extending portion 18 a is a contact 23 penetrating the interlayer insulating film 21. Is connected to the metal wiring 24 formed in the upper layer. The transistor can be controlled by applying a control voltage to the gate electrode 18 through the metal wiring 24.

  A sidewall 19 is formed on the side surface of the peripheral edge of the gate electrode 18, and silicide films 20a and 20b are formed on the upper surfaces of the gate electrode 18 and the n + diffusion layer 16b, respectively.

  Here, the contact 23 is provided so as to protrude from the end of the extending portion 18a of the gate electrode 18, and the bottom surface of the contact 23 is in contact with the upper surface of the n + diffusion layer 16b (silicide film 20b). That is, the gate electrode 18, the n + diffusion layer 16 b, and the metal wiring 24 are connected via the contact 23.

Next, a method for manufacturing the semiconductor device 10 will be described with reference to the drawings.
As shown in FIG. 7A, a polysilicon film is formed on the substrate 11 having the first and second element regions 14 and 15 surrounded by the STI portion 12 with the gate insulating films 17a and 17b interposed therebetween. Then, this is patterned by a photolithography method and a dry etching method to form the gate electrode 18. Next, an impurity is introduced onto the second element region 15 by ion implantation to form an n− diffusion layer 16a, and then a side wall 19 made of silicon oxide or the like is formed on the side surface of the peripheral edge of the gate electrode 18. .

  Next, as shown in FIG. 7B, an impurity is introduced onto the second element region 15 by ion implantation to form an n + diffusion layer 16b, and on the upper surfaces of the gate electrode 18 and the n + diffusion layer 16b. Silicide films 20a and 20b are formed respectively. The n− diffusion layer and the n + diffusion layer are formed in the source / drain region 13 of the first element region 14 simultaneously with the second element region 15.

  Next, as shown in FIG. 8A, an interlayer insulating film 21 made of silicon oxide or the like is deposited on the substrate 11 by the CVD method. Further, both the extended portion 18a of the gate electrode 18 and the n + diffusion layer 16b are deposited. A contact hole 22 for forming a contact 23 connected to is formed by dry etching. Thereafter, as shown in FIG. 8B, a contact 23 is filled with a plug made of tungsten or the like to form a contact 23, and a metal film made of aluminum or the like deposited on the interlayer insulating film 21 by sputtering. Are patterned by a photolithography method and a dry etching method to form a metal wiring layer including the metal wiring 24 connected to the contact 23.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present embodiment, the following effects can be obtained.

  According to this embodiment, the substrate 11 includes the n + diffusion layer 16b that forms a pn junction diode together with the substrate 11, and the extension portion 18a of the gate electrode 18 is connected to the n + diffusion layer 16b via the contact 23. I am letting. That is, the metal wiring of the metal wiring layer is not interposed in the connection between the gate electrode 18 and the n + diffusion layer 16b as in the prior art. For this reason, electrons charged in the gate electrode 18 in a process before forming the metal wiring 24 such as a flattening process after the plug is buried in the contact hole 22 can be emitted to the substrate 11.

  Furthermore, according to the present embodiment, the gate electrode 18 and the n + diffusion layer 16b are connected via the contact 23 for connecting the gate electrode 18 and the metal wiring 24. That is, since the gate electrode 18, the metal wiring 24, and the n + diffusion layer 16b are connected by one contact 23, it is possible to reduce the space required for connecting each.

  Furthermore, according to the present embodiment, the n + diffusion layer 16b that constitutes the pn junction diode together with the substrate 11 is formed simultaneously with the diffusion layer in the source / drain region 13 of the transistor, so that the n + diffusion layer is formed in the second element region 15. It is not necessary to add a process only for forming 16b, and the manufacturing process can be simplified.

(Third embodiment)
Hereinafter, a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a plan view showing the semiconductor device of this embodiment, and FIG. 10 is a cross-sectional view taken along the line AB. Note that the equivalent circuit of the semiconductor device of the present embodiment is the same as the circuit shown in FIG.

  As shown in FIGS. 9 and 10, an STI portion 12 as an element isolation portion is formed on the substrate 11 of the semiconductor device 10. In the first element region 14 surrounded by the STI portion 12, A source / drain region 13 constituting a transistor is provided. In the vicinity of the first element region 14, a second element region 15 that is also surrounded by the STI portion 12 is provided. An n + diffusion layer 16b is formed on the second element region 15, and the n + diffusion layer 16b and the substrate 11 constitute a pn junction diode.

  On the upper surface of the first element region 14, the second element region 15, and the STI portion 12 interposed between the two regions, a gate electrode 18 constituting a transistor is formed with gate insulating films 17a and 17b interposed therebetween. Yes. The gate electrode 18 includes a portion on the first element region 14 and an extending portion 18a extending from the first element region 14, and the extending portion 18a is formed of the interlayer insulating film 21 (FIG. 12C). It is connected to the metal wiring 24 formed in the upper layer by the contact 23 penetrating through the reference). The transistor can be controlled by applying a control voltage to the gate electrode 18 through the metal wiring 24.

  Sidewalls 19 are formed on the side surfaces of the peripheral edge of the gate electrode 18 except for a part of the extended portion 18a (sidewall removal region) 19a. Further, a silicide film 20a as a conductor film is integrally formed on the upper surface of the gate electrode 18, the side surface of the gate electrode 18 in the sidewall removal region 19a, and the upper surface of the n + diffusion layer 16b in order to reduce the respective electric resistance. The gate electrode 18 and the n + diffusion layer 16b are connected by a silicide film 20a formed on the side surface of the gate electrode 18 in the sidewall removal region 19a.

  Here, as shown in FIG. 9, the position of the sidewall removal region 19 a where the gate electrode 18 and the n + diffusion layer 16 b are connected is from the contact 23 connecting the gate electrode 18 and the metal wiring 24 to the gate electrode 18. The path from the contact 23 to the sidewall removal region 19a is shorter than the path from the contact 23 to the first element region 14.

Next, a method for manufacturing the semiconductor device 10 will be described with reference to the drawings.
11 and 12 are cross-sectional views showing a method for manufacturing the semiconductor device 10 of the present embodiment, and are cross-sectional views taken along the line AA ′ of the plan view shown in FIG.
As shown in FIG. 11A, a polysilicon film is formed on the substrate 11 having the second element region 15 surrounded by the STI portion 12 with a gate insulating film 17b therebetween, and this is formed by photolithography. Then, patterning is performed by a dry etching method to form the gate electrode 18. Next, an impurity is introduced onto the second element region 15 by ion implantation to form an n− diffusion layer 16a, and then a side wall 19 made of silicon oxide or the like is formed on the side surface of the peripheral edge of the gate electrode 18. .

  Next, as shown in FIG. 11B, the sidewall 19 formed in the sidewall removal region 19a (see FIG. 9) in the peripheral portion of the gate electrode 18 is removed by a dry etching method, and the gate electrode 18 sides are exposed. Next, an impurity is introduced onto the second element region 15 by ion implantation to form an n + diffusion layer 16b. The n− diffusion layer and the n + diffusion layer are formed in the source / drain region 13 of the first element region 14 simultaneously with the second element region 15.

  Thereafter, as shown in FIG. 11C, after depositing a refractory metal film (for example, cobalt film) 20 on the substrate 11, the substrate 11 is heat-treated to silicidize the refractory metal film 20 to form a silicide film. Form. Next, when the refractory metal film 20 that has not been silicided is removed by wet processing, as shown in FIG. 12A, the upper surface of the gate electrode 18, the side surface of the gate electrode 18 in the sidewall removal region 19a, and n + A silicide film (cobalt silicide film) 20a remains integrally on the upper surface of the diffusion layer 16b.

  Next, as shown in FIG. 12B, an interlayer insulating film 21 made of silicon oxide or the like is deposited on the substrate 11 by a CVD method, and further, a contact 23 connected to the extending portion 18a of the gate electrode 18 is formed. A contact hole 22 is formed by dry etching. Thereafter, as shown in FIG. 12C, a contact 23 is filled with a plug made of tungsten or the like to form a contact 23, and a metal film made of aluminum or the like deposited on the interlayer insulating film 21 by sputtering. Are patterned by a photolithography method and a dry etching method to form a metal wiring layer including the metal wiring 24 connected to the contact 23.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present embodiment, the following effects can be obtained.

  According to this embodiment, the substrate 11 is provided with the n + diffusion layer 16b that forms a pn junction diode together with the substrate 11, and the gate electrode 18 and the n + diffusion layer 16b are connected to the top surface and the side surface of the gate electrode 18, and the n + diffusion. The layers are connected by an integral silicide film 20a covering the upper surface of the layer 16b. That is, the metal wiring of the metal wiring layer is not interposed in the connection between the gate electrode 18 and the n + diffusion layer 16b as in the prior art. For this reason, electrons charged in the gate electrode 18 in the process before forming the metal wiring 24 such as the process of forming the contact hole 22 and the contact 23 can be emitted to the substrate 11.

  Furthermore, according to the present embodiment, the path from the contact 23 where the gate electrode 18 and the metal wiring 24 are connected to the sidewall removal region 19a connected to the n + diffusion layer 16b is the contact from the contact 23 to the first element region. 14 is shorter than the route to 14, it is easy to suppress the electrons charged in the metal wiring 24 from reaching the first element region 14 and to emit the electrons to the substrate 11 through the n + diffusion layer 16 b. Become.

  Furthermore, according to the present embodiment, the position of the sidewall removal region 19a where the gate electrode 18 and the n + diffusion layer 16b are connected is from the contact 23 connecting the gate electrode 18 and the metal wiring 24 along the gate electrode 18. In the middle of the path toward the first element region 14, the electrons charged in the metal wiring 24 are prevented from reaching the first element region 14, and the electrons are transferred to the substrate 11 through the n + diffusion layer 16 b. Easy to release.

  Furthermore, according to the present embodiment, since the silicide film 20a is used as an integral conductor film covering the upper and side surfaces of the gate electrode 18 and the upper surface of the n + diffusion layer 16b, the conductor film is formed in a self-aligned manner. (Salicide) is possible, and the formation of the conductor film is facilitated.

  Furthermore, according to the present embodiment, the n + diffusion layer 16b that constitutes the pn junction diode together with the substrate 11 is formed simultaneously with the diffusion layer in the source / drain region 13 of the transistor, so that the n + diffusion layer is formed in the second element region 15. It is not necessary to add a process only for forming 16b, and the manufacturing process can be simplified.

(Fourth embodiment)
Hereinafter, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a plan view showing the semiconductor device of this embodiment, and FIG. 14 is a cross-sectional view taken along the line AB. Note that the equivalent circuit of the semiconductor device of the present embodiment is the same as the circuit shown in FIG.

  As shown in FIGS. 13 and 14, an STI portion 12 as an element isolation portion is formed on the substrate 11 of the semiconductor device 10, and the first element region 14 surrounded by the STI portion 12 includes A source / drain region 13 constituting a transistor is provided. In the vicinity of the first element region 14, a second element region 15 that is also surrounded by the STI portion 12 is provided. An n + diffusion layer 16b is formed on the second element region 15, and the n + diffusion layer 16b and the substrate 11 constitute a pn junction diode.

  On the upper surface of the first element region 14, the second element region 15, and the STI portion 12 interposed between the two regions, a gate electrode 18 constituting a transistor is formed with gate insulating films 17a and 17b interposed therebetween. Yes. The gate electrode 18 includes a portion on the first element region 14 and an extending portion 18a extending from the first element region 14. The extending portion 18a is formed of the interlayer insulating film 21 (FIG. 16C). It is connected to the metal wiring 24 formed in the upper layer by the contact 23 penetrating through the reference). The transistor can be controlled by applying a control voltage to the gate electrode 18 through the metal wiring 24.

  Sidewalls 19 are formed on the side surfaces of the peripheral edge of the gate electrode 18, and silicide films 20a and 20b as conductor films are formed on the upper surface of the gate electrode 18 and the upper surface of the n + diffusion layer 16b, respectively. . Further, a refractory metal film 20c as a conductor film is integrally formed with the silicide films 20a and 20b in a partial region (metal film remaining region) 19b on the outer surface of the sidewall 19, and the gate electrode 18 and the n + The diffusion layer 16b is connected by a refractory metal film 20c formed on the outer surface of the sidewall 19 on the metal film remaining region 19b.

  Here, as shown in FIG. 13, the position of the metal film remaining region 19 b where the gate electrode 18 and the n + diffusion layer 16 b are connected is from the contact 23 connecting the gate electrode 18 and the metal wiring 24 to the gate electrode 18. The path from the contact 23 to the metal film remaining region 19b is shorter than the path from the contact 23 to the first element region 14.

Next, a method for manufacturing the semiconductor device 10 will be described with reference to the drawings.
15 and 16 are cross-sectional views showing the method for manufacturing the semiconductor device 10 of this embodiment, and are cross-sectional views taken along the line AA ′ of the plan view shown in FIG.
As shown in FIG. 15A, a polysilicon film is formed on the substrate 11 having the second element region 15 surrounded by the STI portion 12 with a gate insulating film 17b therebetween, and this is formed by photolithography. Then, patterning is performed by a dry etching method to form the gate electrode 18. Next, an impurity is introduced onto the second element region 15 by an ion implantation method to form an n − diffusion layer 16a. Thereafter, a sidewall 19 made of silicon oxide or the like is formed on the side surface of the peripheral edge of the gate electrode 18, and an impurity is introduced onto the second element region 15 by ion implantation to form an n + diffusion layer 16b.

  Next, as shown in FIG. 15B, a refractory metal film (for example, cobalt film) 20 is deposited on the substrate 11, the substrate 11 is heat-treated, and the refractory metal film 20 is silicided to form a silicide film. Form. Thereafter, as shown in FIG. 15C, a masking layer (resist) 25 is formed on the outer surface of the sidewall 19 in the metal film remaining region 19b (see FIG. 13). Next, when the refractory metal film 20 that has not been silicided is removed by wet processing, silicide films 20a and 20b are formed on the upper surface of the gate electrode 18 and the upper surface of the n + diffusion layer 16b, as shown in FIG. While being formed, the refractory metal film 20c on the outer surface of the sidewall 19 in the metal film remaining region 19b remains integrally with the silicide films 20a and 20b. Thereafter, the masking layer 25 is removed by etching.

  Next, as shown in FIG. 16B, an interlayer insulating film 21 made of silicon oxide or the like is deposited on the substrate 11 by the CVD method, and further, a contact 23 connected to the extending portion 18a of the gate electrode 18 is formed. A contact hole 22 is formed by dry etching. Thereafter, as shown in FIG. 16C, a contact 23 is filled with a plug made of tungsten or the like to form a contact 23, and a metal film made of aluminum or the like deposited on the interlayer insulating film 21 by sputtering. Are patterned by a photolithography method and a dry etching method to form a metal wiring layer including the metal wiring 24 connected to the contact 23.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present embodiment, the following effects can be obtained.

  According to the present embodiment, the substrate 11 includes the n + diffusion layer 16b that constitutes a pn junction diode together with the substrate 11, and the gate electrode 18 and the n + diffusion layer 16b are connected to the upper surface of the gate electrode 18 and the sidewall 19. They are connected by an integral conductor film (silicide films 20a, 20b, refractory metal film 20c) covering the outer surface and the upper surface of the n + diffusion layer 16b. That is, the metal wiring of the metal wiring layer is not interposed in the connection between the gate electrode 18 and the n + diffusion layer 16b as in the prior art. For this reason, electrons charged in the gate electrode 18 in the process before forming the metal wiring 24 such as the process of forming the contact hole 22 and the contact 23 can be emitted to the substrate 11.

  Furthermore, according to the present embodiment, the path from the contact 23 where the gate electrode 18 and the metal wiring 24 are connected to the metal film remaining region 19b connected to the n + diffusion layer 16 is from the contact 23 to the first element region. Therefore, the electrons charged in the metal wiring 24 can be prevented from reaching the first element region 14 and can be easily emitted to the substrate 11 through the n + diffusion layer 16b. Become.

  Further, according to the present embodiment, the position of the metal film remaining region 19b where the gate electrode 18 and the n + diffusion layer 16b are connected is located along the gate electrode 18 from the contact 23 connecting the gate electrode 18 and the metal wiring 24. In the middle of the path toward the first element region 14, the electrons charged in the metal wiring 24 are prevented from reaching the first element region 14, and the electrons are transferred to the substrate 11 through the n + diffusion layer 16 b. Easy to release.

  Furthermore, according to the present embodiment, since the conductor film is formed on the outer surface of the sidewall 19, it is necessary to remove the sidewall 19 in order to form the conductor film connecting the gate electrode 18 and the n + diffusion layer 16b. There is no.

  Furthermore, according to the present embodiment, since the silicide films 20a and 20b are used as the conductor film covering the upper surface of the gate electrode 18 and the upper surface of the n + diffusion layer 16b in the integral conductor film, The conductor film on the upper surface and the upper surface of the n + diffusion layer 16b can be formed in a self-aligned manner (salicide), and the formation of the conductor film is facilitated.

  Furthermore, according to the present embodiment, the n + diffusion layer 16b that constitutes the pn junction diode together with the substrate 11 is formed simultaneously with the diffusion layer in the source / drain region 13 of the transistor, so that the n + diffusion layer is formed in the second element region 15. It is not necessary to add a process only for forming 16b, and the manufacturing process can be simplified.

(Fifth embodiment)
Hereinafter, a semiconductor device according to a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 17 is a plan view showing the semiconductor device of this embodiment, and FIG. 18 is a cross-sectional view taken along the line AB in FIG.

  In the semiconductor device 10 of this embodiment, a silicide film 20a is formed in the middle of a path from the contact 23 connected to the metal wiring 24 to the first element region 14 in a part of the extended portion 18a of the gate electrode 18. The configuration is the same as that of the first embodiment except that the high resistance region 26 is not provided. The high resistance region 26 is masked with a silicon oxide film or the like on the high resistance region 26 before depositing the refractory metal film 20 for forming the silicide film 20a on the gate electrode 18. Silicidation is inhibited, and the resistance is higher than that in the region where the silicide film 20a is formed.

  FIG. 19 is a circuit diagram showing an equivalent circuit of the semiconductor device 10. Between the transistor 110 and the pn junction diode 120, the resistor 140 by the high resistance region 26 is provided.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present embodiment, the following effects can be obtained in addition to the effects of the first embodiment.

  According to the semiconductor device of the present embodiment, a part of the extended portion 18 a of the gate electrode 18 is on the gate electrode 18 in the middle of the path from the contact 23 connected to the metal wiring 24 to the first element region 14. Since the high resistance region 26 having a higher resistance value than other regions is provided, the surge voltage applied to the gate electrode 18 on the first element region 14 by the electrons charged in the contact 23 and the metal wiring 24. The peak value of can be kept low.

  When a semiconductor device is provided with a resistor, a diffusion layer having an electric resistance of a predetermined resistance value is formed on the semiconductor substrate, or a long wiring is provided in the metal wiring layer or the gate electrode layer to use the wiring resistance. A method of forming a large number of contacts between the gate electrode layer and the metal wiring layer or between different metal wiring layers and utilizing the contact resistance can be considered. The resistance formed in this manner requires a relatively large area in itself or in a region for connection with a resistance such as a contact, and therefore the space efficiency is deteriorated.

  However, according to the semiconductor device of the present embodiment, since the high resistance region 26 is provided in the extending portion 18a of the gate electrode 18, the metal wiring only for connecting the gate electrode 18 and the high resistance region 26, There is no need to form a contact. Furthermore, since the high resistance region 26 has a high resistance value because no silicide film is formed on the upper surface, the high resistance region 26 has a stable resistance in a small area as compared with the resistance of a long wiring and a large number of contacts. It becomes possible.

(Modification)
In addition, you may change embodiment of this invention as follows.

  In the second embodiment, instead of forming the n + diffusion layer 16b on the second element region 15 simultaneously with the diffusion layer of the transistor formed in the first element region 14, Similarly, the n + diffusion layer 16 may be formed on the second element region 15 before the gate electrode 18 is formed.

  According to this, it becomes possible to extend the n + diffusion layer 16b on the upper surface of the second element region 15 also on the region overlapping the gate electrode 18. Therefore, when the contact hole 22 is formed, even if the sidewall 19 is eroded by the influence of etching, the n + diffusion layer 16b is formed on the upper surface of the second element region 15 when the semiconductor device 10 is operated. It is possible to suppress the leakage of current from the contact 23 in the region where no is formed. Alternatively, the same effect can be obtained even if the n + diffusion layer 16b is enlarged by introducing impurities again through the contact hole 22 after the contact hole 22 is formed.

  In the embodiment, LOCOS (Local Oxidation Of Silicon), planar LOCOS, or the like can be used instead of the STI structure as the element isolation portion. In the case where an SOI (Silicon On Insulator) substrate is used, the element isolation portion may be formed by mesa isolation.

  The semiconductor substrate is not limited to a p-type silicon substrate, but can be applied to an n-type silicon substrate.

1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line AB in FIG. 1. FIG. 3 is a circuit diagram showing an equivalent circuit of the semiconductor device of the first embodiment. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. The top view which shows the semiconductor device of 2nd Embodiment. (A), (b) is sectional drawing which shows the manufacturing method of the semiconductor device of 2nd Embodiment. (A), (b) is sectional drawing which shows the manufacturing method of the semiconductor device of 2nd Embodiment. The top view which shows the semiconductor device of 3rd Embodiment. FIG. 10 is a cross-sectional view taken along line AB in FIG. 9. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device of 3rd Embodiment. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device of 3rd Embodiment. The top view which shows the semiconductor device of 4th Embodiment. FIG. 14 is a cross-sectional view taken along line AB in FIG. 13. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device of 4th Embodiment. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device of 4th Embodiment. The top view which shows the semiconductor device of 5th Embodiment. FIG. 18 is a cross-sectional view taken along line AB of FIG. A circuit diagram showing an equivalent circuit of a semiconductor device of a 5th embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... p-type silicon substrate as a semiconductor substrate, 12 ... STI part as an element isolation | separation part, 13 ... Source / drain region which comprises a transistor, 14 ... 1st element region, 15 ... 2nd Element region, 16, 16b ... n + diffusion layer, 16a ... n- diffusion layer, 17a ... gate insulating film constituting transistor, 17c ... opening, 18 ... gate electrode constituting transistor, 18a ... extension portion, 19 ... Side wall, 19a ... Side wall removal region, 19b ... Metal film remaining region, 20, 20c ... High melting point metal film as conductor film, 20a, 20b ... Silicide film as conductor film, 21 ... Interlayer insulating film, 22 ... Contact Holes 23 ... Contacts 24 ... Metal wiring 25 ... Masking layer 26 ... High resistance region 110 ... Transistor 120 ... Diode , 130 ... signal line, 140 ... resistance.

Claims (18)

In a semiconductor device formed on a semiconductor substrate,
The semiconductor substrate comprising: a first element region in which a transistor is formed; and a second element region having a diffusion layer that forms a pn junction diode together with the semiconductor substrate;
A gate electrode formed on the first element region to which a control voltage for controlling the operation of the transistor is applied and extends from the first element region and is connected to the diffusion layer The gate electrode;
An interlayer insulating film formed on the gate electrode;
Provided in a metal wiring layer formed on the interlayer insulating film, metal wiring for applying the control voltage to the gate electrode,
A contact passing through the interlayer insulating film and connecting the gate electrode and the metal wiring;
And the gate electrode is connected to the diffusion layer between the metal wiring layer and the semiconductor substrate.   2. The semiconductor device according to claim 1, wherein the gate electrode extends from the first element region and covers the diffusion layer so as to be conductive.   2. The semiconductor device according to claim 1, wherein the gate electrode is connected to the diffusion layer through the contact.   2. The semiconductor device according to claim 1, wherein an integral conductor film is formed to cover an upper surface and a side surface of the gate electrode and an upper surface of the diffusion layer, and the gate electrode is connected to the diffusion layer by the conductor film. A semiconductor device characterized by that.   2. The semiconductor device according to claim 1, further comprising: a sidewall made of an insulating material on a side surface of the gate electrode; and an upper surface of the gate electrode, an outer surface of the sidewall, and an upper surface of the diffusion layer. An integrated conductor film for covering is formed, and the gate electrode is connected to the diffusion layer through the conductor film.   6. The semiconductor device according to claim 1, wherein a path from a portion where the gate electrode is connected to the metal wiring to a portion where the gate electrode is connected to the diffusion layer is the gate electrode is the metal wiring. A semiconductor device characterized by being shorter than a path from a portion connected to the first element region to the first element region.   7. The semiconductor device according to claim 6, wherein the gate electrode is connected to the diffusion layer in the middle of a path from a portion connected to the metal wiring to the first element region. Semiconductor device.   8. The semiconductor device according to claim 1, wherein another gate on the gate electrode is disposed in the middle of a path from the portion where the gate electrode is connected to the metal wiring to the first element region. A semiconductor device comprising a high resistance region having a resistance value higher than that of the region.   9. The semiconductor device according to claim 8, wherein the gate electrode is formed of polysilicon having a silicide film formed on an upper surface thereof, and the high resistance region extends from the first element region of the gate electrode. And a high resistance value because no silicide film is formed on the upper surface. A manufacturing method for manufacturing the semiconductor device according to claim 2,
Forming the diffusion layer;
Forming the gate electrode such that a portion of the gate electrode covers the diffusion layer in a conductive manner;
Forming the interlayer insulating film;
Forming the contact;
Forming the metal wiring;
A method for manufacturing a semiconductor device, comprising: A manufacturing method for manufacturing the semiconductor device according to claim 3,
In the semiconductor substrate on which the diffusion layer and the gate electrode are formed,
Forming the interlayer insulating film;
Forming the contact connectable to both the gate electrode and the diffusion layer in the interlayer insulating film;
Forming the metal wiring;
A method for manufacturing a semiconductor device, comprising: A manufacturing method for manufacturing the semiconductor device according to claim 4,
In the semiconductor substrate on which the diffusion layer and the gate electrode are formed,
Forming an integral conductor film covering the top and side surfaces of the gate electrode and the top surface of the diffusion layer;
Forming the interlayer insulating film;
Forming the contact;
Forming the metal wiring;
A method for manufacturing a semiconductor device, comprising:   13. The method of manufacturing a semiconductor device according to claim 12, wherein the conductor film is a silicide film. A manufacturing method for manufacturing the semiconductor device according to claim 5,
In the semiconductor substrate on which the diffusion layer and the gate electrode are formed,
Forming the sidewall;
Forming an integral conductor film covering the upper surface of the gate electrode, the outer surface of the sidewall, and the upper surface of the diffusion layer;
Forming the interlayer insulating film;
Forming the contact;
Forming the metal wiring;
A method for manufacturing a semiconductor device, comprising: 15. The method of manufacturing a semiconductor device according to claim 14, wherein the step of forming an integral conductor film covering the upper surface of the gate electrode, the outer surface of the sidewall, and the upper surface of the diffusion layer comprises:
Forming a metal film on the diffusion layer and the gate electrode;
Heat treating the semiconductor substrate to react the metal film and forming a silicide film on the upper surface of the gate electrode and the upper surface of the diffusion layer;
Forming a masking layer on the metal film formed on the outer surface of the sidewall;
Removing the metal film at a portion where the masking layer is not formed;
Removing the masking layer;
A method for manufacturing a semiconductor device, comprising:   16. The method of manufacturing a semiconductor device according to claim 11, wherein the diffusion layer is formed simultaneously with the diffusion layer of the transistor after the gate electrode is formed. Method. On the semiconductor substrate,
A transistor,
A diffusion layer constituting a pn junction diode together with the semiconductor substrate;
A gate electrode to which a control signal for controlling the operation of the transistor is applied;
An interlayer insulating film formed on the gate electrode;
Metal wiring formed on the interlayer insulating film;
A contact passing through the interlayer insulating film and connecting the gate electrode and the metal wiring;
A method for manufacturing a semiconductor device comprising:
A method for manufacturing a semiconductor device, comprising the step of connecting the gate electrode and the diffusion layer before the step of forming the metal wiring. A method of manufacturing a semiconductor device formed on a semiconductor substrate,
In the semiconductor substrate comprising: a first element region in which a transistor is formed; and a second element region in which a diffusion layer forming a pn junction diode is formed together with the semiconductor substrate.
Forming the diffusion layer;
Forming a gate electrode extending from the first element region to the second element region and covering the diffusion layer in a conductive manner;
Forming an interlayer insulating film on the top surface of the gate electrode;
Forming a contact connected to the gate electrode in the interlayer insulating film;
Forming a metal wiring connected to the contact on the upper surface of the interlayer insulating film;
A method for manufacturing a semiconductor device, comprising:

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