JP2005338777A - Display device and electronic appliance - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low power consumption display device and an electronic appliances capable of decreasing power consumption. <P>SOLUTION: The display device of the invention comprises a pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver. Each of the plurality of pixels includes a light emitting element, a first transistor for controlling a video signal input to the pixel, a second transistor for controlling emission/non-emission of the light emitting element, and a capacity element holding the video signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a display device including a self-luminous element, a driving method thereof, and a television device. The present invention also relates to an element substrate in which elements are provided on an insulating surface. Further, the present invention relates to a source driver and a gate driver including a plurality of elements.

The present invention also relates to an electronic device using a display device including a light emitting element.

In recent years, the development of display devices including light emitting elements typified by EL (Electro Luminescence) elements has been promoted, and a wide range of uses is expected by taking advantage of self-luminous type such as high image quality, wide viewing angle, thinness, and light weight. Has been. Since a light-emitting element has a property in which luminance is proportional to a current value, there is a display device that employs constant-current driving in which a constant current is supplied to the light-emitting element in order to accurately represent gradation (Patent Document 1). reference).
JP 2003-323159 A

Electronic devices equipped with a display function such as an information terminal and a mobile phone are widely used. However, many of such electronic devices use a battery, and reduction of power consumption is an issue. However, when the constant current driving is employed as in the display device described in Patent Document 1, the driving transistor connected in series with the light emitting element must be operated in the saturation region, and thus the driving voltage needs to be increased. There is no reduction in power consumption. Therefore, an object of the present invention is to provide a display device that can reduce power consumption and a driving method thereof.

The display device of the present invention includes a pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver. Each of the plurality of pixels includes a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and a capacitor element that holds a video signal. Have

The gate electrode of the first transistor is connected to the first gate driver and the second gate driver through the gate line. One of the source electrode and the drain electrode of the first transistor is connected to the source driver through the source line. The other of the source electrode and the drain electrode of the first transistor is connected to the gate electrode of the second transistor. One of the source electrode and the drain electrode of the second transistor is connected to the pixel electrode of the light-emitting element. The other of the source electrode and the drain electrode of the second transistor is connected to a power source.

The present invention having the above configuration realizes a high aperture ratio because only two transistors are arranged in a pixel. When a high aperture ratio is realized, the luminance of the light-emitting element can be lowered with an increase in the light emitting area. Accordingly, the driving voltage of the light emitting element can be lowered to reduce power consumption.

The display device of the present invention employs constant voltage driving in which a constant voltage is applied to the light emitting element. In the constant voltage driving, it is not necessary to operate the driving transistor in the saturation region, and it is not necessary to increase the driving voltage. Therefore, power consumption can be reduced as compared with the constant current driving.

The capacitor includes a semiconductor layer provided in the same layer as a semiconductor layer included in the first transistor and the second transistor, and a conductive layer provided in the same layer as a gate electrode included in the first transistor and the second transistor. And an insulating layer provided between the semiconductor layer and the conductive layer. The capacitor is connected to the first conductive layer provided in the same layer as the gate electrode included in the first transistor and the second transistor, and the source electrode or the drain electrode of the first transistor and the second transistor. Including a second conductive layer provided in the same layer as a conductive layer (corresponding to a source wiring or a drain wiring) and an insulating layer provided between the first conductive layer and the second conductive layer. Features.

In the present invention having the above structure, since the capacitor element is provided below the source wiring or the drain wiring, the area of one pixel can be used effectively, and the aperture ratio does not decrease due to the arrangement of the capacitor element.

In addition, a thickness of a conductive layer (corresponding to a source wiring or a drain wiring) connected to a source electrode or a drain electrode of the first transistor and the second transistor is 500 nm to 1300 nm.

In addition, the light-emitting element includes a first insulating layer provided over the first transistor and the second transistor, and a second insulating layer in contact with the first insulating layer. The light-emitting element is formed over the second insulating layer. The 1st electrode which is included is provided, It is characterized by the above-mentioned.

In addition, the partition layer (insulating layer) that covers the end portion of the first electrode included in the light-emitting element has a column-direction width of 10 to 25 μm. It is characterized by that. In addition, a partition layer (insulating layer) covering an end portion of the first electrode included in the light-emitting element is provided, and the partition layer (insulating layer) has a light-shielding property.

One of the first electrode and the second electrode of the light-emitting element is reflective, and the other is light-transmitting. In addition, the first electrode and the second electrode of the light-emitting element have a light-transmitting property.

The display device of the present invention includes a power supply control circuit that changes potentials of the first power supply and the second power supply so that a reverse bias can be applied to the light emitting element.

The display device of the present invention includes a monitor circuit that operates based on an ambient temperature, and a power supply control circuit that changes a power supply potential supplied to a pixel region based on an output of the monitor circuit. The monitor circuit includes a monitor light emitting element.

A source driver included in the display device of the present invention includes a pulse output circuit, a latch, and a selection circuit, and a first protection circuit connected to an input node of the pulse output circuit, and between the pulse output circuit and the latch A second protection circuit is provided, and a third protection circuit is provided between the selection circuit and the pixel region.

Each of the first gate driver and the second gate driver included in the display device of the present invention includes a pulse output circuit and a selection circuit, and a first protection circuit connected to an input node of the pulse output circuit; And a second protection circuit provided between the selection circuit and the pixel region.

The protection circuit is one or more types selected from a resistor element, a capacitor element, and a rectifier element. The rectifying element is a transistor or a diode in which a gate electrode and a drain electrode are connected. The pulse output circuit is a plurality of flip-flop circuits or decoder circuits.

The light-emitting element includes a material that emits red light from a triplet excited state, a material that emits green light from a singlet excited state, or a material that emits blue light from a singlet excited state. Alternatively, the light-emitting element includes a material that emits red light from a triplet excited state, a material that emits green light from a triplet excited state, or a material that emits blue light from a singlet excited state. . By using a material that emits light from a triplet excited state with high emission efficiency, power consumption can be reduced.

In the pixel region included in the display device of the present invention, a plurality of power supply lines connected to the first power supply are provided in the column direction, and the power supply lines are shared between adjacent pixels.

The present invention provides an element substrate in a state where the pixel electrode of the light emitting element is formed in the display device having the above-described configuration. More specifically, the element substrate is a state in which a transistor and a pixel electrode connected to the transistor are formed on an insulating surface, and corresponds to a state in which an electroluminescent layer and a counter electrode are not formed.

The display device of the present invention operates as follows. One frame period has a plurality of subframe periods SF1, SF2,..., SFn (n is a natural number), and each of the plurality of subframe periods includes a plurality of write periods Ta1, Ta2,. One selected from a plurality of lighting periods Ts1, Ts2,..., Tsn, each of the plurality of writing periods having a plurality of gate selection periods, and a plurality of gate selection periods. each has a plurality of sub-gate selection period, the length of the plurality of lighting periods Ts1: Ts2: ···: Tsn = 2 (n-1): 2 (n-2): ···: 2 0 And the order of appearance of the plurality of lighting periods is random.

Alternatively, one or more periods selected from the plurality of subframe periods are divided into a plurality of parts, each of the divided one or more subframe periods, and one or more subframe periods that are not divided Each has one selected from a plurality of writing periods Ta1, Ta2,..., Tam (m is a natural number) and one selected from a plurality of lighting periods Ts1, Ts2,. Each of the plurality of writing periods has a plurality of gate selection periods, and each of the plurality of gate selection periods has a plurality of sub-gate selection periods.

Alternatively, one or more periods selected from the plurality of subframe periods are divided into a plurality of parts, each of the divided one or more subframe periods, and one or more subframe periods that are not divided Each has one selected from a plurality of writing periods Ta1, Ta2,..., Tam (m is a natural number) and one selected from a plurality of lighting periods Ts1, Ts2,. Each of the plurality of writing periods has a plurality of gate selection periods, each of the plurality of gate selection periods has a plurality of sub-gate selection periods, and the order in which the plurality of lighting periods appear is random And

In one period selected from the plurality of sub-gate selection periods, the gate line is selected by one of the first gate driver and the second gate driver, and in one period selected from the plurality of sub-gate selection periods, A gate line is selected by the other of the first gate driver and the second gate driver, and the light-emitting element emits light or does not emit light based on a video signal input to the gate electrode of the second transistor. .

  Note that in the present invention, applicable transistor types are not limited, and a thin film transistor (TFT) using a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a semiconductor substrate, or an SOI substrate is used. A MOS transistor, a junction transistor, a bipolar transistor, a transistor using an organic semiconductor or a carbon nanotube, and other transistors can be applied. There is no limitation on the kind of the substrate over which the transistor is provided, and the transistor can be provided over a single crystal substrate, an SOI substrate, a glass substrate, or the like.

In the present invention, being connected is synonymous with being electrically connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, another element (for example, another element or a switch) that enables electrical connection may be disposed therebetween.

Further, a capacitor element in a pixel or the like can be substituted by a gate capacitor such as a transistor. In that case, the capacitive element can be omitted.

The switch may be an electrical switch or a mechanical switch. Any switch can be used as long as it can control the flow of current. It may be a transistor, a diode, or a logic circuit combining them. Therefore, when a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desirable that the off-state current is small, it is desirable to use a transistor having a polarity with a small off-state current. As a transistor with low off-state current, there is a transistor provided with an LDD region. In addition, when the transistor operated as a switch operates at a source terminal potential close to a low potential side power supply (VSS, Vgnd, 0 V, etc.), the n-channel type is used. On the contrary, the source terminal potential is a high potential. When operating in a state close to a side power supply (VDD or the like), it is desirable to use a p-channel type. This is because the absolute value of the voltage between the gate and the source can be increased, so that it can easily operate as a switch. Note that a CMOS switch may be formed using both an n-channel type and a p-channel type.

In the present invention using the constant voltage driving, the driving voltage of the light emitting element can be lowered as compared with the case of using the constant current driving, so that power consumption can be reduced.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
The configuration of the display device of the present invention will be described with reference to FIGS. The display device of the present invention includes a plurality of elements in a region where the source line Sx (x is a natural number, 1 ≦ x ≦ m) and the gate line Gy (y is a natural number, 1 ≦ y ≦ n) intersect via an insulator. The pixel 10 including a plurality of pixels is included (see FIG. 1A). The pixel 10 includes a light emitting element 13, a capacitor element 16, and two transistors. Of the two transistors, one is a switching transistor 11 (hereinafter sometimes referred to as TFT 11) that controls the input of a video signal to the pixel 10, and the other controls light emission and non-light emission of the light emitting element 13. This is a driving transistor 12 (hereinafter sometimes referred to as TFT 12). The TFTs 11 and 12 are field effect transistors and have three terminals of a gate electrode, a source electrode, and a drain electrode.

The gate electrode of the TFT 11 is connected to the gate line Gy, one of the source electrode and the drain electrode is connected to the source line Sx, and the other is connected to the gate electrode of the TFT 12. One of the source electrode and the drain electrode of the TFT 12 is connected to the first power supply 17 through the power supply line Vx (x is a natural number, 1 ≦ x ≦ m), and the other is connected to the pixel electrode of the light emitting element 13. The counter electrode of the light emitting element 13 is connected to the second power source 18 through a power line. The capacitive element 16 is provided between the gate electrode and the source electrode of the TFT 12. The conductivity types of the TFTs 11 and 12 are not limited, and may be either N-type or P-type. However, in the illustrated configuration, the TFT 11 is N-type and the TFT 12 is P-type. The potential of the first power supply 17 and the potential of the second power supply 18 are not particularly limited, but are set to different potentials so that a forward bias voltage or a reverse bias voltage is applied to the light emitting element 13.

The power supply line Vx connected to the first power supply 17 and the power supply line connected to the second power supply 18 are kept at a constant potential.

The display device of the present invention having the above structure is characterized in that the number of transistors arranged in the pixel 10 is two. With the above feature, the number of transistors laid out in one pixel 10 is reduced, and the number of transistors is small, so that the number of wirings inevitably arranged can be reduced, so that a high aperture ratio and high definition are achieved. Realize high yield. In addition, when a high aperture ratio is realized, the luminance of the light-emitting element can be lowered with an increase in the area that emits light. That is, the current density can be lowered. Accordingly, the driving voltage can be lowered, so that power consumption can be reduced. Further, the reliability can be improved by reducing the drive voltage.

The semiconductor constituting the TFTs 11 and 12 may be any of an amorphous semiconductor (amorphous silicon), a microcrystalline semiconductor, a polycrystalline semiconductor (polysilicon), an organic semiconductor, and the like. The microcrystalline semiconductor is formed by using silane gas (SiH ₄ ) and fluorine gas (F ₂ ), by using silane gas and hydrogen gas, or after forming a thin film by using the gas mentioned above, You may form by irradiating.

The gate electrodes of the TFTs 11 and 12 are formed of a single layer or a stacked layer using a conductive material. For example, a stacked structure of tungsten (W) and tungsten nitride (WN, composition ratio of tungsten (W) and nitrogen (N) is not limited), or a stacked structure of molybdenum (Mo), aluminum (Al), and molybdenum (Mo) A laminated structure of molybdenum (Mo) and molybdenum nitride (MoN, the composition ratio of molybdenum (Mo) and nitrogen (N) is not limited) may be employed.

A conductive layer (corresponding to a source wiring or a drain wiring) connected to an impurity region (source electrode and drain electrode) included in the TFTs 11 and 12 is formed of a single layer or a stacked layer using a conductive material. For example, titanium (Ti), aluminum silicon (Al-Si, aluminum (Al) to which silicon (Si) is added), a laminated structure of titanium (Ti), molybdenum (Mo), aluminum-silicon (Al-Si, silicon) Laminated structure of (Si) -added aluminum (Al)) and molybdenum (Mo), molybdenum nitride (MoN, composition ratio of molybdenum (Mo) and nitrogen (N) is not limited), aluminum-silicon (Al-Si) In addition, a stacked structure of aluminum (Al) to which silicon (Si) is added and molybdenum nitride (MoN, the composition ratio of molybdenum (Mo) and nitrogen (N) is not limited) may be employed.

Next, FIG. 2 shows a layout of the pixel 10 having the above configuration. In this layout, the conductive layers 19 corresponding to the pixel electrodes of the TFTs 11 and 12, the capacitor element 16, and the light emitting element 13 are shown. Next, FIG. 1B shows a cross-sectional structure corresponding to ABC in this layout. TFTs 11 and 12, a light emitting element 13, and a capacitor element 16 are provided on a substrate 20 having an insulating surface such as glass or quartz.

The light emitting element 13 corresponds to a stacked body of a conductive layer 19 corresponding to a pixel electrode, an electroluminescent layer 33, and a conductive layer 34 corresponding to a counter electrode. When both the conductive layers 19 and 34 have translucency, the light emitting element 13 emits light in a direction toward the conductive layer 19 and in a direction toward the conductive layer 34. That is, the light emitting element 13 performs double-sided emission. When one of the conductive layers 19 and 34 has a light-transmitting property and the other has a light-blocking property, the light-emitting element 13 emits light only in the direction toward the conductive layer 19 or in the direction toward the conductive layer 34. That is, the light emitting element 13 performs top emission or bottom emission. FIG. 1B shows a cross-sectional structure in the case where the light emitting element 13 performs bottom emission.

The capacitive element 16 is disposed between the gate electrode and the source electrode of the TFT 12 and holds the gate-source voltage of the TFT 12. The capacitive element 16 includes a semiconductor layer 21 provided in the same layer as the semiconductor layer included in the TFTs 11 and 12, and conductive layers 22a and 22b provided in the same layer as the gate electrodes of the TFTs 11 and 12 (hereinafter collectively referred to as the conductive layer 22). And a capacitor is formed by an insulating layer between the semiconductor layer 21 and the conductive layer 22.

Note that the semiconductor layer of the TFT 11, the semiconductor layer of the TFT 12, and the semiconductor layer 21 of the capacitor 16 are provided on the same base insulating layer.

The capacitive element 16 includes a conductive layer 22 provided in the same layer as the gate electrodes of the TFTs 11 and 12, and conductive layers (corresponding to source wirings or drain wirings) 24 to 27 connected to the source electrodes or drain electrodes of the TFTs 11 and 12. The capacitor is formed by the conductive layer 23 provided in the same layer as the first layer and the insulating layer between the conductive layer 22 and the conductive layer 23.
With the above characteristics, the capacitor 16 can obtain a capacitance value sufficient to hold the gate-source voltage of the TFT 12. In addition, the capacitive element 16 is provided below the conductive layer constituting the power supply line, and therefore, the aperture ratio is not reduced by the arrangement of the capacitive element 16.

The conductive layers 24 to 27 and the conductive layer 23 corresponding to the source wiring or drain wiring of the TFTs 11 and 12 have a thickness of 500 nm to 2000 nm, preferably 500 nm to 1300 nm. Since the conductive layers 23 to 27 constitute the source line Sx and the power supply line Vx, the influence of the voltage drop can be suppressed by increasing the film thickness of the conductive layers 23 to 27 as described above. it can. If the conductive layers 23 to 27 are thickened, the wiring resistance can be reduced. Conversely, if the conductive layers 23 to 27 are too thick, it becomes difficult to perform pattern processing accurately, or the surface is uneven. Becomes a problem. That is, the thickness of the conductive layers 23 to 27 is preferably determined within the above range in consideration of the wiring resistance, the ease of pattern processing, and the influence of surface irregularities.

In addition, it has insulating layers 28 and 29 (hereinafter collectively referred to as the first insulating layer 30) covering the TFTs 11 and 12, and a second insulating layer 31 provided on the first insulating layer 30, A feature is that a conductive layer 19 corresponding to a pixel electrode is provided over the second insulating layer 31. If the second insulating layer 31 is not provided, the conductive layers 24 to 27 corresponding to the source wiring or the drain wiring and the conductive layer 23 are provided in the same layer as the conductive layer 19. Then, the region where the conductive layer 19 is provided is restricted to a region other than the region where the conductive layers 23 to 27 are provided. However, by providing the second insulating layer 31, the margin of the region where the conductive layer 19 is provided is widened, and a high aperture ratio is realized. In the case of top emission, this configuration is particularly effective. When a high aperture ratio is realized, the driving voltage can be lowered and the power consumption can be reduced as the area for emitting light increases.

Note that the first insulating layer 30 and the second insulating layer 31 are formed using an inorganic material such as silicon oxide or silicon nitride, an organic material such as polyimide or acrylic, or the like. The first insulating layer 30 and the second insulating layer 31 may be formed of the same material, or may be formed of different materials. Further, as a material for forming the first insulating layer 30 and the second insulating layer 31, a siloxane-based material may be used. For example, a skeleton structure is formed by a bond of silicon and oxygen, and at least a substituent has One in which an organic group containing hydrogen (for example, an alkyl group or aromatic hydrocarbon) is used, or one in which a skeleton structure is formed by a bond between silicon and oxygen and a fluoro group is used as a substituent, or silicon and oxygen And an organic group containing at least hydrogen and a fluoro group are used as a substituent.

In addition, a partition layer 32 (also referred to as a bank, a bank, or an insulating layer) is provided between the pixels 10, and the width 35 of the partition layer 32 on the capacitor 16 can hide a wiring provided therebelow. Any width can be used. Specifically, the width 35 is 7.5 to 27.5 μm, preferably 10 to 25 μm (see FIG. 3). Thus, a high aperture ratio is realized by narrowing the width of the partition wall layer 32. When a high aperture ratio is realized, the driving voltage can be lowered and the power consumption can be reduced as the area for emitting light increases.

Note that, according to the illustrated layout, the aperture ratio of the pixel is about 50%. The length in the column direction (vertical direction) of the pixel 10 of the layout shown in the drawing is indicated by a width 38, and the length in the row direction (lateral direction) is indicated by a width 37. The partition layer 32 may be formed using either an inorganic material or an organic material. However, since the electroluminescent layer is provided so as to be in contact with the partition layer 32, it is preferable to have a shape in which the radius of curvature continuously changes so that no pinhole or the like is generated in the electroluminescent layer.

Further, the partition layer 32 is characterized in that it has a light shielding property. Due to the above characteristics, the outline between the pixels 10 becomes clear, and a high-definition image can be displayed. The partition wall layer 32 includes pigments and carbon nanotubes, and is colored with additives such as these pigments and carbon, and therefore has a light shielding property.

The display device of the present invention includes a pixel region 40 in which a plurality of the pixels 10 described above are arranged in a matrix, a first gate driver 41, a second gate driver 42, and a source driver 43 (see FIG. 4). The first gate driver 41 and the second gate driver 42 are disposed so as to face each other with the pixel region 40 interposed therebetween, or are disposed in one of the upper, lower, left, and right sides of the pixel region 40.

The source driver 43 includes a pulse output circuit 44, a latch 45, and a selection circuit 46. The latch 45 has a first latch 47 and a second latch 48. The selection circuit 46 includes a transistor 49 (hereinafter referred to as TFT 49) and an analog switch 50. The TFT 49 and the analog switch 50 are provided in each column corresponding to the source line Sx. The inverter 51 is for generating an inverted signal of the WE signal (Write Erase), and may not be provided when an inverted signal of the WE signal is supplied from the outside.

The gate electrode of the TFT 49 is connected to the selection signal line 52, one of the source electrode and the drain electrode is connected to the source line Sx, and the other is connected to the power source 53. The analog switch 50 is provided between the second latch 48 and the source line Sx. That is, the input node of the analog switch 50 is connected to the second latch 48, and the output node is connected to the source line Sx. One of the two control nodes of the analog switch 50 is connected to the selection signal line 52, and the other is connected to the selection signal line 52 via the inverter 51. The potential of the power source 53 is a potential for turning off the TFT 12 included in the pixel 10. When the TFT 12 is N-type, the potential of the power source 53 is L level, and when the TFT 12 is P-type, the potential of the power source 53 is H level. To do.

The first gate driver 41 has a pulse output circuit 54 and a selection circuit 55. The second gate driver 42 has a pulse output circuit 56 and a selection circuit 57. The selection circuits 55 and 57 are connected to the selection signal line 52. However, the selection circuit 57 included in the second gate driver 42 is connected to the selection signal line 52 via the inverter 58. That is, the WE signals input to the selection circuits 55 and 57 via the selection signal line 52 are in an inverted relationship with each other.

Each of the selection circuits 55 and 57 has a tristate buffer. The input node of the tristate buffer is connected to the pulse output circuit 54 or the pulse output circuit 56, and the control node is connected to the selection signal line 52. The output node of the tristate buffer is connected to the gate line Gy. The tri-state buffer is in an operating state when a signal transmitted from the selection signal line 52 is at an H level, and is in an indefinite state when the signal is at an L level.

The indefinite state is a state opposite to the operating state.

A pulse output circuit 44 included in the source driver 43, a pulse output circuit 54 included in the first gate driver 41, and a pulse output circuit 56 included in the second gate driver 42 are used as a shift register or a decoder circuit including a plurality of flip-flop circuits. Equivalent to. If a decoder circuit is applied as the pulse output circuits 44, 54 and 56, the source line Sx or the gate line Gy can be selected at random. If the source line Sx or the gate line Gy can be selected at random, it is possible to suppress the generation of a pseudo contour that occurs when the time gray scale method is applied.

The configuration of the source driver 43 is not limited to the above description, and a level shifter and a buffer may be provided. The configurations of the first gate driver 41 and the second gate driver 42 are not limited to the above description, and a level shifter or a buffer may be provided. Although not described above, the source driver 43, the first gate driver 41, and the second gate driver 42 include a protection circuit. The configuration of the driver having the protection circuit will be described later in a third embodiment.

Thus, the n-th stage output (n is a natural number) of the first gate driver 41 and the n-th stage output of the second gate driver 42 control the n-th gate line. A selection circuit for controlling signal output is provided at the output terminals of the first gate driver 41 and the second gate driver 42. One of the first gate driver 41 and the second gate driver 42 is a gate driver that selects a pixel row to which a video signal is written, and the other is a pixel row that erases a signal written to the pixel. It is a gate driver to select.

The display device of the present invention includes a power supply control circuit 63. The power supply control circuit 63 includes a power supply circuit 61 that supplies power to the light emitting element 13 and a controller 62. The power supply circuit 61 is connected to the pixel electrode of the light emitting element 13 through the TFT 12 and the power supply line Vx. The power supply circuit 61 is connected to the counter electrode of the light emitting element 13 through a power supply line.

When a forward bias voltage is applied to the light emitting element 13 and a current is caused to flow through the light emitting element 13 to emit light, the potential of the first power supply 17 becomes higher than the potential of the second power supply 18. A potential difference between the first power supply 17 and the second power supply 18 is set.

On the other hand, when a reverse bias voltage is applied to the light emitting element 13, the first power supply 17 and the second power supply are set so that the potential of the first power supply 17 is lower than the potential of the second power supply 18. 18 potentials are set. Such setting of the power supply potential is performed by supplying a predetermined signal from the controller 62 to the power supply circuit 61.

In the present invention, by applying a reverse bias voltage to the light emitting element 13 using the power supply control circuit 63, deterioration with time of the light emitting element 13 can be suppressed and reliability can be improved. In addition, the light emitting element 13 may have an initial failure in which the anode and the cathode are short-circuited due to adhesion of foreign matters, pinholes due to fine protrusions on the anode or the cathode, and non-uniformity of the electroluminescent layer. When such an initial failure occurs, the pixel is not turned on or off according to the signal, and almost all of the current flows through the short-circuited portion of the anode and the cathode, causing the phenomenon that the entire element is extinguished, or a specific pixel There is a problem that the image is not displayed satisfactorily due to a phenomenon that does not light or not light. However, according to the configuration of the present invention, since a reverse bias can be applied to the light emitting element, a current is supplied locally only to the short-circuited portion of the anode and the cathode, and the short-circuited portion is heated. It can be insulated by oxidation or carbonization. As a result, even if an initial failure occurs, the failure can be resolved and an image can be displayed favorably. It should be noted that such initial failure insulation is preferably performed before shipment. In addition to the initial failure, a new short circuit between the anode and the cathode may occur over time. Such a defect is also called a progressive defect, but according to the configuration of the present invention, a reverse bias can be periodically applied to the light emitting element, so even if a progressive defect occurs, the defect is eliminated, An image can be displayed satisfactorily. Note that there is no particular limitation on the timing at which the reverse bias voltage is applied to the light emitting element 13.

The display device of the present invention includes a monitor circuit 64 and a control circuit 65. The monitor circuit 64 operates based on the ambient temperature (hereinafter referred to as environmental temperature). The control circuit 65 has a constant current source and a buffer. In the configuration shown in the figure, the monitor circuit 64 includes a monitor light emitting element 66 (hereinafter sometimes referred to as a light emitting element 66).

The control circuit 65 supplies a signal for changing the power supply potential to the power supply control circuit 63 based on the output of the monitor circuit 64. The power supply control circuit 63 changes the power supply potential supplied to the pixel region 40 based on the signal supplied from the control circuit 65. The present invention having the above-described configuration can improve the reliability by suppressing the fluctuation of the current value caused by the change in the environmental temperature. Detailed configurations of the monitor circuit 64 and the control circuit 65 will be described later in a fourth embodiment.

In the display device of the present invention which performs constant voltage driving, when the luminance of the light emitting element is 500 cd / m ² and the aperture ratio of the pixel is 50%, the power consumption is 1 W or less (950 mW). On the other hand, the power consumption of the display device that performs constant current driving was approximately 2 W (2040 mW) when the luminance of the light emitting element was 500 cd / m ² and the aperture ratio of the pixel was 25%. That is, it can be seen that power consumption can be reduced by adopting constant voltage driving. Note that power consumption can be reduced to 1 W or less, preferably 0.7 W or less by employing constant voltage driving.

Note that the above power consumption value is the power consumption of only the pixel region, and does not include the power consumption of the drive circuit portion. In both cases, the display duty ratio of the time gradation is 70%.

In addition, the number of pixels in the pixel region of the display device that performs the constant voltage drive and the display device that performs the constant current drive, in which the power consumption is measured, is 240 × 3 × 320, and both are the same.

Note that as described above, the transistor in the present invention may be any type of transistor, and may be formed on any substrate. Therefore, the circuit as shown in FIG. 4 may be entirely formed on a glass substrate, may be formed on a plastic substrate, may be formed on a single crystal substrate, or may be an SOI substrate. It may be formed on any substrate, and may be formed on any substrate. Alternatively, a part of the circuit in FIG. 4 may be formed on a certain substrate, and another part of the circuit in FIG. 4 may be formed on another substrate. That is, all the circuits in FIG. 4 may not be formed on the same substrate. For example, in FIG. 4, a pixel region 40 and a first gate driver 41 are formed using a TFT on a glass substrate, and a source driver 43 (or part thereof) is formed on a single crystal substrate, The IC chip may be connected to the glass substrate by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Auto Bonding) or a printed board.

(Embodiment 2)
In the above configuration, the TFT 12 is P-type, but the case where the TFT 12 is N-type will be described with reference to FIG.

The pixel 10 includes a light-emitting element 13, a capacitor 16, and TFTs 11 and 12 (see FIG. 19A). When the light emitting element 13 has a forward stacked structure (the pixel electrode is an anode and the counter electrode is a cathode), when applying a forward bias voltage to the light emitting element 13 in accordance with the current flow direction of the light emitting element 13, The power source 17 is a high potential power source, and the second power source 18 is a low potential power source. When a reverse bias voltage is applied to the light emitting element 13, the first power source 17 is a low potential power source and the second power source 18 is a high potential power source. The capacitive element 16 is for holding the voltage between the gate and the source of the TFT 12. According to the above configuration, the source electrode of the TFT 12 is a terminal connected to the pixel electrode of the light emitting element 13. The capacitive element 16 is provided between the pixel electrode of the light emitting element 13 and the gate electrode of the TFT 12.

On the other hand, when the light emitting element 13 has a reverse stacking structure (the pixel electrode is a cathode and the counter electrode is an anode), when applying a forward bias voltage to the light emitting element 13 according to the current flow direction of the light emitting element 13, The first power supply 17 is a low potential power supply, and the second power supply 18 is a high potential power supply. When a reverse bias voltage is applied to the light emitting element 13, the first power source 17 is a high potential power source and the second power source 18 is a low potential power source. In addition, since the source electrode of the TFT 12 is a terminal connected to the power supply line Vx, the capacitor 16 is provided between the power supply line Vx and the gate electrode of the TFT 12.

A cross-sectional structure of the display device shown in FIG. 19A is shown in FIG. In the display device, TFTs 11 and 12, a light emitting element 13, and a capacitor element 16 are provided on a substrate 20 having an insulating surface such as glass or quartz. The conductivity type of the TFT 11 is not particularly limited. However, if the TFT 11 is also an N type, the TFTs 11 and 12 have the same conductivity type. Then, since it is not necessary to make TFTs separately, the yield can be improved.

The display device of the present invention having the above structure is characterized in that the number of transistors arranged in the pixel 10 is two. With the above features, high aperture ratio, high definition, and high yield are achieved. In addition, by realizing a high aperture ratio, the drive voltage can be lowered, so that power consumption can be reduced.

(Embodiment 3)
A configuration of the source driver 43 included in the display device of the present invention will be described with reference to FIGS. The source driver 43 includes a pulse output circuit 44, a NAND 71, a first latch 47, a second latch 48, a selection circuit 46 (the first latch 47, the second latch 48, and the selection circuit 46 are collectively referred to as SLAT in the drawing). (See FIG. 5). The pulse output circuit 44 has a configuration in which a plurality of unit circuits (SSR) 70 are connected in cascade. The pulse output circuit 44 is supplied with a clock signal (SCK), a clock back signal (SCKB), and a start pulse (SSP). A data signal (DataR, DataG, DataB) is supplied to the first latch 47. The second latch 48 is supplied with a latch pulse (SLAT) and an inversion pulse (SLATB) of the latch pulse. The selection circuit 46 is supplied with a write / erase signal (SWE, Write Erase signal, hereinafter sometimes referred to as WE signal) and an inverted signal (SWEB) of the WE signal.

The unit circuit 70 included in the pulse output circuit 44 includes a plurality of transistors and a logic circuit (see FIG. 6). In the unit circuit 70, a resistance element 72 is provided as a protection circuit at an input node (P1) to which a clock signal or a clock back signal is input. Resistive elements 76 to 78 are provided as protection circuits at input nodes (P3, P4, P5), which are input nodes of the first latch 47 and to which data signals are supplied (see FIG. 7). Although not shown in FIG. 5, a level shifter 73 and a buffer 74 are provided below the selection circuit 46, and a protection circuit 75 is provided below the buffer 74. The protection circuit 75 includes four transistors 79 to 82 for one source line. Note that the power supply potentials 83 to 85 supplied to the buffer 74 are set according to the color of light emitted from the pixels connected to the source line Sx.

The source driver 43 includes a first protection circuit (corresponding to the resistance element 72 in the illustrated configuration) connected to the input node (P1) of the pulse output circuit 44, and input nodes (P3, P4, P5) of the first latch 47. ) Connected to a second protection circuit (corresponding to resistance elements 76 to 78 in the configuration shown) and a third protection circuit provided in the lower stage of the selection circuit 46 (corresponding to transistors 79 to 82 in the configuration shown) It is characterized by having. With the above characteristics, deterioration and destruction of the element due to static electricity can be suppressed.

Next, the configuration of the first gate driver 41 will be described with reference to FIGS. Since the configuration of the second gate driver 42 is the same as that of the first gate driver 41, the description of the configuration is omitted here. The first gate driver 41 includes a pulse output circuit 54, a level shifter (GLS) 86, and a selection circuit 55 (see FIG. 8). The configuration of the pulse output circuit 54 is the same as that of the pulse output circuit 44 included in the source driver 43, and has a configuration in which a plurality of unit circuits (GSR) 70 are connected in cascade, and the input node (P1) has a protection circuit. Is provided.

The selection circuit 55 includes a tristate buffer 87 and a protection circuit 88 (see FIG. 9). The tri-state buffer 87 prevents one of the first gate driver 41 and the second gate driver 42 from disturbing the output of the other driver when the gate line Gy is charged / discharged. Therefore, as the selection circuit 55, an analog switch, a clocked inverter, or the like may be used in addition to the tristate buffer as long as it has the above function. The protection circuit 88 includes element groups 89 and 90.

The first gate driver 41 is provided at the lower stage of the first protection circuit (corresponding to the resistance element 72 in the configuration shown in FIG. 6) connected to the input node (P1) of the pulse output circuit 54 and the selection circuit 55. A feature is that a second protection circuit 88 is provided. With the above characteristics, deterioration and destruction of the element due to static electricity can be suppressed. More specifically, a clock signal or a data signal input to the input node may contain noise, and this noise may momentarily give a high voltage or a low voltage to the element. However, the present invention having a protection circuit can suppress malfunction of the element, deterioration and destruction of the element.

Note that the protection circuit includes not only a resistance element and a transistor but also one or a plurality of types selected from a resistance element, a capacitor element, and a rectifier element. The rectifying element is a transistor or a diode in which a gate electrode and a drain electrode are connected.

Next, the operation of the protection circuit will be briefly described. Here, the operation of the protection circuit 88 included in the first gate driver 41 will be described.
First, it is assumed that a signal having a voltage higher than VDD is supplied from the output node of the tristate buffer 87 due to the influence of noise or the like. Then, the element group 89 is turned off and the element group 90 is turned on from the relationship between the gate-source voltages. Then, the charge charged in the tristate buffer 87 is discharged to the power supply line that transmits VDD, and the potential of the gate line Gx is VDD or VDD + α (α is a number of 0 or more, and VDD + α is higher than VDD. Potential).

On the other hand, it is assumed that a signal having a voltage lower than VSS is supplied from the output node of the tristate buffer 87. Then, the element group 89 is turned on and the element group 90 is turned off from the relationship between the gate-source voltages. Then, the potential of the gate line Gx becomes VSS or VSS-α (α is a number of 0 or more, and VSS-α means a potential lower than VSS).
Thus, even if the voltage supplied from the output node of the tristate buffer 87 instantaneously becomes higher than VDD or lower than VSS due to noise or the like, the voltage applied to the gate line Gx is , Not higher than VDD and lower than VSS. Therefore, malfunction, damage, and destruction of the element due to noise, static electricity, and the like can be suppressed.

In addition, the display device of the present invention includes a protection circuit 101 provided between a connection film such as an FPC (Flexible Print Circuit) and the first gate driver 41, the second gate driver 42, or the source driver 43 ( FIG. 18). In the case of the source driver 43, signals such as SCK, SSP, DataR, DataG, DataB, SLAT, and SWE are supplied from the outside through the connection film, but the protection circuit 101 transmits the signals listed above. It is provided between the wiring and the connection film. In the case of the first gate driver 41, signals such as GCK, G1SP, PWC, and WE are supplied from the outside through the connection film, but the protection circuit 101 is a wiring that transmits the signals listed above. And the connecting film. In the configuration shown in the figure, the protection circuit 101 includes transistors 95 and 96, resistance elements 97 and 98, and capacitive elements 99 and 100 whose gate electrodes and drain electrodes are connected. This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 4)
The temperature compensation function of the present invention is executed by the monitor circuit 64, the control circuit 65, and the power supply control circuit 63 that operate based on the ambient temperature (see FIG. 10). The monitor circuit 64 includes a light emitting element 66 in the illustrated configuration. One electrode of the light emitting element 66 is connected to a power source maintained at a constant potential (grounded in the configuration shown in the figure), and the other electrode is connected to the control circuit 65. The control circuit 65 includes a constant current source 91 and an amplifier 92. The power supply control circuit 63 includes a power supply circuit 61 and a controller 62. The power supply circuit 61 is preferably a variable power supply that can change the power supply potential to be supplied.

A mechanism in which the light emitting element 66 detects the environmental temperature will be described. A constant current is supplied from the constant current source 91 between both electrodes of the light emitting element 66. That is, the current value of the light emitting element 66 is always constant. When the environmental temperature changes in this state, the resistance value of the light emitting element 66 itself changes. When the resistance value of the light emitting element 66 changes, the current value of the light emitting element 66 is always constant, so that the potential difference between both electrodes of the light emitting element 66 changes. By detecting a change in potential difference between both electrodes of the light emitting element 66 due to this temperature change, a change in environmental temperature is detected. More specifically, since the potential of the electrode on the side of the light emitting element 66 maintained at a constant potential does not change, a change in the potential of the electrode connected to the constant current source 91 is detected.

A signal including information on such a change in potential of the light emitting element is supplied to the amplifier 92, amplified by the amplifier 92, and then output to the power supply control circuit 63. The power supply control circuit 63 changes the potential of the power supplied to the pixel region 40 through the amplifier 92 based on the output of the monitor circuit 64. Then, the power supply potential can be corrected according to the temperature change. That is, the fluctuation of the current value caused by the temperature change can be suppressed.

In addition, in the structure shown in figure, although it has multiple light emitting elements 66, this invention is not restrict | limited to this. The number of light emitting elements 66 provided in the monitor circuit 64 is not limited. Even when the light-emitting element 66 is used, a structure in which a transistor is connected to the light-emitting element 66 in series may be applied. In that case, when necessary, a transistor connected in series to the light-emitting element 66 is turned on.

Further, although the light emitting element 66 is used as the monitor circuit 64, the present invention is not limited to this, and a known temperature sensor may be used. When a known temperature sensor is used, it may be provided on the same substrate as the pixel region 40 or may be externally attached using an IC. Since the temperature compensation function of the present invention does not require any operation by the user, it can be corrected continuously after the display device is passed to the end user, so that the product can have a long life. This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 5)
The operation of the display device of the present invention will be described with reference to FIGS. First, the operation of the source driver will be described (see FIGS. 4 and 11A). The pulse output circuit 44 receives a clock signal (hereinafter referred to as SCK), a clock inversion signal (hereinafter referred to as SCKB), and a start pulse (hereinafter referred to as SSP), and the first latch 47 according to the timing of these signals. Outputs a sampling pulse. The first latch 47 to which data is input holds the video signal from the first column to the last column in accordance with the timing at which the sampling pulse is input. When the latch pulse is input, the second latch 48 transfers the video signals held in the first latch 47 to the second latch 48 all at once.

Here, the operation of the selection circuit 46 in each period will be described with the period T1 when the WE signal transmitted from the selection signal line 52 is L level and the period T2 when the WE signal is H level. The periods T1 and T2 correspond to half of the horizontal scanning period. The period T1 is also referred to as a first sub-gate selection period and the period T2 is also referred to as a second sub-gate selection period.

In the period T1 (first sub-gate selection period), the WE signal transmitted from the selection signal line 52 is at the L level, the TFT 49 is turned on, and the analog switch 50 is turned off. Then, the plurality of signal lines S1 to Sm are electrically connected to the power supply 53 via the TFTs 49 arranged in each column. That is, the plurality of signal lines S <b> 1 to Sm have the same potential as the power supply 53.

At this time, the TFT 11 included in the pixel 10 is in an on state, and the potential of the power supply 53 is transmitted to the gate electrode of the TFT 12 through the TFT 11. Then, the TFT 12 is turned off, and the two electrodes included in the light emitting element 13 have the same potential. That is, no current flows between both electrodes included in the light emitting element 13 and no light is emitted. In this manner, regardless of the state of the video signal input to the video line, the potential of the power supply 53 is transmitted to the gate electrode of the TFT 12, the TFT 11 is turned off, and the potentials of the two electrodes included in the light emitting element 13. An operation in which the same potential is applied is called an erase operation.

In the period T2 (second sub-gate selection period), the WE signal transmitted from the selection signal line 52 is at the H level, the TFT 49 is turned off, and the analog switch 50 is turned on. Then, the video signal held in the second latch 48 is transmitted to a plurality of signal lines S1 to Sm for one row at the same time. At this time, the TFT 11 included in the pixel 10 is in an on state, and a video signal is transmitted to the gate electrode of the TFT 12 through the TFT 11. Then, according to the input video signal, the TFT 12 is turned on or off, and the two electrodes included in the light emitting element 13 have different potentials or the same potential. More specifically, when the TFT 12 is turned on, the two electrodes included in the light emitting element 13 have different potentials, and a current flows through the light emitting element 13. That is, the light emitting element 13 emits light. The current flowing through the light emitting element 13 is the same as the current flowing between the source electrode and the drain electrode of the TFT 12.

On the other hand, when the TFT 12 is turned off, the two electrodes included in the light emitting element 13 have the same potential, and no current flows through the light emitting element 13. That is, the light emitting element 13 does not emit light. In this manner, an operation in which the TFT 12 is turned on or off in accordance with the video signal and the potentials of the two electrodes included in the light emitting element 13 are different from each other or the same potential is referred to as a writing operation.

Next, operations of the first gate driver 41 and the second gate driver 42 will be described. G1CK, G1CKB, and G1SP are input to the pulse output circuit 54, and pulses are sequentially output to the selection circuit 55 in accordance with the timing of these signals. G2CK, G2CKB, and G2SP are input to the pulse output circuit 56, and pulses are sequentially output to the selection circuit 57 in accordance with the timing of these signals. FIG. 11B shows each column of the i-th row, j-th row, k-th row, and p-th row (i, j, k, p are natural numbers, 1 ≦ i, j, k, p ≦ n). The potential of the pulse supplied to the selection circuits 55 and 57 is shown.

Here, similarly to the description of the operation of the source driver 43, the period T1 is when the WE signal transmitted from the selection signal line 52 is L level, and the period T2 is when the WE signal is H level. The operation of the selection circuit 55 included in the first gate driver 41 and the selection circuit 57 included in the second gate driver 42 will be described. Note that in the timing chart of FIG. 11B, the potential of the gate line Gy (y is a natural number, 1 ≦ y ≦ n) to which a signal is transmitted from the first gate driver 41 is denoted as Gy41, and the second gate The potential of the gate line to which the signal is transmitted from the driver 42 is denoted as Gy42. Needless to say, Gy41 and Gy42 indicate the same wiring.

In the period T1 (first sub-gate selection period), the WE signal transmitted from the selection signal line 52 is at the L level. Then, the L level WE signal is input to the selection circuit 55 included in the first gate driver 41, and the selection circuit 55 becomes indefinite. On the other hand, an H level signal obtained by inverting the WE signal is input to the selection circuit 57 included in the second gate driver 42, and the selection circuit 57 enters an operating state. That is, the selection circuit 57 transmits an H level signal (row selection signal) to the i-th gate line Gi, and the gate line Gi has the same potential as the H-level signal. That is, the second gate driver 42 selects the i-th gate line Gi.

As a result, the TFT 11 included in the pixel 10 is turned on. Then, the potential of the power supply 53 included in the source driver 43 is transmitted to the gate electrode of the TFT 12, the TFT 12 is turned off, and the potentials of both electrodes of the light emitting element 13 are the same potential. That is, during this period, an erasing operation in which the light emitting element 13 does not emit light is performed.

In the period T2 (second sub-gate selection period), the WE signal transmitted from the selection signal line 52 is at the H level. Then, an H level WE signal is input to the selection circuit 55 included in the first gate driver 41, and the selection circuit 55 enters an operating state. That is, the selection circuit 55 transmits the H level signal to the gate line Gi of the i-th row, and the gate line Gi has the same potential as the H level signal. That is, the first gate driver 41 selects the i-th gate line Gi.

As a result, the TFT 11 included in the pixel 10 is turned on. Then, the video signal is transmitted from the second latch 48 included in the source driver 43 to the gate electrode of the TFT 12, the TFT 12 is turned on or off, and the potentials of the two electrodes included in the light emitting element 13 are different from each other. It becomes a potential. That is, in this period, the writing operation in which the light emitting element 13 emits light or does not emit light is performed. On the other hand, an L level signal is input to the selection circuit 57 included in the second gate driver 42, and an indefinite state is set.

As described above, the gate line Gy is selected by the second gate driver 42 in the period T1 (first subgate selection period), and is selected by the first gate driver 41 in the period T2 (second subgate selection period). The That is, the gate line is controlled complementarily by the first gate driver 41 and the second gate driver 42. Then, in the first sub-gate selection period and the second sub-gate selection period, an erase operation is performed on one side and a write operation is performed on the other side.

Note that in a period in which the first gate driver 41 selects the i-th gate line Gi, the second gate driver 42 is not operating (the selection circuit 57 is in an indefinite state) or other than the i-th row. A row selection signal is transmitted to the gate line of the row. Similarly, during a period in which the second gate driver 42 transmits a row selection signal to the i-th gate line Gi, the first gate driver 41 is in an indefinite state, or the gate lines of other rows except for the i-th row. A row selection signal is transmitted.

In addition, since the light emitting element 13 can be forcibly turned off according to the present invention that performs the above-described operation, the duty ratio can be improved even when the number of gradations increases. Further, although the light emitting element 13 can be forcibly turned off, it is not necessary to provide a TFT for discharging the charge of the capacitor 16, and thus a high aperture ratio is realized. When a high aperture ratio is realized, the luminance of the light-emitting element can be lowered with an increase in the area that emits light. That is, since the driving voltage can be lowered, power consumption can be reduced.

Note that the present invention is not limited to the above-described form in which the gate selection period is divided into two. The gate selection period may be divided into three or more. This embodiment mode can be freely combined with the above embodiment modes.

Note that an erasing signal is input to the pixel in the first half of the gate selection period (first sub-gate selection period), and an image (video) signal is input to the pixel in the second half of the gate selection period (second sub-gate selection period). However, it is not limited to this. In the first half of the gate selection period (first sub-gate selection period), an image (video) signal is input to the pixel, and in the second half of the gate selection period (second sub-gate selection period), an erase signal is input to the pixel. Also good.

  Alternatively, an image (video) signal is input to the pixel also in the first half of the gate selection period (first sub-gate selection period), and an image (video) is also input to the pixel in the second half of the gate selection period (second sub-gate selection period). ) A signal may be input. A signal corresponding to a different subframe may be input to each. As a result, the subframe period can be provided so that the lighting period is continuously arranged without providing the erasing period. In this case, since it is not necessary to provide an erasing period, the duty ratio can be increased.

(Embodiment 6)
Regarding the operation of the display device of the present invention, the vertical axis represents the scanning line, the horizontal axis represents the time (FIGS. 12A and 12C), and the timing of the i-th gate line Gi (1 ≦ i ≦ m). This will be described with reference to charts (FIGS. 12B and 12D). In the time gray scale method, one frame period has a plurality of subframe periods SF1, SF2,..., SFn (n is a natural number).

Each of the plurality of subframe periods includes one selected from a plurality of write periods Ta1, Ta2,..., Tan performing a write operation or an erase operation, and a plurality of lighting periods Ts1, Ts2,. With one selected. Each of the plurality of writing periods has a plurality of gate selection periods. Each of the plurality of gate selection periods has a plurality of sub-gate selection periods. The number of divisions in each gate selection period is not particularly limited, but is preferably divided into two to eight, and more preferably two to four. Further, the lighting period Ts1: Ts2:...: Tsn has a length ratio of, for example, 2 ^(n-1) : 2 ^(n-2) : ...: 2 ¹ : 2 ⁰ . That is, the lighting periods Ts1, Ts2,..., Tsn are set so that each bit has a different length.

In the following, a timing chart in the case where the AC drive period FRB (Frame Reverse Bias) is not included and 3-bit gradation (8 gradations) is expressed will be described (FIGS. 12A and 12B). )reference). In this case, one frame period is divided into three subframe periods SF1 to SF3. The sub-frame periods SF1 to SF3 have one selected from the writing periods Ta1 to Ta3 and one selected from the lighting periods Ts1 to Ts3. The writing period has a plurality of gate selection periods. Each of the plurality of gate selection periods has a plurality of subgate selection periods. Here, each of the plurality of gate selection periods has two subgate selection periods, and performs an erasing operation in the first subgate selection period. A case where a writing operation is performed in the second sub-gate selection period is described.

Note that the erasing operation is an operation performed in order to make the light emitting element emit no light, and is an operation performed only in a necessary subframe period.

Next, a timing chart in the case where the AC drive period FRB is included will be described (see FIGS. 12C and 12D). The AC driving period FRB includes an AC driving period FRB in which a reverse bias is simultaneously applied to all the light emitting elements by reversing the vertical relationship (level difference) of the potential applied to the light emitting elements, opposite to the writing period TaRB in which only the erasing operation is performed. Have.

Note that the AC driving period FRB is not necessarily provided in each frame period, and may be provided for each of a plurality of frame periods. Further, the subframe periods SF1 to SF3 and the AC drive period (also referred to as reverse bias application period) FRB need not be provided separately, and may be provided during the lighting periods Ts1 to Ts3 of a certain subframe period.

Further, the order of the subframe periods is not limited to the above description that appears in the order of the upper bits to the lower bits, and the order of appearance may be random. Further, the order in which the subframe periods appear may be random for each frame period.
One or a plurality of periods selected from a plurality of subframe periods may be divided into a plurality of periods. In that case, each of the divided one or more subframe periods and each of the non-divided one or more subframe periods includes a plurality of writing periods Ta1, Ta2,. One selected from a natural number) and one selected from a plurality of lighting periods Ts1, Ts2, ..., Tsm.

Therefore, a timing chart in the case where the subframe period of the upper bits is divided into a plurality of parts and the order in which the subframe periods appear is random will be described (see FIG. 13). The timing chart shown expresses 6-bit gradation, and the subframe period SF1 is divided into three (indicated by SF1-1 to SF1-3 in the figure), and the subframe period SF2 is divided into two. (Indicated by SF2-1 and SF2-2 in the figure), the subframe period SF3 is divided into two (indicated by SF3-1 and SF3-2 in the figure). Then, the display timing of the first row pixels, the display timing of the last row pixels, the scanning timing of the erasing gate driver, and the scanning timing of the writing gate driver are shown. The display duty ratio of the timing chart shown in the figure is 51%. This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 7)
As described above, the display device of the present invention includes a plurality of pixels 10 including the light emitting element 13, the capacitor element 16, and the TFTs 11 and 12. Here, however, the power supply line Vx is provided between adjacent pixels. A mode of sharing the data will be described with reference to FIG. As described above, when the power supply line Vx is shared between adjacent pixels, the arrangement of the adjacent pixels is in a horizontally inverted relationship with each other. When the power supply line Vx is shared between adjacent pixels, the number of wirings to be arranged can be reduced, so that a high aperture ratio is realized. When a high aperture ratio is realized, the luminance of the light-emitting element can be lowered with an increase in the area that emits light. That is, since the driving voltage can be lowered, power consumption can be reduced.

In the case of the above structure, the light emitting element preferably emits monochromatic or white light. If a filter or a color conversion layer is provided on the light emission side, color display can be performed. As described above, when the power supply line is shared, it is easier to correct the power supply potential with respect to deterioration if the structure emits monochromatic or white light than the electroluminescent layer is separately applied. This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 8)
The display device of the present invention may be provided with a polarizing plate, a wave plate, and a circularly polarizing plate in order to improve contrast. The light-emitting element included in the display device of the present invention has a structure including an electroluminescent layer between a pair of electrodes. In the case of performing color display, electroluminescent layers having different emission wavelength bands may be formed for each pixel. Typically, electroluminescent layers corresponding to red (R), green (G), and blue (B) colors are used. Form. In this case, when a filter (colored layer) that transmits light in the emission wavelength band is provided on the light emitting side of the light emitting element, the color purity is improved and the mirroring (reflection) of the pixel portion is prevented. Can be achieved. In addition, when a filter is provided, it is possible to omit a circularly polarizing plate that has been conventionally required, and it is possible to eliminate loss of light emitted from the electroluminescent layer. Furthermore, a change in color tone that occurs when the pixel region is viewed obliquely can be reduced. The electroluminescent layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be performed if a filter that transmits light of a specific wavelength is provided on the light emitting side of the light emitting element.

For the electroluminescent layer, a material that emits light from singlet excitation (hereinafter referred to as singlet excitation material) or a material that emits light from triplet excitation (hereinafter referred to as triplet excitation material) is used. For example, among light-emitting elements that emit red light, light-emitting elements that emit green light, and light-emitting elements that emit blue light, a red light emitting element having a relatively short luminance half time is formed of a triplet excited light emitting material, and the other light emitting element is single-layered. It is formed of a term excitation luminescent material. The triplet excited light-emitting material has an advantage in that the light emission efficiency is good, so that less power is required to obtain the same luminance.

Alternatively, the red and green materials may be formed of a triplet excited light emitting material, and the blue material may be formed of a singlet excited light emitting material. By forming a green light-emitting element having high human visibility with a triplet excitation light-emitting material, further reduction in power consumption can be achieved. Note that examples of triplet excited light emitting materials include those using a metal complex as a dopant, such as a metal complex having platinum as a third transition series element as a central metal, and a metal complex having iridium as a central metal.

The light emitting element may use either a stacked structure in which an anode, an electroluminescent layer, and a cathode are sequentially stacked from the bottom, or a reverse stacked structure in which a cathode, an electroluminescent layer, and an anode are sequentially stacked from the bottom. As the electrode included in the light-emitting element, light-transmitting ITO (indium tin oxide), ITSO in which silicon is added to ITO, IZO (indium zinc oxide), or GZO (gallium zinc oxide) may be used. . This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 9)
A panel on which a pixel region 40, a first gate driver 41, a second gate driver 42, and a source driver 43 are mounted, which is an embodiment of the display device of the present invention, will be described. Over the substrate 405, a pixel region 40 including a plurality of pixels including the light-emitting element 13, a first gate driver 41, a second gate driver 42, a source driver 43, and a connection film 407 are provided (see FIG. 15A). ). The connection film 407 is connected to an external circuit (IC chip).

FIG. 15B is a cross-sectional view taken along the line A-A ′ of the panel, and shows the TFT 12 provided in the pixel region 40, the light emitting element 13, and the CMOS circuit 410 provided in the source driver 43.

A sealing material 408 is provided around the pixel region 40, the first gate driver 41, the second gate driver 42, and the source driver 43, and the light emitting element 13 is sealed by the sealing material 408 and the counter substrate 406. . This sealing process is a process for protecting the light emitting element 13 from moisture. Here, a method of sealing with a cover material (glass, ceramics, plastic, metal, etc.) is used, but a thermosetting resin or ultraviolet light is used. A method of sealing with a curable resin or a method of sealing with a thin film having a high barrier ability such as a metal oxide or a nitride may be used. The element formed over the substrate 405 is preferably formed using a crystalline semiconductor (polysilicon) having favorable characteristics such as mobility as compared to an amorphous semiconductor. Realized. Since the number of external ICs to be connected is reduced, the panel having the above configuration can be made small, light, and thin.

Note that in the above structure, the pixel electrode of the light-emitting element 13 has a light-transmitting property, and the counter electrode of the light-emitting element 13 has a light-blocking property. Therefore, the light emitting element 13 performs bottom emission.

As a structure different from the above, the pixel electrode of the light-emitting element 13 may have a light-shielding property, and the counter electrode of the light-emitting element 13 may have a light-transmitting property (see FIG. 16A). In this case, the light emitting element 13 performs top emission.

As another structure different from the above, both the pixel electrode of the light-emitting element 13 and the counter electrode of the light-emitting element 13 may have a light-transmitting property (see FIG. 16B). In this case, the light emitting element 13 performs double-sided emission.

The display device of the present invention may employ any of bottom emission, top emission, and dual emission. However, in the case of performing bottom emission and double emission, the conductive layer (corresponding to the source wiring or drain wiring) connected to the impurity region included in the TFT 12 is a material with low reflectivity such as aluminum (Al) and molybdenum (Mo). It is good to form with what combined. Specifically, a laminated structure of molybdenum (Mo), aluminum-silicon (Al-Si, aluminum (Al) to which silicon (Si) is added) and molybdenum (Mo), molybdenum nitride (MoN, molybdenum (Mo) and Composition ratio of nitrogen (N) is not limited), aluminum-silicon (Al-Si, aluminum (Al) to which silicon (Si) is added), and molybdenum nitride (MoN, molybdenum (Mo) and nitrogen (N)) It is preferable to adopt a laminated structure such as a ratio is not limited. If it does so, it can prevent that the light emitted from the light emitting element reflects in a source wiring or a drain wiring, and can take out light outside.

Note that the pixel region 40 is configured by a TFT using an amorphous semiconductor (amorphous silicon) formed on an insulating surface as a channel portion, and the first gate driver 41, the second gate driver 42, and the source driver 43 are ICs. You may comprise with a chip | tip. The IC chip may be bonded onto the substrate 405 by a COG method, or may be bonded to the connection film 407 connected to the substrate 405. An amorphous semiconductor can be easily formed on a large-area substrate by using the CVD method and does not require a crystallization step, so that an inexpensive panel can be provided. At this time, if a conductive layer is formed by a droplet discharge method typified by an ink jet method, a cheaper panel can be provided. This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 10)
Mobile devices such as television devices (TVs, television receivers), digital cameras, digital video cameras, mobile phone devices (mobile phones), PDAs, and the like as electronic devices using display devices having pixel regions including light-emitting elements Examples thereof include a terminal, a portable game machine, a monitor, a computer, an audio playback device such as a car audio, and an image playback device equipped with a recording medium such as a home game machine. A specific example will be described with reference to FIG.

A portable information terminal using the display device of the present invention illustrated in FIG. 17A includes a main body 9201, a display portion 9202, and the like. Power consumption can be reduced by the present invention. A digital video camera using the display device of the present invention illustrated in FIG. 17B includes display portions 9701 and 9702, and the present invention can reduce power consumption. A portable terminal using the display device of the present invention illustrated in FIG. 17C includes a main body 9101, a display portion 9102, and the like, and can reduce power consumption according to the present invention. A portable television device using the display device of the present invention illustrated in FIG. 17D includes a main body 9301, a display portion 9302, and the like. Power consumption can be reduced by the present invention. A portable computer using the display device of the present invention illustrated in FIG. 17E includes a main body 9401, a display portion 9402, and the like. Power consumption can be reduced by the present invention. A television set using the display device of the present invention illustrated in FIG. 17F includes a main body 9501, a display portion 9502, and the like, and can reduce power consumption according to the present invention. Among the electronic devices mentioned above, those using a battery can extend the usage time of the electronic device by reducing the power consumption, and can save the trouble of charging the battery.

A specific example of a compensation circuit for temperature characteristics and luminance characteristics is shown in FIG. A display panel 2020 and a power source 2000 are included. The power supply 2000 corresponds to the control circuit 65 of the display device shown in FIG. 4 of the first embodiment. The display panel includes a pixel portion 2021, a monitor element 2027, and a first power supply terminal 2026, and the pixel portion 2021 includes a switching TFT 2022, a storage capacitor 2023, a driving TFT 2024, and a light emitting element 2025. When the driving TFT 2024 is turned on and the light emitting element 2025 is connected to the second power supply terminal 2028, the light emitting element 2025 emits light.

Since the current / voltage characteristics of the light emitting element 2025 change with temperature, when a constant voltage is applied, the light emitting element 2025 has high luminance at high temperature and low luminance at low temperature. In order to correct this, a constant current is passed from the constant current source 2011 to the monitor element 2027, and a voltage generated there is applied to the second power supply terminal 2028 via the amplifier 2012 and the transistor 2013. If the monitor element 2027 and the light emitting element 2025 are formed of the same material, the temperature characteristic is canceled and the luminance can be kept constant with respect to the temperature.

A power supply 2000 is a switching regulator, and includes a first comparator 2001, a second comparator 2002, an oscillation circuit 2004, a smoothing capacitor 2005, a diode 2006, a switch transistor 2008, an inductor 2009, reference power supplies 2003, 2007, 2014, and an attenuator 2010. Is done. The reference power supply 2007 uses a power supply with a large current capacity, such as a battery.

The configuration of the switching regulator is not limited to the above, and other configurations may be used. In FIG. 20, the switch transistor is an NPN bipolar transistor, but this is not limited to this.

The output signal of the oscillation circuit 2004 is compared with the output signal of the reference power supply 2003 and the first comparator 2001 by the second comparator 2002, and the switch transistor 2008 is turned on / off by the output signal of the second comparator 2002. When the switch transistor 2008 is turned on, a current flows through the inductor 2009 and the magnetic field energy is held in the inductor 2009. When the switch transistor 2008 is turned off, the magnetic field energy changes to a voltage and charges the smoothing capacitor 2005 via the diode 2006. Depending on the on / off duty of the switch transistor 2008, the DC voltage generated in the smoothing capacitor changes.

The DC voltage of the smoothing capacitor 2005 is attenuated by the attenuator 2010 and input to the first comparator 2001. The first comparator 2001 compares the voltages of the reference power supply 2014 and the attenuator 2010 and inputs the output to the second comparator 2002. In this way, feedback is applied and a necessary voltage can be generated in the smoothing capacitor 2005. Although the constant current source 2011, the amplifier 2012, and the monitor element 2027 are directly connected here, they may be connected via other elements such as resistors and switches.

In the embodiment shown in FIG. 20, the voltage of the smoothing capacitor 2005 takes a constant value without depending on temperature, but the light emitting element has temperature characteristics. In general, the voltage of a light emitting element is large at a low temperature and small at a high temperature. FIG. 21A shows such a state. At high temperatures, the difference between the light emitting element voltage and the smoothing capacitor voltage (denoted as a switching regulator voltage in FIG. 21) becomes large, and this amount consumes wasted power. As shown in FIG. 21B, useless power can be reduced if the switching regulator voltage is lowered in conjunction with the light emitting element voltage at a high temperature.

FIG. 22 shows an embodiment conceived for solving such a problem. The voltage of the monitor element is also input to the switching regulator, and the switching regulator voltage is linked to the light emitting element voltage.

FIG. 22 shows a specific example of a compensation circuit for temperature characteristics and luminance characteristics. A display panel 2220 and a power source 2200 are included. The power source 2200 corresponds to the control circuit 65 of the display device shown in FIG. The display panel includes a pixel portion 2221, a monitor element 2227, and a first power supply terminal 2226, and the pixel portion 2221 includes a switching TFT 2222, a storage capacitor 2223, a driving TFT 2224, and a light emitting element 2225. When the driving TFT 2224 is turned on and the light emitting element 2225 is connected to the second power supply terminal 2228, the light emitting element 2225 emits light.

Since the current / voltage characteristics of the light-emitting element 2225 change with temperature, when a constant voltage is applied, the light-emitting element 2225 has high luminance at high temperature and low luminance at low temperature. In order to correct this, a constant current is supplied from the constant current source 2211 to the monitor element 2227, and a voltage generated there is applied to the second power supply terminal 2228 via the amplifier 2212 and the transistor 2213. If the monitor element 2227 and the light emitting element 2225 are formed of the same material, the temperature characteristic is canceled and the luminance can be kept constant with respect to the temperature.

A power supply 2200 is a switching regulator and includes a first comparator 2201, a second comparator 2202, an oscillation circuit 2204, a smoothing capacitor 2205, a diode 2206, a switch transistor 2208, an inductor 2209, reference power supplies 2203 and 2207, and an attenuator 2210. . The reference power source 2207 uses a power source having a large current capacity, such as a battery.

The configuration of the switching regulator is not limited to the above, and other configurations may be used. In FIG. 22, the switch transistor is an NPN bipolar transistor, but this is not limited to this.

The output signal of the oscillation circuit 2204, the reference power supply 2203, and the output signal of the first comparator 2201 are compared by the second comparator 2202, and the switch transistor 2208 is turned on / off by the output signal of the second comparator 2202. When the switch transistor 2208 is turned on, a current flows through the inductor 2209 and the magnetic field energy is held in the inductor 2209. When the switch transistor 2208 is turned off, the magnetic field energy changes to a voltage and charges the smoothing capacitor 2205 via the diode 2206. Depending on the on / off duty of the switch transistor 2208, the DC voltage generated in the smoothing capacitor changes.

The voltage of the monitor element 2227 is input to the first comparator 2201 through the amplifier 2214 and the attenuator 2215. The DC voltage of the smoothing capacitor 2205 is attenuated by the attenuator 2210 and input to the first comparator 2201. The first comparator 2201 compares the voltages of the attenuator 2215 and the attenuator 2210 and inputs the output to the second comparator 2202. In this way, feedback is applied and a necessary voltage can be generated in the smoothing capacitor 2205.

Although the constant current source 2211, the amplifiers 2212 and 2214, and the monitor element 2227 are directly connected here, they may be connected via other elements such as resistors and switches.

FIG. 23 shows an embodiment in which the output of the switching regulator is directly connected to the second power supply terminal of the display panel. The voltage of the monitor element is also input to the switching regulator, and the switching regulator voltage is linked to the light emitting element voltage.

FIG. 23 shows a specific example of a compensation circuit for temperature characteristics and luminance characteristics. A display panel 2320 and a power source 2300 are included. The power source 2300 corresponds to the control circuit 65 of the display device shown in FIG. The display panel includes a pixel portion 2321, a monitor element 2327, and a first power supply terminal 2326, and the pixel portion 2321 includes a switching TFT 2322, a storage capacitor 2323, a driving TFT 2324, and a light emitting element 2325. When the driving TFT 2324 is turned on and the light emitting element 2325 is connected to the second power supply terminal 2328, the light emitting element 2325 emits light.

Since the current / voltage characteristics of the light-emitting element 2325 change with temperature, when a constant voltage is applied, the light-emitting element 2325 has high luminance at high temperature and low luminance at low temperature. In order to correct this, a constant current is supplied from the constant current source 2311 to the monitor element 2327 and applied to the second power supply terminal 2328 via a switching regulator voltage generated there. If the monitor element 2327 and the light emitting element 2325 are formed of the same material, the temperature characteristic is canceled, and the luminance can be kept constant with respect to the temperature. Compared with the embodiment of FIG. 22, the stability is reduced, but there is an advantage that amplifiers and transistors can be reduced.

A power supply 2300 is a switching regulator and includes a first comparator 2301, a second comparator 2302, an oscillation circuit 2304, a smoothing capacitor 2305, a diode 2306, a switch transistor 2308, an inductor 2309, reference power supplies 2303 and 2307, and an attenuator 2310. . The reference power supply 2307 uses a power supply with a large current capacity, such as a battery. The output signal of the oscillation circuit 2304, the reference power supply 2303, and the output signal of the first comparator 2301 are compared by the second comparator 2302, and the switch transistor 2308 is turned on / off by the output signal of the second comparator 2302. When the switch transistor 2308 is turned on, a current flows through the inductor 2309 and the magnetic field energy is held in the inductor 2309. When the switch transistor 2308 is turned off, the magnetic field energy changes to a voltage and charges the smoothing capacitor 2305 via the diode 2306. The DC voltage generated in the smoothing capacitor changes depending on the on / off duty of the switch transistor 2308.

The voltage of the monitor element 2327 is input to the first comparator 2301 through the amplifier 2314 and the attenuator 2315. The DC voltage of the smoothing capacitor 2305 is attenuated by the attenuator 2310 and input to the first comparator 2301. The first comparator 2301 compares the voltages of the attenuator 2315 and the attenuator 2310 and inputs the output to the second comparator 2302. In this way, feedback is applied and a necessary voltage can be generated in the smoothing capacitor 2305. Although the constant current source 2311, the amplifier 2314, and the monitor element 2327 are directly connected here, they may be connected via other elements such as resistors and switches.

FIG. 24 shows an embodiment in which a plurality of monitor elements are provided. The voltage of a plurality of monitor elements is also input to the switching regulator, and the switching regulator voltage is linked to the light emitting element voltage.

FIG. 24 shows a specific example of a compensation circuit for temperature characteristics and luminance characteristics. A display panel 2420 and a power source 2400 are included. The power supply 2400 corresponds to the control circuit 65 of the display device shown in FIG. The display panel includes a pixel portion 2421, a monitor element 2427, a monitor element 2429, and a first power supply terminal 2426, and the pixel portion 2421 includes a switching TFT 2422, a storage capacitor 2423, a drive TFT 2424, and a light emitting element 2425. . When the driving TFT 2424 is turned on and the light emitting element 2425 is connected to the second power supply terminal 2428, the light emitting element 2425 emits light.

Since the current / voltage characteristics of the light-emitting element 2425 change with temperature, when a constant voltage is applied, the light-emitting element 2425 has high luminance at high temperatures and low luminance at low temperatures. In order to correct this, a constant current is supplied from the constant current source 2411 and the constant current source 2417 to the monitor element 2427 and the monitor element 2429, and the voltage generated there is supplied to the second power supply terminal 2428 via the amplifier 2412 and the transistor 2413. Applied. If the monitor element 2427, the monitor element 2429, and the light emitting element 2425 are formed of the same material, the temperature characteristics are canceled, and the luminance can be kept constant with respect to the temperature.
If two monitor elements are provided on both sides of the pixel portion and averaged by the adder circuit 2416 and then connected to the amplifiers 2412 and 2414, more accurate monitoring can be performed. In the present invention, the number of monitor elements can be further increased. Increasing the number of monitor elements can reduce the difference between the monitor elements and the light emitting elements.

A power supply 2400 is a switching regulator, and includes a first comparator 2401, a second comparator 2402, an oscillation circuit 2404, a smoothing capacitor 2405, a diode 2406, a switch transistor 2408, an inductor 2409, reference power supplies 2403 and 2407, and an attenuator 2410. . The reference power supply 2407 uses a power supply with a large current capacity, such as a battery. The output signal of the oscillation circuit 2404, the reference power supply 2403, and the output signal of the first comparator 2401 are compared by the second comparator 2402, and the switch transistor 2408 is turned on / off by the output signal of the second comparator 2402. When the switch transistor 2408 is turned on, a current flows through the inductor 2409 and magnetic field energy is held in the inductor 2409. When the switch transistor 2408 is turned off, the magnetic field energy changes to a voltage and charges the smoothing capacitor 2405 through the diode 2406. Depending on the on / off duty of the switch transistor 2408, the DC voltage generated in the smoothing capacitor changes.

The voltages of the monitor element 2427 and the monitor element 2429 are input to the first comparator 2401 through the adder circuit 2416, the amplifier 2414, and the attenuator 2415. The DC voltage of the smoothing capacitor 2405 is attenuated by the attenuator 2410 and input to the first comparator 2401. The first comparator 2401 compares the voltages of the attenuator 2415 and the attenuator 2410 and inputs the output to the second comparator 2402.

In this way, feedback is applied and a necessary voltage can be generated in the smoothing capacitor 2405. Here, the constant current source 2411, the constant current source 2417, the amplifier 2412, the monitor element 2427, and the monitor element 2429 are directly connected, but may be connected via other elements such as a resistor and a switch.

In the first to fourth embodiments, the first power supply terminal and the second power supply terminal of the display panel are fixed, but the voltage applied to these terminals is periodically changed by sandwiching a changeover switch or the like, and the light emitting element or the monitor The element may be AC driven.

Moreover, although temperature compensation was described in Examples 1-4, it can compensate also with respect to deterioration of a light emitting element, when a monitor element and a light emitting element deteriorate similarly.

The present invention is not limited to the line-sequential driving source driver 43 as shown in FIG. 4, and a dot-sequential driving source driver can also be applied. Therefore, in this embodiment, an example of a source driver of dot sequential driving that can be applied to the display device of the present invention is shown in FIG. In addition, the same code | symbol is used for the same location as the structure of the source driver 43 of FIG.

A source driver 2501 in FIG. 25 includes a pulse output circuit 44, a switch group 2503, and a selection circuit 46. The switch group includes a switch 2502 corresponding to each column of pixels. The selection circuit 46 also includes an inverter 51, an analog switch 50, and a TFT 49 corresponding to each column of pixels. One terminal of the TFT 49 is connected to the power source 53. As the pulse output circuit 44, for example, a shift register can be used.

An operation method of the source driver 2501 will be briefly described.

When the source driver 2501 performs a write operation, the WE signal is set to H level and the analog switch 50 is turned on. At this time, the TFT 49 that transmits the erase signal is turned off. Then, the switch 2502 in the column where the DATA signal is to be written is sequentially selected by the pulse output circuit 44, and the DATA signal is written to the pixel.

When the source driver 2501 performs an erasing operation, the WE signal is set to L level, the analog switch 50 is turned off, and the erasing TFT 49 is turned on. Then, one terminal of the erasing TFT 49 is connected to the power source 53, and the potential of the power source 53 can be set to the potential of the signal line, so that the gate potential of the TFT for driving the pixel can be set. That is, the potential difference between the gate electrode and the source electrode of the TFT that drives the pixel can be eliminated, and the charge accumulated in the storage capacitor that holds the gate-source voltage can be discharged. . The TFT for driving the pixel corresponds to the TFT 12 in FIG. 4, the signal line corresponds to the signal lines S <b> 1 to Sm in FIG. 4, and the storage capacitor corresponds to the capacitive element 16. The source potential of the TFT 12 is the potential of the power supply line Vx. That is, the potential of the power supply 53 and the potential of the power supply line Vx are preferably equal. Thus, the signal written by the source driver can be erased.

In this embodiment, another configuration of the selection circuit 46 included in the source driver 43 of FIG. 4 is shown in FIG. In this embodiment, a clocked inverter 2603 is applied in place of the analog switch 50 used in the selection circuit 46 of the source driver 43 shown in FIG. In addition, the same code | symbol is used for the same location as the structure of the source driver 43 of FIG.

The source driver 2601 shown in this embodiment includes a pulse output circuit 44, a first latch 47, a second latch 48, and a selection circuit 2602. The selection circuit 2602 includes an inverter 51, a clocked inverter 2603, and a TFT 49. One terminal of the TFT 49 is connected to the power source 53.

An operation method of the selection circuit 2602 shown in this embodiment is briefly described.

When the source driver 2601 performs a write operation, the WE signal can be set to H level and a signal input to the clocked inverter 2603 can be output. At this time, the TFT 49 that transmits the erase signal is turned off. Thus, the signal from the second latch 48 can be written to the pixel.

When the source driver performs the erasing operation, the WE signal is set to L level so that the signal input to the clocked inverter 2603 is not output. Then, the TFT 49 is turned on. In this manner, the signal lines S1 to Sm can be set to the potential of the power supply 53, and signals written to the pixels can be erased.

Note that the selection circuit 2602 shown in this embodiment can also be applied to the source driver 2501 shown in FIG.

Further, when the signal is a digital signal, the circuit can be represented by a logic gate. Therefore, in this embodiment, the circuit represented by the logic gate circuit is applied to the selection circuit 46 included in the source driver 43 shown in FIG. This is shown in FIG. In addition, the same code | symbol is used for the same location as the structure of the source driver 43 of FIG.

The source driver 2701 includes a pulse output circuit 44, a first latch 47, a second latch 48, and a selection circuit 2702. The selection circuit 2702 has a NOR gate 2704 and an inverter 2705. Note that as a signal input to one terminal of the NOR gate 2704 in each column of the selection circuit 2702, a signal obtained by inverting the WE signal by the inverter 2703 is input. When the source driver performs a write operation, the WE signal is set to the H level. Then, the signal is inverted by the inverter 2703, and the L level is input to one input terminal of the NOR gate 2704 of each column. A signal from each column of the second latch 48 is input to the other terminal. When the signal from the second latch 48 is at the H level, the output of the NOR gate becomes the L level, further inverted by the inverter 2705, and the H level is output to the source signal line. Then, the gate potential of the TFT 12 of the pixel selected by the gate line becomes H level, and the TFT 12 is turned on. When the signal from the second latch 48 is at the L level, the output of the NOR gate 2704 becomes the H level, and is further inverted by the inverter 2705 to output the L level to the source signal line. Then, the gate potential of the TFT 12 of the pixel selected by the gate line becomes L level, and the TFT 12 is turned off. Then, these potentials are accumulated in the capacitive element 16. Thus, a signal can be written to the pixel.

At the time of erase operation, the WE signal is set to L level. Then, it is inverted by the inverter 2703 and the H level is input to one input terminal of the NOR gate 2704 of each column. Then, regardless of the signal from the second latch 48 (that is, the input signal of the other input terminal of the NOR gate), the output of the NOR gate becomes L level, and is further inverted by the inverter 2705, and the source signal line has H The level is output. Then, the gate potential of the TFT 12 of the pixel selected by the gate line becomes H level, the capacitive element 16 is discharged, and the TFT 12 is turned off. Thus, the signal written in the pixel can be erased.

Note that the selection circuit 2702 shown in this embodiment can also be applied to the source driver 2501 shown in FIG.

In this embodiment, FIG. 28 shows an example in which the tristate buffer 87 and the protection circuit 88 included in the selection circuit 55 included in the first gate driver 41 shown in FIG. The tristate buffer 87 shown in FIG. 9 prevents the output of the other driver from obstructing when one of the first gate driver 41 and the second gate driver 42 charges and discharges the gate line Gy. Is. Accordingly, an enable circuit 2801 using an analog switch 2803 as shown in FIG. 28 may be used instead of the tristate buffer as long as it has the above functions. The protection circuit 2802 includes a rectifying element 2805 and a rectifying element 2806.

The enable circuit 2801 includes an analog switch 2803 and an inverter 2804. The analog switch 2803 switches on and off by the P2 signal, and sends the P1 signal to the gate line. That is, when one of the first gate driver 41 and the second gate driver 42 charges and discharges the gate line Gy, the first gate driver is used so that the output of the other driver does not hinder it. 41 and the P2 signal of the enable circuit 2801 of the second gate driver 42 are inverted signals.

The first gate driver 41 includes a first protection circuit (corresponding to the resistance element 72 in the illustrated configuration) connected to the input node of the pulse output circuit 54, and a second protection circuit provided in the lower stage of the selection circuit 46. It is characterized by having 2802. With the above characteristics, deterioration and destruction of the element due to static electricity can be suppressed. More specifically, a clock signal or a data signal input to the input node may contain noise, and this noise may momentarily give a high voltage or a low voltage to the element. However, the present invention having a protection circuit can suppress malfunction of the element, deterioration and destruction of the element.

Note that the protection circuit includes not only a resistance element and a transistor but also one or a plurality of types selected from a resistance element, a capacitor element, and a rectifier element. The rectifying element is a transistor or a diode in which a gate electrode and a drain electrode are connected. In this embodiment, the rectifier elements 2805 and 2806 are applied to the protection circuit 2802. However, the protection circuit 2802 may be composed of one or a plurality of elements selected from a resistor element, a resistor element, a capacitor element, and a rectifier element. In addition to the diode-connected transistor, a PN junction or PIN junction diode, a Schottky diode, or the like may be used as the rectifying element.

Next, the operation of the protection circuit will be briefly described. Here, the operation of the protection circuit 2802 included in the first gate driver 41 will be described.

First, it is assumed that a signal having a voltage higher than VDD is supplied from the output node of the enable circuit 2801 due to noise or the like. Then, a forward bias is applied to the rectifier element 2806, and the charge charged in the enable circuit 2801 is discharged to the power supply line that transmits VDD, and the potential of the gate line Gx is VDD or VDD + α (α is 0 or more) VDD + α means a potential higher than VDD).

On the other hand, it is assumed that a signal having a voltage lower than VSS is supplied from the output node of the enable circuit 2801. Then, a forward bias is applied to the rectifying element 2805, and the potential of the gate line Gx is VSS or VSS-α (α is a number of 0 or more, and VSS-α means a potential lower than VSS). Potential.

As described above, even if the voltage supplied from the output node of the enable circuit 2801 is instantaneously higher than VDD or lower than VSS due to noise or the like, the voltage applied to the gate line Gx is It will not be higher than VDD nor lower than VSS. Therefore, malfunction, damage, and destruction of the element due to noise, static electricity, and the like can be suppressed.

In this embodiment, an example in which the tristate buffer 87 and the protection circuit 88 included in the selection circuit 55 included in the first gate driver 41 shown in FIG. 4 are replaced with another configuration is shown in FIG. The tristate buffer 87 shown in FIG. 9 prevents the output of the other driver from obstructing when one of the first gate driver 41 and the second gate driver 42 charges and discharges the gate line Gy. Is. Accordingly, an enable circuit 2901 using a clocked inverter 2902 as shown in FIG. 29 may be used instead of the tristate buffer as long as it has the above functions. The protection circuit 2802 includes a rectifying element 2805 and a rectifying element 2806. In this configuration, a clocked inverter is applied instead of the analog switch of the enable circuit 2801 shown in the ninth embodiment, and the enable circuit 2801 and the protection circuit 2802 shown in FIG. Since it is the same as that, it abbreviate | omits.

In this embodiment, the selection signal line 52 in FIG. 4 will be described. The WE signal is input to the gate driver and the source driver via the selection signal line 52. At this time, it is necessary to pay attention to the timing of signals actually input to the pixels.

That is, the timing at which the selection signal sent from the gate signal line to the pixel is turned off (the timing at which the selection of the gate signal line is released), and the timing at which the video signal or the erasing signal sent from the source signal line to the pixel changes. Need to be considered. For example, if a video signal or an erasure signal is changed before the selection signal sent from the gate signal line to the pixel is turned off, the changed signal is input to the pixel. Therefore, it is important that the video signal and the erasure signal to be input to the pixel are not changed until the selection signal is turned off (until the selection of the gate signal line is released). After the selection signal is turned off (after the selection of the gate signal line is released), there is no problem even if the value changes to the value of the video signal or the erasing signal to be input to the next pixel.

Therefore, as shown in FIG. 30, a delay circuit 3000 may be provided before inputting the WE signal to the source driver 43. Then, the WE signal may be input to the gate driver as it is. As a result, when the WE signal changes, the WE signal is transmitted to the source driver with a delay by the delay circuit, so that the timing at which the video signal or erasure signal changes is delayed from the selection signal (the video signal or erasure signal changes). The timing can be made later than the timing at which the selection of the gate signal line is released). As a result, a correct signal can be input to the pixel. Note that FIG. 30 is a diagram schematically showing the same configuration as the display device of FIG.

Next, FIG. 31 shows an example of a delay circuit. Basically, the input signal may be output after being delayed. FIG. 31 shows an example in which a flip-flop circuit is used. Here, a flip-flop circuit 3101 as shown in FIG. 31 includes a clocked inverter 3102, a clocked inverter 3103, and an inverter 3104, and is generally called a delay flip-flop circuit (DFF). Clocked inverters 3102 and 3103 constituting the DFF operate in synchronization with a clock signal input thereto. For this reason, when one stage of the DFF is arranged as a delay circuit, the signal is delayed by the amount of the clock signal supplied to the DFF (only half the period of the clock signal).

FIG. 34 shows a timing chart. It can be seen that the output signal (WE ′ signal) from the DFF is delayed by a half time of the cycle of the clock signal with respect to the input signal (WE signal) to the DFF 3101.

Here, the clock signal input to the DFF 3101 of the delay circuit may be any signal. However, if an input signal can be used for another purpose, it is more efficient. Therefore, a clock signal input to the source driver may be used.

In the case of FIG. 31, the clock signal input to the DFF 3101 is delayed by a time corresponding to half the period of the clock signal. However, if more delay is desired, a plurality of stages of DFF 3101 are provided as shown in FIG. What is necessary is just to connect in series. It is possible to arbitrarily design the delay time by adjusting how many stages of DFF 3101 are connected. In FIG. 32, three DFFs are connected in series. Therefore, as shown in the timing chart of FIG. 35, the output signal (WE ″ signal) from the DFF is the input signal (WE signal) to the DFF for three times the half of the period of the clock signal. It can be seen that is delayed.

In FIGS. 31 and 32, a configuration using a DFF is shown; however, the present invention is not limited to this. Any configuration is applicable as long as it is a circuit used in a shift register.

As another method, the signal may be delayed by using a delay time when the signals are sequentially propagated through a plurality of circuits instead of being delayed in synchronization with the clock signal. The configuration in that case is shown in FIG. Here, a plurality of stages of inverters 3301 are connected to delay a signal. However, the delayed signal and the signal before being delayed may be input to the NAND 3302 and the output of the NAND 3302 may be used to narrow the pulse width of the signal. The inverted WE signal is returned by the inverter 3303.

The display device shown in FIG. 4 has a configuration in which the first gate driver 41 and the second gate driver are arranged so as to face each other with the pixel region 40 interposed therebetween. However, in this embodiment, one gate driver is provided. FIG. 36 shows a display device that operates in the same manner as the display device shown in FIG. In addition, the same code | symbol is used for the place with the same structure as the display apparatus shown in FIG.

The source driver 43 includes a pulse output circuit 44, a latch 45, and a selection circuit 46. The latch 45 has a first latch 47 and a second latch 48. The selection circuit 46 includes a TFT 49 and an analog switch 50. The TFT 49 and the analog switch 50 are provided in each column corresponding to the source line Sx. The inverter 51 is for generating an inverted signal of the WE signal (Write Erase), and may not be provided when an inverted signal of the WE signal is supplied from the outside.

The gate electrode of the TFT 49 is connected to the selection signal line 52, one of the source electrode and the drain electrode is connected to the source line Sx, and the other is connected to the power source 53. The analog switch 50 is provided between the second latch 48 and the source line Sx. That is, the input node of the analog switch 50 is connected to the second latch 48, and the output node is connected to the source line Sx. One of the two control nodes of the analog switch 50 is connected to the selection signal line 52, and the other is connected to the selection signal line 52 via the inverter 51. The potential of the power source 53 is a potential for turning off the TFT 12 included in the pixel 10. When the TFT 12 is N-type, the potential of the power source 53 is L level, and when the TFT 12 is P-type, the potential of the power source 53 is H level. To do.

The gate driver 3601 includes a first pulse output circuit 3603, a second pulse output circuit 3602, and a selection circuit 3604. The selection circuit 3604 includes NAND gates 3606 and 3607, inverters 3608, 3609, and 3611 and a NOR gate 3610 corresponding to each column of gate lines. The selection signal line 52 is branched and one selection signal line 52 a is connected to one terminal of the NAND gate 3606, and the other terminal of the NAND gate 3606 is connected to the first pulse output circuit 3603. The other selection signal line 52 b is connected to one terminal of a NAND gate 3607 through an inverter 3605, and the other terminal of the NAND gate 3607 is connected to a second pulse output circuit 3602. The output terminal of the NAND gate 3606 is connected to the input terminal of the inverter 3608, and the output terminal of the NAND gate 3607 is connected to the input terminal of the inverter 3609. The output terminals of the inverters 3608 and 3609 are connected to the input terminal of the NOR gate 3610, and the output terminal of the NOR gate 3610 is connected to the input terminal of the inverter 3611. That is, the signal input to the selection circuit 3604 from the selection signal line 52a and the signal input to the selection circuit 3604 from the selection signal line 52b are inverted.

Here, an operation method of the gate driver of this embodiment will be described.

When both the input terminals of the NAND gate 3606 or the NAND gate 3607 are at the H level, the gate line Gx receives an H level signal.

Here, the WE signal is set to the H level when a signal is written to the pixel. Then, the H level is input from the selection signal line 52a to one terminal of the NAND gate 3606. Therefore, the row of the gate line corresponding to the row where the H level is output from the first pulse output circuit 3603 to which the other terminal of the NAND gate 3606 is connected becomes the pixel row selected for writing. That is, the transistor 11 in the pixel row in which the signal is written is turned on. When the WE signal is at the H level, the analog switch of the selection circuit 46 is turned on, and the signal from the second latch 48 is output to the signal line Sx. In this way, charges are accumulated in the capacitor 16 that holds the gate potential of the TFT 12 that drives the pixel, and a signal can be written to the pixel.

At the time of erasing operation for erasing the signal written to the pixel, the WE signal is set to L level. Then, an H level is input from the selection signal line 52b to one terminal of the NAND gate 3607 via the inverter 3605. Therefore, the row of the gate line corresponding to the row where the H level is output from the second pulse output circuit 3602 to which the other terminal of the NAND gate 3607 is connected becomes the pixel row selected for erasing. That is, the transistor 11 in the pixel row to be erased is turned on. When the WE signal is at the L level, the TFT 49 of the selection circuit 46 is turned on, and the potential of the power supply 53 becomes the potential of the signal line Sx. In this way, the capacitor 16 that holds the gate potential of the TFT 12 that drives the pixel is discharged, and the signal written in the pixel can be erased.

The pulse output circuit 44 included in the source driver 43, the first pulse output circuit 3603 and the second pulse output circuit 3602 included in the gate driver 3601 correspond to a shift register or a decoder circuit including a plurality of flip-flop circuits. If a decoder circuit is applied as the pulse output circuits 44, 3602, 3603, the source line Sx or the gate line Gy can be selected at random. If the source line Sx or the gate line Gy can be selected at random, it is possible to suppress the generation of a pseudo contour that occurs when the time gray scale method is applied.

The configuration of the source driver 43 is not limited to the above description, and a level shifter and a buffer may be provided. The configuration of the gate driver 3601 is not limited to the above description, and a level shifter or a buffer may be provided. Although not described above, the source driver 43 and the gate driver 3601 have a protection circuit. The configuration described in Embodiment 3 can be used as the configuration of the driver having the protection circuit.

The delay circuit shown in FIGS. 31 to 33 shown in Embodiment 11 can be applied to the display device shown in FIG. 36 shown in this embodiment.

The display device of the present invention includes a power supply control circuit 63. The power supply control circuit 63 includes a power supply circuit 61 that supplies power to the light emitting element 13 and a controller 62. The power supply circuit 61 is connected to the pixel electrode of the light emitting element 13 through the TFT 12 and the power supply line Vx. The power supply circuit 61 is connected to the counter electrode of the light emitting element 13 through a power supply line.

When a forward bias voltage is applied to the light emitting element 13 and a current is caused to flow through the light emitting element 13 to emit light, the potential of the first power supply 17 becomes higher than the potential of the second power supply 18. A potential difference between the first power supply 17 and the second power supply 18 is set.
On the other hand, when a reverse bias voltage is applied to the light emitting element 13, the first power supply 17 and the second power supply are set so that the potential of the first power supply 17 is lower than the potential of the second power supply 18. 18 potentials are set. Such setting of the power supply potential is performed by supplying a predetermined signal from the controller 62 to the power supply circuit 61.

In the present invention, by applying a reverse bias voltage to the light emitting element 13 using the power supply control circuit 63, deterioration with time of the light emitting element 13 can be suppressed and reliability can be improved. In addition, the light emitting element 13 may have an initial failure in which the anode and the cathode are short-circuited due to adhesion of foreign matters, pinholes due to fine protrusions on the anode or the cathode, and non-uniformity of the electroluminescent layer. When such an initial failure occurs, the pixel is not turned on or off according to the signal, and almost all of the current flows through the short-circuited portion of the anode and the cathode, causing the phenomenon that the entire element is extinguished, or a specific pixel There is a problem that the image is not displayed satisfactorily due to a phenomenon that does not light or not light. However, according to the configuration of the present invention, since a reverse bias can be applied to the light emitting element, a current is supplied locally only to the short-circuited portion of the anode and the cathode, and the short-circuited portion is heated. It can be insulated by oxidation or carbonization. As a result, even if an initial failure occurs, the failure can be resolved and an image can be displayed favorably. It should be noted that such initial failure insulation is preferably performed before shipment. In addition to the initial failure, a new short circuit between the anode and the cathode may occur over time. Such a defect is also called a progressive defect, but according to the configuration of the present invention, a reverse bias can be periodically applied to the light emitting element, so even if a progressive defect occurs, the defect is eliminated, An image can be displayed satisfactorily. Note that there is no particular limitation on the timing at which the reverse bias voltage is applied to the light emitting element 13.

The display device of the present invention includes a monitor circuit 64 and a control circuit 65. The monitor circuit 64 operates based on the ambient temperature (hereinafter referred to as environmental temperature). The control circuit 65 has a constant current source and a buffer. In the illustrated configuration, the monitor circuit 64 includes a monitor light emitting element 66.

The control circuit 65 supplies a signal for changing the power supply potential to the power supply control circuit 63 based on the output of the monitor circuit 64. The power supply control circuit 63 changes the power supply potential supplied to the pixel region 40 based on the signal supplied from the control circuit 65. The present invention having the above-described configuration can improve the reliability by suppressing the fluctuation of the current value caused by the change in the environmental temperature. Note that the detailed configuration of the monitor circuit 64 and the control circuit 65 can be the configuration shown in the third embodiment.

In the display device of the present invention which performs constant voltage driving, when the luminance of the light emitting element is 500 cd / m ² and the aperture ratio of the pixel is 50%, the power consumption is 1 W or less (950 mW). On the other hand, the power consumption of the display device that performs constant current driving was approximately 2 W (2040 mW) when the luminance of the light emitting element was 500 cd / m ² and the aperture ratio of the pixel was 25%. That is, it can be seen that power consumption can be reduced by adopting constant voltage driving. Note that power consumption can be reduced to 1 W or less, preferably 0.7 W or less by employing constant voltage driving.
Note that the above power consumption value is the power consumption of only the pixel region, and does not include the power consumption of the drive circuit portion. In both cases, the display duty ratio of the time gradation is 70%.

In addition, the number of pixels in the pixel region of the display device that performs the constant voltage drive and the display device that performs the constant current drive, in which the power consumption is measured, is 240 × 3 × 320, and both are the same.

4A and 4B illustrate a pixel included in a display device of the present invention and a cross-sectional structure thereof. 4A and 4B each illustrate a mask layout of a pixel included in a display device of the present invention. 4A and 4B each illustrate a mask layout of a pixel included in a display device of the present invention. FIG. 6 illustrates a structure of a display device of the present invention. FIG. 6 illustrates a structure of a source driver included in a display device of the present invention. FIG. 6 illustrates a structure of a source driver included in a display device of the present invention. FIG. 6 illustrates a structure of a source driver included in a display device of the present invention. 6A and 6B illustrate a structure of a gate driver included in a display device of the present invention. 6A and 6B illustrate a structure of a gate driver included in a display device of the present invention. The figure explaining the temperature compensation function of this invention. FIG. 9 illustrates operation of a display device of the present invention. The figure explaining a time gradation system. The figure explaining a time gradation system. 4A and 4B each illustrate a mask layout of a pixel included in a display device of the present invention. FIG. 14 illustrates a panel which is one embodiment of the display device of the present invention. FIG. 14 illustrates a panel which is one embodiment of the display device of the present invention. FIG. 14 illustrates an electronic device including the display device of the invention. FIG. 9 illustrates a structure of a protection circuit. 4A and 4B illustrate a pixel included in a display device of the present invention and a cross-sectional structure thereof. FIG. 9 illustrates a compensation circuit of the present invention. 3A and 3B illustrate temperature characteristics of a light-emitting element. FIG. 9 illustrates a compensation circuit of the present invention. FIG. 9 illustrates a compensation circuit of the present invention. FIG. 9 illustrates a compensation circuit of the present invention. 7 shows an example of a source driver that can be applied to the present invention. 7 shows an example of a source driver that can be applied to the present invention. 7 shows an example of a source driver that can be applied to the present invention. 6A and 6B illustrate a structure of a gate driver included in a display device of the present invention. 6A and 6B illustrate a structure of a gate driver included in a display device of the present invention. The schematic diagram of the display apparatus of this invention provided with the delay circuit. 6 shows an example of a delay circuit that can be applied to the present invention. 6 shows an example of a delay circuit that can be applied to the present invention. 6 shows an example of a delay circuit that can be applied to the present invention. 4 is a timing chart of a delay circuit that can be applied to the present invention. 4 is a timing chart of a delay circuit that can be applied to the present invention. FIG. 6 illustrates a structure of a display device of the present invention.

Claims (26)

A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
The capacitive element has a first semiconductor layer, an insulating layer, and a conductive layer,
The first semiconductor layer, the second semiconductor layer of the first transistor, and the third semiconductor layer of the second transistor are provided over a base insulating layer;
The insulating layer is provided on the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer,
The display device, wherein the conductive layer, the first gate electrode of the first transistor, and the second gate electrode of the second transistor are provided over the insulating layer. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
The capacitor element includes a first conductive layer, a first insulating layer, and a second conductive layer,
The first conductive layer, the first gate electrode of the first transistor, and the second gate electrode of the second transistor are provided on a second insulating layer;
The first insulating layer is provided on the first conductive layer,
The second conductive layer, the first wiring connected to the source or drain electrode of the first transistor, and the second wiring connected to the source or drain electrode of the second transistor are A display device provided over the first insulating layer. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
The capacitor element includes a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer,
The first semiconductor layer, the second semiconductor layer of the first transistor, and the third semiconductor layer of the second transistor are provided on the same base insulating layer;
The first insulating layer is provided on the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer,
The first conductive layer, the first gate electrode of the first transistor, and the second gate electrode of the second transistor are provided on the first insulating layer;
The second insulating layer is provided on the first conductive layer, the first gate electrode, and the second gate electrode,
The second conductive layer, the first wiring connected to the source or drain electrode of the first transistor, and the second wiring connected to the source or drain electrode of the second transistor are A display device provided on the second insulating layer. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
A first insulating layer is provided on top of the first transistor and the second transistor;
A second insulating layer is provided on the first insulating layer;
A display device, wherein the first electrode of the light-emitting element is provided over the second insulating layer. In claim 4,
The display device according to claim 1, wherein a width in a column direction of the insulating layer disposed on the capacitor element is 10 to 25 μm. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
An insulating layer is provided to cover an end of the pixel electrode of the light emitting element;
The display device, wherein the insulating layer has a light shielding property. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
One of the first electrode and the second electrode of the light-emitting element has reflectivity, and the other has translucency. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
The display device is characterized in that the first electrode and the second electrode of the light-emitting element have a light-transmitting property. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
The first electrode of the light emitting element is connected to the first power supply line through the second transistor,
A second electrode of the light emitting element is connected to a second power line;
A display device comprising: a power supply control circuit that sets a potential of the first power supply line and a potential of the second power supply line so that a reverse bias is applied to the light emitting element. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
A display device comprising: a monitor circuit that operates based on an environmental temperature; and a power supply control circuit that sets a power supply potential supplied to the pixel region based on an output of the monitor circuit. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
A monitor circuit that operates based on an environmental temperature; and a power supply control circuit that sets a power supply potential to be supplied to the pixel region based on an output of the monitor circuit;
The display device, wherein the monitor circuit includes a monitor light emitting element. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
The light-emitting element includes a material that emits red light from a triplet excited state, a material that emits green light from a singlet excited state, or a material that emits blue light from a singlet excited state. . A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
The light emitting element includes a material that emits red light from a triplet excited state, a material that emits green light from a triplet excited state, or a material that emits blue light from a singlet excited state. . A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
In the pixel region, a plurality of power lines are provided in the column direction,
A display device, wherein the power supply line is shared between adjacent pixels. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
The source driver includes a pulse output circuit, a latch, and a selection circuit,
A first protection circuit connected to an input node of the pulse output circuit;
A second protection circuit provided between the pulse output circuit and the latch;
A third protection circuit provided between the selection circuit and the pixel region;
Each of the first to third protection circuits has one or more types selected from a resistor element, a capacitor element, and a rectifier element. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
A protection circuit provided between the source driver and the connection film;
The display device according to claim 1, wherein the protection circuit includes one or more types selected from a resistance element, a capacitance element, and a rectifying element. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
Each of the first gate driver and the second gate driver includes a pulse output circuit and a selection circuit,
A first protection circuit connected to an input node of the pulse output circuit;
A second protection circuit provided between the selection circuit and the pixel region;
Each of the first protection circuit and the second protection circuit has one or more types selected from a resistor element, a capacitor element, and a rectifier element. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
One or both of the first gate driver and the second gate driver, and a protection circuit provided between the connection films,
The display device according to claim 1, wherein the protection circuit includes one or more types selected from a resistance element, a capacitance element, and a rectifying element. In any one of Claims 15 thru / or Claim 18,
The display device, wherein the rectifying element is a transistor or a diode in which a gate electrode and a drain electrode are connected. In claim 15 or claim 17,
The display device, wherein the pulse output circuit is a plurality of flip-flop circuits or decoder circuits. A pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver;
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
A monitor circuit that operates based on an environmental temperature, and a control circuit that sets a power supply potential to be supplied to the pixel region based on an output of the monitor circuit;
The monitor circuit has a monitor light emitting element,
The display device, wherein the control circuit is a switching regulator. A pixel region including a plurality of pixels, a source driver, a first gate driver for selecting a pixel row to which a signal is written, and a second gate driver for selecting a pixel row to erase a signal written to the pixel And
Each of the plurality of pixels holds a light emitting element, a first transistor that controls input of a video signal to the pixel, a second transistor that controls light emission or non-light emission of the light emitting element, and the video signal. A capacitive element;
The source driver includes a first selection circuit that selects an operation of outputting a signal for writing to the pixel or an operation of outputting a signal for erasing the signal written to the pixel,
Each of the first gate driver and the second gate driver includes a second selection circuit that selects which of the first gate driver and the second gate driver operates,
A delay circuit that outputs a signal input to the second selection circuit that determines which one of the first gate driver and the second gate driver performs an operation by delaying the signal to the first selection circuit. A display device comprising: 23. The display device according to claim 22, wherein the delay circuit includes a plurality of flip-flop circuits. 24. In any one of claims 1 to 23,
The first wiring connected to the source or drain electrode of the first transistor and the second wiring connected to the source or drain electrode of the second transistor have a thickness of 500 nm to 1300 nm. A display device. 24. In any one of claims 1 to 23,
A gate electrode of the first transistor is connected to the first gate driver and the second gate driver via a gate line;
One of the source electrode and the drain electrode of the first transistor is connected to the source driver through a source line,
The other of the source electrode and the drain electrode of the first transistor is connected to the gate electrode of the second transistor,
One of the source electrode and the drain electrode of the second transistor is connected to the first electrode of the light emitting element,
A display device, wherein the other of the source electrode and the drain electrode of the second transistor is kept at a constant potential. An electronic apparatus using the display device according to any one of claims 1 to 24.

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