JP2005333118A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, especially using a TFT having an LDD region, represented by a TFT manufacturable in a simplified process, and a liquid crystal display and an EL display, and their manufacturing methods. <P>SOLUTION: The semiconductor device comprises a channel region, a semiconductor layer composed of a pair of impurity regions and a pair of low-concentration impurity layers, and a gate electrode layer of a monolayer structure or laminated layer structure having film thickness differences which is contacted with the semiconductor layer via a gate insulation film. The gate electrode layer having film thickness differences is easily formed by the liquid-drop discharge method, the advantage of which is utilized to its maximum. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an active element such as a transistor formed over a large-area glass substrate, a liquid crystal display device (hereinafter also referred to as “LCD”) and an EL display device including the active element, and a method for manufacturing the same. In particular, the present invention relates to a thin film transistor, a liquid crystal display device, an EL display device, and a manufacturing method thereof using a droplet discharge method typified by an inkjet method.

  Conventionally, a so-called active matrix liquid crystal display panel composed of thin film transistors (hereinafter also referred to as “TFTs”) on a glass substrate is a light exposure process using a photomask, as in the manufacturing technology of a semiconductor integrated circuit. Thus, it has been manufactured by patterning various thin films.

  Until now, a production technique has been adopted in which a plurality of liquid crystal display panels are cut out from a single mother glass substrate and mass production is efficiently performed. The size of the mother glass substrate was increased from 300 x 400 mm of the first generation in early 1990 to the fourth generation in 2000 and increased to 680 x 880 mm or 730 x 920 mm. Production technology has progressed so that

  When the size of the glass substrate or the display panel is small, the patterning process can be performed relatively easily by the exposure apparatus. However, as the substrate size increases, the entire surface of the display panel can be obtained by a single exposure process. Cannot be processed simultaneously. As a result, a method has been developed in which a region coated with a photoresist is divided into a plurality of regions, an exposure process is performed for each predetermined block region, and the entire substrate is exposed by sequentially repeating the exposure process (for example, , See Patent Document 1).

In addition, when forming an active matrix substrate composed of a plurality of TFTs used in an active matrix LCD or EL display device, the electric field concentrated on the edge of the drain region of the TFT is relaxed, so-called hot carriers (hot electrons or hot electrons). In order to suppress the hot hole effect, a technique of providing a relatively low-concentration impurity region (LDD region; Lightly Doped Drain Regions) formed at the ends of the source and drain regions is used (for example, Patent Documents). 2).
Japanese Patent Laid-Open No. 11-326951 Japanese Patent Laid-Open No. 10-135468

  However, the size of the glass substrate is further increased to 1000 × 1200 mm or 1100 × 1300 mm in the fifth generation, 1500 × 1800 mm in the sixth generation, 2000 × 2200 mm in the seventh generation, 2500 × 3000 mm class in the eighth generation, In addition, when a larger size is assumed, it is difficult to manufacture a display panel with high productivity and low cost by a process using only a conventional patterning method. That is, if exposure processing is performed many times by continuous exposure, the processing time increases, and it has become difficult to cope with an increase in the size of the substrate.

  Further, in the case where an LDD region is provided in a TFT, it is necessary to separately form an insulating film serving as a mask or to devise the shape of the gate electrode layer in order to provide a concentration difference in impurities implanted into the semiconductor film. In addition, the patterning process naturally increases, and the process becomes complicated. In addition, as the number of processes increases, there are naturally problems that the operating cost of the apparatus and the material cost increase, and that it is required to process a large amount of waste liquid containing heavy metals and insulators. .

  The present invention has been made in view of such a situation, and a semiconductor device typified by a TFT that can be manufactured by a simplified process, a liquid crystal display device and an EL display device including the semiconductor device, and those It is an object to provide a manufacturing method. In particular, it is an object to provide a semiconductor device using a TFT having an LDD region, a liquid crystal display device including the semiconductor device, and an EL display device in a simplified process.

  In order to solve the above problems, a semiconductor device according to the present invention is formed in contact with a semiconductor layer including a channel region, a pair of impurity regions, and a pair of low-concentration impurity regions, and a gate insulating film. In addition, a gate electrode layer having a single layer structure or a stacked structure having a difference in film thickness is included.

  The pair of low-concentration impurity regions are formed so as to overlap a region having a smaller thickness in the gate electrode layer having a thickness difference.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a gate insulating film formed over a semiconductor layer, and a single-layer structure or a stacked structure having a film thickness difference over the gate insulating film. A gate electrode layer is formed, and a pair of impurity regions and a pair of low-concentration impurity regions are formed by introducing impurities into the semiconductor layer using the gate electrode layer as a mask.

  The pair of low-concentration impurity regions are formed so as to overlap with a region having a smaller thickness in the gate electrode layer having a thickness difference.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes forming a gate insulating film over a semiconductor layer, forming a gate electrode layer over the gate insulating film, and firing the gate electrode layer. A feature is that impurity elements having different concentrations are introduced into the semiconductor layer by utilizing a change in width before and after, thereby forming a pair of impurity regions and a pair of low-concentration impurity regions.

  Since the present invention includes a gate electrode layer having a single layer structure or a stacked structure having a film thickness difference, a low-concentration impurity region is easily formed using the film thickness difference of the gate electrode layer. be able to. In addition, the impurity region and the low-concentration impurity region can be formed simultaneously by doping the impurity element once. As a result, a semiconductor device such as a TFT having a structure in which a low concentration impurity region overlaps the gate electrode layer (Lov structure) can be easily formed.

  Further, the present invention is characterized in that it includes a gate electrode layer having a single layer structure or a stacked structure having a film thickness difference. Such a gate electrode layer can be simplified by adopting a droplet discharge method in particular. The convenience of the droplet discharge method can be utilized to the maximum.

  In addition, in the present invention, by adopting the droplet discharge method positively, the process can be simplified, the material cost can be reduced, and a semiconductor device with high throughput and high yield, and light emission including the same A device (typically, an EL display device) or a liquid crystal display device can be provided. In particular, even if the size of the glass substrate is increased to the sixth generation (1500 × 1800 mm), the seventh generation (2000 × 2200 mm), the eighth generation (2500 × 3000 mm class), or larger, the production A display panel can be manufactured with good performance at low cost. Further, it is not necessary to treat a large amount of waste liquid containing heavy metal as a conductive material, and the present invention is significant from the viewpoint of environmental considerations.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and various changes can be made in form and details without departing from the spirit and scope of the present invention. For example, the present invention can be implemented by appropriately combining each of the present embodiment and this example.

  In addition, the present invention provides a method for manufacturing any semiconductor device, a method for manufacturing a liquid crystal display device, and a method for manufacturing an EL display device by positively using a maskless process such as a droplet discharge method. It is not necessary to perform this process by a maskless process, and it is sufficient that the maskless process is included in at least a part of the processes. Therefore, hereinafter, even when only a droplet discharge method is shown, it can be replaced with another manufacturing method including a conventional patterning step.

(Embodiment 1)
In the present embodiment, an embodiment of a configuration of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIGS. Here, a top gate TFT will be described as an example.

  First, the semiconductor layer 101 is formed over the substrate 100 (FIG. 1A). The semiconductor layer 101 is formed using an amorphous semiconductor, a crystalline semiconductor, or a semi-amorphous semiconductor. In any case, a semiconductor film containing silicon, silicon germanium (SiGe), or the like as a main component can be used. In particular, a semi-amorphous semiconductor containing silicon as a main component is referred to as SAS (semi-amorphous silicon), microcrystalline silicon, or microcrystalline silicon. The semiconductor layer 101 can be formed by a CVD method, a sputtering method, or the like. Note that the thickness of the semiconductor layer 101 is preferably 10 to 100 nm. Alternatively, the semiconductor layer 101 may be formed using a substrate such as a silicon wafer or an SOI substrate (such as a SIMOX substrate).

When a crystalline semiconductor film is used, after processing the amorphous semiconductor film with a solution containing a catalyst such as nickel, a crystalline silicon semiconductor film is obtained by a thermal crystallization process at 500 to 750 ° C., and further crystallized by laser crystallization. It can be obtained by improving the sex. A crystalline semiconductor film can also be obtained by directly forming a polycrystalline semiconductor film by LPCVD (low pressure CVD) as a source gas of disilane (Si ₂ H ₆ ) and germanium fluoride (GeF ₄ ). it can. The gas flow rate ratio is Si ₂ H ₆ / GeF ₄ = 20 / 0.9, the film formation temperature is 400 to 500 ° C., and He or Ar is used as the carrier gas, but the gas flow ratio, film formation temperature, and carrier gas are used. Is not limited to these conditions.

  Note that as the substrate 100, a glass substrate, a quartz substrate, a substrate formed of an insulating material such as alumina, a plastic substrate having heat resistance that can withstand a processing temperature in a later process, or the like can be used. In this case, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), etc. (x, y = 1, 2,... ), A base insulating film for preventing diffusion of impurities and the like from the substrate side may be formed. In addition, a substrate in which an insulating film such as silicon oxide or silicon nitride is formed on the surface of a metal such as stainless steel or a semiconductor substrate can also be used.

Next, a resist 102 is formed over the semiconductor layer 101 (FIG. 1A). The resist 102 is preferably formed by discharging a composition containing a resist material from the nozzle 120. However, the resist 102 may be formed by patterning as in the prior art. Then, the semiconductor layer 101 is etched using the resist 102 as a mask, so that the island-shaped semiconductor layer 103 is formed (FIG. 1B). As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ , NF ₃ , CHF ₃ , or the like, or O ₂ is used. Although used, it is not limited to these. The etching may use atmospheric pressure plasma.

Next, the gate insulating film 104 is formed over the island-shaped semiconductor layer 103 (FIG. 1B). As the gate insulating film, silicon oxide (SixOy, for example, SiO ₂ ), silicon nitride (SixNy, for example, Si ₃ N ₄ ), silicon oxynitride (SiOxNy or SiNxOy), alumina (Al ₂ O ₃ ), tantalum oxide (Ta ₂₎ Any insulating film such as O ₅ ), lanthanum oxide (La ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), silicate (ZrAlxOy), and aluminate (HfAlxOy) can be used. Further, a structure in which these materials are stacked in two or more layers may be employed.

  Next, a first gate electrode layer 105 is formed over the gate insulating film 104 by discharging a composition containing a first conductive material by a droplet discharge method using a nozzle 121 (FIG. 1 ( C)).

  Next, the second gate electrode layer 106 is formed on the first gate electrode layer 105 by discharging a composition containing the second conductive material by a droplet discharge method using the nozzle 122 ( FIG. 1D). Here, as illustrated in FIG. 1D, the second gate electrode layer 106 is made narrower than the first gate electrode layer 105. The second gate electrode layer 106 is wider than the first gate electrode layer 105, and the second gate electrode layer 106 completely covers the first gate electrode layer 105. It may be formed.

  In any case, a low concentration impurity region is formed through the first gate electrode layer 105 in an impurity element doping step which will be described later.

  Here, different nozzles 121 and 122 are used in forming the first and second gate electrode layers. However, the first and second gate electrode layers are formed by changing discharge conditions using the same nozzle. It may be formed.

  There are no particular restrictions on the thickness of the first and second gate electrode layers. However, in the case where the width of the second gate electrode layer 106 is narrower than the width of the first gate electrode layer 105, the first gate electrode layer 105 can be made as easy as possible to inject impurities into the semiconductor layer. The second gate electrode layer 106 is preferably as thin as possible so that impurities are not implanted into the channel region. On the other hand, when the width of the second gate electrode layer 106 is wider than the width of the first gate electrode layer 105, the opposite is true. Note that the first or second gate electrode layer may have a stacked structure so that impurities are not implanted into the channel region.

  Note that the droplet discharge method means a method of forming a predetermined pattern by discharging a composition containing a predetermined conductive material from the pores, and typically includes an inkjet method, but is not limited thereto. In addition, dispensing methods, screen printing, offset printing, and the like are also included. Hereinafter, as the composition, any material that can be discharged and formed by a droplet discharge method, such as a conductive material, a semiconductor material, an organic semiconductor material, an insulating material (including both organic and inorganic), an organic material, and an inorganic material. Is included. Here, as typical organic materials and inorganic materials, LCD alignment films, color filters, spacers, light emitting layers in EL light emitting elements, electron transport layers, electron injection layers, hole transport layers, hole injection layers And color filters. Hereinafter, a composition containing these materials may be referred to as an ink, a droplet, or a paste (in particular, a nano paste when a material having a nano (nm) order size is included).

  Various materials can be selected as the first or second conductive material depending on the function of the conductive film. Typical examples include AgCu, Au, Ni, Pt, Cr, Al, W, Ta, Mo, Zn, Fe, In, Ti, Si, Ge, tin (Sn), palladium (Pd), iridium (Ir ), Rhodium (Rh), ruthenium (Ru), rhenium (Re), tellurium (Te), cadmium (Cd), zirconium (Zr), barium (Ba), antimony lead, tin / antimony oxide, fluorine-doped zinc oxide, Carbon, graphite, glassy carbon, lithium, beryllium, sodium, magnesium, potassium, calcium, scandium, manganese, zirconium, gallium, niobium, sodium-potassium alloy, magnesium / copper mixture, magnesium / silver mixture, magnesium / aluminum mixture, magnesium / Indium mixture, a Minium / aluminum oxide mixture, lithium / aluminum mixture, etc., silver halide fine particles or the like, or dispersible nanoparticles, or indium tin oxide (ITO) used as a transparent conductive film, ITO or silicon oxide Indium Tin Oxide (ITSO: Indium Tin Oxide), Zinc Oxide (ZnO), Zinc Oxide with Addition of Gallium (GZO), Indium Zinc Oxide Mixed with 2-20% Zinc Oxide (IZO: Indium Zinc Oxide), organic indium, organic tin, titanium nitride, an alloy of Al, C, Ni, or the like can be used.

  Note that when copper is used, a barrier film may be provided as a countermeasure against impurities. As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone may be used. Here, as a barrier film in the case of using copper as a wiring, an insulating or conductive material containing nitrogen such as silicon nitride, silicon oxynitride, aluminum nitride, titanium nitride, or tantalum nitride (TaN) is used. These may be formed by a droplet discharge method.

  Here, the first and second gate electrode layers are formed of different materials (for example, the first gate electrode layer is TaN and the second gate electrode layer is W). Good. Further, the materials may be appropriately changed according to the line width and length. For example, a relatively large area such as the first gate electrode layer in FIGS. 1C and 1D uses an inexpensive material such as Cu or Al, and the second gate electrode layer has a low resistance. Ag can be used.

  The diameter of the nozzle for discharging the composition used for the droplet discharge means described above is set to 0.1 to 50 μm (preferably 0.6 to 26 μm), and the composition discharged from the nozzle is discharged. The amount is preferably set to 0.00001 pl to 50 pl (preferably 0.0001 to 40 pl). This discharge amount increases in proportion to the size of the nozzle diameter. In addition, the distance between the object to be processed and the nozzle outlet is preferably as close as possible in order to drop the liquid droplets at a desired location, and is preferably set to about 0.1 to 2 mm. In addition, the ejection amount can be controlled by changing the pulse voltage applied to the piezoelectric element without changing the nozzle diameter. These discharge conditions are preferably set so that the line width of the gate electrode layer is about 10 μm or less.

  Note that the viscosity of the composition used for the droplet discharge method is preferably 300 mPa · s or less, in order to prevent drying and to smoothly discharge the composition from the discharge port. Note that the viscosity, surface tension, and the like of the composition may be appropriately adjusted according to the solvent to be used and the application. For example, the viscosity of a composition in which ITO, ITSO, organic indium, or organic tin is dissolved or dispersed in a solvent is 5 to 50 mPa · s, and the viscosity of a composition in which silver is dissolved or dispersed in a solvent is 5 to 20 mPa · s. The viscosity of a composition in which gold is dissolved or dispersed in a solvent is 10 to 20 mPa · s.

  Although depending on the diameter of each nozzle and the desired pattern shape, the diameter of the conductive material particles is preferably as small as possible for preventing nozzle clogging and producing a high-definition pattern. 1 μm or less is preferable. The composition is formed by a known method such as an electrolytic method, an atomizing method, or a wet reduction method, and its particle size is generally about 0.5 to 10 μm. However, when formed in a gas evaporation method, the nanomolecules protected by the dispersant are as fine as about 7 nm, and the nanoparticles are aggregated in the solvent when the surface of each particle is covered with a coating agent. And stably disperse at room temperature and shows almost the same behavior as liquid. Therefore, it is preferable to use a coating agent.

  Alternatively, the gate electrode layer may be formed by discharging a composition containing particles in which one conductive material is covered with another conductive material. At this time, it is desirable to provide a buffer layer between the two conductive materials. For example, as shown in FIG. 19, a particle structure in which a buffer layer 312 made of Ni or NiB (nickel boron) is provided between Cu 310 and Ag 311 in a particle in which the periphery of Cu 310 is covered with Ag 311 (FIG. 19A). (FIG. 19B).

  Note that the first and second gate electrode layers are generally formed by performing heat treatment after discharging the composition. For example, the film is formed by drying at 100 ° C. for 3 minutes and further baking at 200 to 350 ° C. for 15 to 30 minutes in an atmosphere containing nitrogen and / or oxygen. This heat treatment may be performed every time the first conductive material and the second conductive material are discharged, or may be performed at a time after the first conductive material and the second conductive material are discharged.

  Here, in the case where the gate electrode layer is formed by a droplet discharge method, a mechanism by which the film thickness of the gate electrode layer is reduced by the subsequent heat treatment will be described.

  When the gate electrode layer is formed by a droplet discharge method, the composition (droplet) discharged from the nozzle is generally obtained by dispersing or dissolving a conductive material constituting the gate electrode layer in an organic solvent. In addition, the composition contains a dispersant and a thermosetting resin called a binder. Here, the dispersant has a function of uniformly distributing the conductive particles in the solvent, and the binder has a function of preventing generation of cracks and uneven baking during firing. Then, by the drying or baking step, evaporation of the organic solvent, decomposition and removal of the dispersant, and curing shrinkage by the binder proceed simultaneously, so that the conductive particles are fused and the composition is cured. At this time, the conductive particles grow from the nano level to several tens to hundreds of tens of nanometers, and are fused together and chained together to form a metal chain. On the other hand, most of the remaining organic components (about 80 to 90%) are pushed out of the metal chain, and as a result, from the conductive layer (gate electrode layer) containing the metal chain and the organic component covering the surface. A layer (hereinafter simply referred to as “organic layer”) is formed.

  When the conductive paste is fired in an atmosphere containing nitrogen and oxygen, oxygen contained in the gas (including oxygen contained as an atmospheric component in the heating atmosphere) and carbon, hydrogen, etc. contained in the organic layer. By reacting, the organic layer can be removed. Further, when oxygen is not contained in the firing atmosphere, the organic layer can be removed separately by oxygen plasma treatment or the like.

  In this way, the conductive layer is baked or dried in an atmosphere containing nitrogen and / or oxygen, and then treated with oxygen plasma to remove the organic layer, thereby reducing the thickness and width of the gate electrode layer. In addition, the remaining gate electrode layer can be smoothed, thinned, and reduced in resistance.

  Note that since the solvent in the composition is volatilized by discharging the composition containing the conductive material under reduced pressure, the time for subsequent heat treatment (drying or baking) can be shortened. Note that when the oxygen composition ratio in the atmosphere is 10 to 25%, the thickness and width of the gate electrode layer can be efficiently reduced. In addition, the gate electrode layer can be made smoother, thinner, and lower in resistance.

  Next, the impurity element 109 is introduced into the island-shaped semiconductor layer 103 by an ion implantation method or the like using the first gate electrode layer 105 and the second gate electrode layer 106 as a mask (FIG. 2A). The impurity element 109 may be an n-type impurity element or a p-type impurity element. As the n-type impurity element, for example, phosphorus (P), arsenic (As), and antimony (Sb) can be used. For example, boron (B) can be used as the p-type impurity element.

  By introduction of the impurity element 109, a pair of impurity regions 110 is formed in a portion of the island-shaped semiconductor layer 103 that does not overlap with the first gate electrode layer 105 and the second gate electrode layer 106. On the other hand, the impurity element 109 is introduced through the first gate electrode layer 105 into a portion of the island-shaped semiconductor layer 103 that overlaps only with the first gate electrode layer 105, thereby forming a pair of low-concentration impurities. Region 111 is formed. The pair of impurity regions 110 constitute a source region or a drain region. A channel region 112 is formed between the pair of low-concentration impurity regions 111 (FIG. 2A).

  Here, the low-concentration impurity region relaxes the electric field concentrated on the end portion of the source or drain region in the transistor, and suppresses the so-called hot carrier (hot electron or hot hole) effect so as to suppress the end portion of the source or drain region. Is a relatively low-concentration impurity region. Note that the impurity implanted into the source or drain region (high concentration impurity region) and the low concentration impurity region may be the same or different. As a typical low-concentration impurity region, there is an LDD region (Lightly Doped Drain). In addition, in order to alleviate the electric field in the vicinity of the drain, there is a transistor having a so-called double drain structure (DDD) composed of a relatively shallow high-concentration region and a low-concentration region surrounding the high-concentration region. The low concentration region is also included in the low concentration impurity region.

  Next, a cap insulating film 113 for protecting the TFT is formed over the second gate electrode layer 106 (FIG. 2B). Although the same material as that of the gate insulating film 104 can be used, it is preferable to use a silicon nitride film or a silicon oxynitride film in order to prevent entry of impurities such as O, C, and Na. The cap insulating film 113 is not essential, but it is desirable to form the cap insulating film 113 as much as possible in order to protect the TFT from mixing of impurities.

  Next, an interlayer insulating film 114 is formed over the entire surface of the substrate over the second gate electrode layer 106 (when the cap insulating film 113 is formed) (FIG. 2B). As the interlayer insulating film 114, a photosensitive or non-photosensitive organic material such as polyimide, acrylic, polyamide, resist, or benzocyclobutene, siloxane (a skeleton structure is formed by a bond of silicon and oxygen, and at least a substituent is included. A heat-resistant organic resin such as an organic group containing hydrogen (eg, an alkyl group or aromatic hydrocarbon), a fluoro group, or an organic group containing at least hydrogen and a fluoro group can be used. Further, carbon black (CB) may be mixed into these materials.

  As a forming method, depending on the material, spin coating, dipping, spray coating, droplet discharge method (inkjet method, dispensing method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. Can be adopted. Alternatively, an SOG film obtained by a coating method (for example, an SiOx film containing an alkyl group) can also be used. In addition, an inorganic material may be used, in which case silicon oxide, silicon nitride, silicon oxynitride, a film containing carbon such as DLC (diamond-like carbon) or carbon nitride (CN), PSG (phosphorus glass), BPSG (phosphorus boron glass), an alumina film, or the like can be used. As a formation method, a plasma CVD method, a low pressure CVD (LPCVD) method, an atmospheric pressure plasma CVD, or the like can be used. Note that these insulating films may be stacked.

Next, using the patterned resist as a mask, the interlayer insulating film 114, the cap insulating film 113, and the gate insulating film 104 are etched to form contact holes 115 (FIG. 2C). Here, plasma etching is employed, and as the etching gas, chlorine gas such as Cl ₂ , BCl ₃ , SiCl _4, CCl _4, etc., CF ₄ , SF ₆ , NF ₃ , CHF _3, etc. are representative. fluorine-based gas, or with O _2, but is not limited thereto. The etching may use atmospheric pressure plasma.

  Note that the interlayer insulating film 114 may be selectively formed by a droplet discharge method without forming a region where a contact hole is to be formed without forming the interlayer insulating film 114 over the entire surface of the substrate. Therefore, it is effective to previously form a liquid repellent organic film such as FAS (fluoroalkylsilane) in a region where a contact hole is to be formed.

  Next, the third conductive material is discharged from the nozzle 123 to the contact hole 115 by a droplet discharge method, whereby the source electrode 116 and the drain electrode 117 are formed (FIG. 2D). As the third conductive material, the same material as that used as the first or second conductive material can be selected.

  Through the above steps, a so-called LDD structure top gate type TFT having a low concentration impurity region is completed.

  As described above, the semiconductor device according to the present invention is formed in contact with the semiconductor layer through the gate insulating film and the semiconductor layer including the channel region, the pair of impurity regions, and the pair of low-concentration impurity regions. A plurality of gate electrode layers having different widths, wherein the pair of low-concentration impurity regions are formed so as to overlap a thin portion of the plurality of gate electrode layers.

  Further, in the method for manufacturing a semiconductor device according to the present invention, a gate insulating film is formed over a semiconductor layer, a plurality of gate electrode layers having different widths are formed over the gate insulating film, and the plurality of gate electrode layers are formed. As a mask, a pair of impurity regions and a pair of low-concentration impurity regions are formed by introducing impurities into the semiconductor layer, and the pair of low-concentration impurity regions has a thickness of the plurality of gate electrode layers. It is characterized by being formed overlying a thin part.

  The present invention includes a gate electrode layer composed of at least two layers having different widths (here, the first and second gate electrode layers), and overlaps a wide layer among the gate electrode layers composed of at least two layers. A pair of low-concentration impurity regions is formed. As a result, at least two gate electrode layers can be easily formed by employing the droplet discharge method, and the convenience of the droplet discharge method can be utilized to the maximum. In addition, by introducing an impurity element using at least two gate electrode layers as a mask, a pair of impurity regions and a pair of low-concentration impurity regions can be easily formed.

  In the present embodiment, the top gate type TFT has been described as an example of the semiconductor device, but application of the present invention is not limited to this. For example, the present invention can be applied to a dual gate type TFT having a structure in which another gate electrode layer is provided under a semiconductor layer with a gate insulating film interposed therebetween.

(Embodiment 2)
In the present embodiment, an embodiment of a structure of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIG. Here, a top gate TFT will be described as an example. Up to the step of forming the gate insulating film 104 can be performed in the same manner as in Embodiment Mode 1 (FIG. 3A).

  After the gate insulating film 104 is formed, a composition containing a conductive material is discharged from the nozzle 121, whereby the gate electrode layer 301 is formed (FIG. 3A). The conductive material can be selected from those shown in the first embodiment. In addition, the gate electrode layer 301 is generally formed by performing heat treatment after discharging the above composition. For example, the gate electrode layer 301 is formed by drying at 100 ° C. for 3 minutes and further baking at 200 to 350 ° C. for 15 to 30 minutes in an atmosphere containing nitrogen and / or oxygen.

  Next, a resist 302 is selectively formed over the gate electrode layer 301 at a substantially central portion of the gate electrode layer 301 (FIG. 3B). The resist 302 is preferably formed by a droplet discharge method. The position where the resist 302 is formed may be set in accordance with the width of the low concentration impurity region. Then, using the resist 302 as a mask, the gate electrode layer 301 is etched to form a gate electrode layer 303 having a tapered side surface (hereinafter, simply referred to as “gate electrode layer 303” in this embodiment) (FIG. 3). (B)).

  Next, using the gate electrode layer 303 and the resist 302 as a mask, the impurity element 109 is introduced (doped) into the island-shaped semiconductor layer 103 by an ion implantation method or the like (FIG. 3C). As the impurity element 109, for example, phosphorus (P), arsenic (As), antimony (Sb), or p-type impurity element, for example, boron (B) can be used in the case of an n-type impurity element.

  With the introduction of the impurity element 109, a pair of impurity regions 110 is formed in a portion of the island-shaped semiconductor layer 103 that does not overlap with the gate electrode layer 303. On the other hand, a part of the island-shaped semiconductor layer 103 that overlaps the tapered side surface of the gate electrode layer 303 is introduced with the impurity element 109 through the side surface, whereby a pair of low-concentration impurity regions 111 is formed. Is done. The pair of impurity regions 110 constitute a source region or a drain region. A channel region 112 is formed between the pair of low-concentration impurity regions 111 (FIG. 3C).

  Note that doping can be performed after the resist 302 is removed; however, it is preferable to perform doping while leaving the resist 302 so that an impurity element is not introduced into the channel region 112.

  Next, after the resist 302 is removed or left, a cap insulating film 113 and an interlayer insulating film 114 for protecting the TFT are formed on the gate electrode layer 303 in the same manner as in the first embodiment (FIG. 3 (D)). Then, the interlayer insulating film 114, the cap insulating film 113, and the gate insulating film 104 are etched to form a contact hole, and then a conductive material is discharged from the nozzle 123 into the contact hole by a droplet discharge method. An electrode 116 and a drain electrode 117 are formed (FIG. 3D). A conductive material similar to that used as the gate electrode layer can be selected.

  Through the above steps, a so-called LDD structure top gate type TFT having a low concentration impurity region is completed.

  As described above, the semiconductor device according to the present invention is formed in contact with the semiconductor layer through the gate insulating film and the semiconductor layer including the channel region, the pair of impurity regions, and the pair of low-concentration impurity regions. And the pair of low-concentration impurity regions are formed so as to overlap a tapered portion of the gate electrode layer.

  The method for manufacturing a semiconductor device according to the present invention includes forming a gate insulating film on a semiconductor layer, forming a gate electrode layer on the gate insulating film, and masking the insulator formed on the gate electrode layer. Etching is performed to form a pair of impurity regions and a pair of low-concentration impurity regions by forming the gate electrode layer into a tapered shape and introducing impurities into the semiconductor layer using the tapered gate electrode layer as a mask. The pair of low-concentration impurity regions are formed to overlap a tapered region of the gate electrode layer.

  The present invention is characterized in that it includes a gate electrode layer having a tapered side surface, and a pair of low-concentration impurity regions are formed so as to overlap the tapered side surface of the gate electrode layer. Thereby, the tapered gate electrode layer can be easily formed by adopting the droplet discharge method in particular, and the convenience of the droplet discharge method can be fully utilized. In addition, a pair of impurity regions and a pair of low-concentration impurity regions can be easily formed by introducing an impurity element using the tapered gate electrode layer as a mask.

  In the present embodiment, the top gate type TFT has been described as an example of the semiconductor device, but application of the present invention is not limited to this. For example, the present invention can be applied to a dual gate TFT. In order to obtain a tapered shape, the gate electrode layer may be selectively formed by a droplet discharge method as described above, and then covered with an insulator such as a resist, and both ends may be etched into a tapered shape. Alternatively, it may be formed stepwise by discharging a composition containing a conductive material constituting the gate electrode layer a plurality of times from nozzles having different discharge amounts.

(Embodiment 3)
In the present embodiment, an embodiment of a structure of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIG. Here, a top gate TFT will be described as an example. The steps up to the step of forming the composition containing the conductive material forming the gate electrode layer by a droplet discharge method can be performed in the same manner as in Embodiments 1 and 2.

  When a composition including a conductive material is formed, a drying process is performed to solidify the composition, whereby the gate electrode layer 400 is obtained (FIG. 4A). For example, the drying process is performed at 100 ° C. for 3 minutes.

  Next, an insulator 401 having heat resistance (hereinafter, simply referred to as “insulator 401” in this embodiment) is selectively formed in a substantially central portion of the gate electrode layer 400 (FIG. 4B). . The insulator 401 is desirably formed selectively by a droplet discharge method. A portion where the insulator 401 is formed may be set in accordance with the width of the low concentration impurity region.

  As a material for the insulator 401 having heat resistance, a heat-resistant resin such as siloxane can be typically used. Note that the material of the insulator 401 is not limited to this as long as the material has heat resistance or heat absorption.

  Next, heat treatment is performed with the gate electrode layer 400 partially covered with the insulator 401. For example, baking is performed at 200 to 350 ° C. for 15 to 30 minutes in an atmosphere containing nitrogen and / or oxygen.

  Through the heat treatment, the thickness of the gate electrode layer 400 in a region where the insulator 401 is not formed is reduced. The mechanism is as described in the first embodiment. Note that in the case where oxygen is not contained in the heating atmosphere, or when a layer (organic layer) made of an organic component remains, the organic layer can be removed by oxygen plasma treatment or the like.

  On the other hand, a region of the gate electrode layer 400 covered with the insulator 401 is protected by the insulator 401 during the heat treatment, and thus the thickness of the region is not reduced.

  Thus, by subjecting the gate electrode layer 400 partially covered with the insulator 401 to heat treatment, gates having different thicknesses in a region covered with the insulator 401 and a region not covered in the gate electrode layer 400 are formed. An electrode layer 402 (hereinafter, simply referred to as “gate electrode layer 402” in this embodiment) is formed (FIG. 4C). Note that the gate electrode layer 402 is basically composed of a single layer, but this is not the case when the gate electrode layer 400 is a multilayer.

  Note that the width of the entire gate electrode layer 402 is also reduced by the heat treatment, and thus it is preferable to control the discharge conditions of the gate electrode layer 400 before the heat treatment in consideration thereof.

  In this way, the gate electrode layer 400 is covered with the insulator 401, fired in an atmosphere containing nitrogen and / or oxygen, or dried and then treated with oxygen plasma, whereby the organic layer on the surface portion is removed. Therefore, the thickness and width of a desired region of the gate electrode layer can be reduced, and the remaining gate electrode layer can be smoothed, thinned, and reduced in resistance. In particular, when the composition ratio of oxygen in the atmosphere is 10 to 25%, the thickness and width of the gate electrode layer can be efficiently reduced, and the gate electrode layer can be smoothed, thinned, and reduced in resistance. Can be planned.

  Next, the impurity element 109 is introduced (doped) into the island-like semiconductor layer 103 by an ion implantation method or the like using the gate electrode layer 402 and the insulator 401 as a mask (FIG. 4D). As the impurity element 109, for example, phosphorus (P), arsenic (As), antimony (Sb), or p-type impurity element, for example, boron (B) can be used in the case of an n-type impurity element.

  With the introduction of the impurity element 109, a pair of impurity regions 110 is formed in a portion of the island-shaped semiconductor layer 103 that does not overlap with the gate electrode layer 402. On the other hand, a part of the island-shaped semiconductor layer 103 that overlaps with a thin part of the gate electrode layer 402 is introduced with the impurity element 109 through the part, whereby a pair of low-concentration impurity regions 111 is formed. It is formed. The pair of impurity regions 110 constitute a source region or a drain region. A channel region 112 is formed between the pair of low-concentration impurity regions 111 (FIG. 4D).

  Note that doping can be performed after the insulator 401 is removed; however, it is preferable to perform doping while leaving the insulator 401 so that an impurity element is not introduced into the channel region 112.

  Next, after the insulator 401 is removed or left, the cap insulating film 113 and the interlayer insulating film 114 for protecting the TFT are formed on the gate electrode layer 402 in the same manner as in the first embodiment. (FIG. 4E). Then, the interlayer insulating film 114, the cap insulating film 113, and the gate insulating film 104 are etched to form a contact hole, and then a conductive material is discharged from the nozzle 123 into the contact hole by a droplet discharge method. An electrode 116 and a drain electrode 117 are formed (FIG. 4E). A conductive material similar to that used as the gate electrode layer can be selected.

  Through the above steps, a so-called LDD structure top gate type TFT having a low concentration impurity region is completed.

  As described above, the semiconductor device according to the present invention is formed in contact with the semiconductor layer through the gate insulating film and the semiconductor layer including the channel region, the pair of impurity regions, and the pair of low-concentration impurity regions. And the pair of low-concentration impurity regions are formed so as to overlap a thin portion of the gate electrode layer. .

  In addition, in the method for manufacturing a semiconductor device according to the present invention, a gate insulating film is formed over a semiconductor layer, a gate electrode layer is formed over the gate insulating film, and an insulating material having heat resistance is formed over the gate electrode layer. Forming and heating the gate electrode layer in an atmosphere containing oxygen and nitrogen to reduce the thickness of the gate electrode layer in a portion where the insulator is not formed, thereby forming gate electrode layers having different thicknesses. A pair of impurity regions and a pair of low concentration impurity regions are formed by introducing impurities into the semiconductor layer using the gate electrode layer as a mask, and the pair of low concentration impurity regions are formed in the gate electrode layer It is characterized in that it is formed so as to overlap with a thin portion.

  The present invention includes a gate electrode layer composed of a single layer having different thicknesses, and the pair of low-concentration impurity regions are formed so as to overlap a thin portion of the gate electrode layer. Yes. As a result, the gate electrode layer can be easily formed especially by employing the droplet discharge method, and the convenience of the droplet discharge method can be utilized to the maximum. In particular, a composition including a conductive material discharged using a droplet discharge method can form a single-layer or multi-layer gate electrode layer having different thicknesses by partial heat treatment. The present invention is characterized in that an impurity element is introduced by using a gate electrode layer having a different film thickness to pass through a thin portion of the film thickness, and a pair of low-concentration impurity regions is easily formed. be able to.

  In the present embodiment, the top gate type TFT has been described as an example of the semiconductor device, but application of the present invention is not limited to this. For example, the present invention can be applied to a dual gate TFT.

(Embodiment 4)
In the present embodiment, an embodiment of a structure of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIG. Here, a top gate TFT will be described as an example. The steps up to the step of forming the composition containing the conductive material forming the gate electrode layer by a droplet discharge method can be performed in the same manner as in Embodiments 1 and 2.

  After the composition containing the conductive material is formed, drying treatment is performed or the composition is left at room temperature to solidify the composition to form the gate electrode layer 400 (FIG. 5A). In the case of the drying treatment, for example, the drying is performed at 100 ° C. for 3 minutes. Note that the gate electrode layer 400 may be a single layer or a multilayer.

  Next, using the gate electrode layer 400 as a mask, the impurity element 109 is introduced (doped) into the island-shaped semiconductor layer 103 by an ion implantation method or the like (FIG. 5B). As the impurity element 109, for example, phosphorus (P), arsenic (As), antimony (Sb), or p-type impurity element, for example, boron (B) can be used in the case of an n-type impurity element.

  With the introduction of the impurity element 109, a pair of impurity regions 110 is formed in a portion of the island-shaped semiconductor layer 103 that does not overlap with the gate electrode layer 400 (FIG. 5B). The pair of impurity regions 110 constitute a source region or a drain region.

  Next, heat treatment is performed on the gate electrode layer 400. As the heat treatment, for example, baking is performed at 200 to 350 ° C. for 15 to 30 minutes in an atmosphere containing nitrogen and / or oxygen. By this heat treatment, a gate electrode layer 500 (hereinafter, simply referred to as “gate electrode layer 500”) in which the width and thickness of the gate electrode layer 400 are reduced is formed (FIG. 5C). . The mechanism by which the width and film thickness of the gate electrode layer 400 decrease is as described in Embodiment 1. The organic layer 501 generated during the heat treatment is baked in an atmosphere containing nitrogen and / or oxygen, or oxygen By removing it by plasma treatment or the like, the gate electrode layer 500 is obtained.

  As described above, the gate electrode layer 400 is baked in an atmosphere containing nitrogen and / or oxygen, or dried and then treated with oxygen plasma, whereby the organic layer on the surface portion is removed. The desired thickness and width of the desired region can be reduced, and the remaining gate electrode layer can be smoothed, thinned, and reduced in resistance. In particular, when the composition ratio of oxygen in the atmosphere is 10 to 25%, the thickness and width of the gate electrode layer can be efficiently reduced, and the gate electrode layer can be smoothed, thinned, and reduced in resistance. Can be planned.

  For example, when the Ag electrode is discharged and the gate electrode layer is baked in a nitrogen atmosphere at 230 ° C. for 1 hr, the gate electrode layer having a thickness of about 1100 nm is further added to the nitrogen atmosphere with a composition ratio of 25%. It was experimentally found that the film thickness was reduced to about 700 nm by mixing oxygen and baking the gate electrode layer at 230 ° C. for 1 hr. The reduction rate is about 63%. Also, the line width is not as low as the film thickness, but the line width was reduced by the second firing. The resistivity decreased to 60 to 70 μΩ · cm by the second firing. Therefore, by doping a high concentration impurity after the first baking, and by doping a lower concentration impurity by utilizing the fact that the line width and film thickness of the gate electrode layer are reduced by the second baking. A low concentration impurity region can be formed. This result can also be applied to the third embodiment.

  Next, using the gate electrode layer 500 as a mask, a low-concentration impurity element 502 is introduced (doped) into the island-shaped semiconductor layer 103 by an ion implantation method or the like (FIG. 5D). As the low-concentration impurity element 502, for example, phosphorus (P), arsenic (As), antimony (Sb) is used in the case of an n-type impurity element, and boron (B) is used in the case of a p-type impurity element. Can do.

  With the introduction of the low-concentration impurity element 502, a pair of low-concentration impurity regions 111 is formed in a portion of the island-shaped semiconductor layer 103 that does not overlap with the gate electrode layer 500 (FIG. 5D). A channel region 112 is formed between the pair of low-concentration impurity regions 111.

  Note that the width of the low-concentration impurity region 111 depends on the width of the gate electrode layer 400 that is reduced by the heat treatment, and thus the heat treatment conditions may be adjusted as appropriate in accordance with the desired width of the low-concentration impurity region 111. .

  Next, a cap insulating film 113 and an interlayer insulating film 114 for protecting the TFT are formed over the gate electrode layer 500 in the same manner as in Embodiment 1 (FIG. 5E). Then, the interlayer insulating film 114, the cap insulating film 113, and the gate insulating film 104 are etched to form a contact hole, and then a conductive material is discharged from the nozzle 123 into the contact hole by a droplet discharge method. An electrode 116 and a drain electrode 117 are formed (FIG. 5E). A conductive material similar to that used as the gate electrode layer can be selected.

  Through the above steps, a so-called LDD structure top gate type TFT having a low concentration impurity region is completed.

  As described above, in the method for manufacturing a semiconductor device according to the present invention, a gate insulating film is formed over a semiconductor layer, a gate electrode layer is formed over the gate insulating film, and the gate electrode layer is used as a mask. By introducing impurities into the semiconductor layer, a pair of impurity regions is formed, and the gate electrode layer is heated in an atmosphere containing oxygen and nitrogen to reduce the thickness and width of the gate electrode layer, A feature is that a pair of low-concentration impurity regions are formed by introducing low-concentration impurities into the semiconductor layer using the gate electrode layer whose thickness and width are reduced as a mask.

  The present invention utilizes the fact that the width and film thickness of the gate electrode layer can be reduced by performing heat treatment on the composition containing the conductive material constituting the gate electrode layer, before and after the heat treatment. By introducing impurity elements having different concentrations using the gate electrode layer as a mask, the source and drain regions and the pair of low-concentration impurity regions can be formed in the semiconductor layer with a simple process. Since the gate electrode layer can be easily formed especially by adopting a droplet discharge method, the present invention can make the most of the convenience of the droplet discharge method.

  In the present embodiment, the top gate type TFT has been described as an example of the semiconductor device, but application of the present invention is not limited to this. For example, the present invention can be applied to a dual gate TFT.

  In this embodiment, with reference to FIGS. 6A and 6B, in the structure of the semiconductor device and the manufacturing method thereof according to the present invention, when base pretreatment is performed, particularly when a hydrophilic film is provided in contact with the lower portion of the gate electrode layer. explain. Here, a top gate TFT will be described as an example. 6A to 6C, the process up to the step of forming the gate insulating film 104 can be performed in the same manner as in the above embodiment.

  FIG. 6A shows a case where a conductive oxide film (here, a TiOx film 130) is formed over the entire surface of the substrate or at least in a region where a gate electrode layer is formed. As the TiOx (titanium oxide) film, it is typically preferable to use titanium dioxide that is also used as a photocatalyst. Thereafter, for example, the gate electrode layers 105 and 106 are formed in the same manner as in the first embodiment.

In FIG. 6B, after a conductive film (here, Ti film 131) is formed over the entire surface, for example, gate electrode layers 105 and 106 are formed in the same manner as in Embodiment 1, and these gate electrode layers are used as a mask. In this example, the Ti film 131 is oxidized (baked or baked after O ₂ ion implantation) to form a TiOx film 130 around the gate electrode layer. The oxidation treatment is performed, for example, by baking a film at 230 ° C. after forming a Ti film having a thickness of 1 to 5 nm. By performing the oxidation treatment, a short circuit between the gate electrode layers can be prevented.

  In FIG. 6C, after the Ti film 131 is formed on the entire surface, for example, the gate electrode layers 105 and 106 are formed as in the first embodiment, and the exposed Ti film 131 is etched using the gate electrode layer 105 as a mask. Shows when to do. Thereby, a short circuit between the gate electrode layers can be prevented.

  In addition to Ti, Sc (scandium), V (vanadium), Cr (chromium), Mn (manganese), Fe (iron), Co (cobalt), Ni (nickel), Cu (copper), Zn (zinc) So-called 3d transition elements such as W (tungsten), Al (aluminum), Ta (tantalum), Zr (zirconium), Hf (hafnium), Ir (iridium), Nb (niobium), Pd (palladium), Pt (Platinum) and oxides, nitrides, and oxynitrides thereof can also be used. When these metals are formed directly on the entire surface of the substrate, as shown in FIGS. 6B and 6C, insulation is achieved by removing or oxidizing, nitriding, and oxynitriding other than the portion where the gate electrode layer is formed. There is a need to.

Titanium oxide is a material also known as a photocatalytic substance. In addition, strontium titanate (SrTiO ₃ ), cadmium selenide (CdSe), potassium tantalate (KTaO ₃ ), cadmium sulfide (CdS), Photocatalytic substances such as zirconium oxide (ZrO ₂ ), niobium oxide (Nb ₂ O ₅ ), zinc oxide (ZnO), iron oxide (Fe ₂ O ₃ ), and tungsten oxide (WO ₃ ) may be formed. In addition to materials containing these metals as main components, a heat-resistant resin such as polyimide, acrylic, or siloxane may be formed, or plasma treatment (preferably atmospheric pressure plasma) may be performed.

  There is no particular limitation on the method for manufacturing the conductor film and its oxide, nitride, and oxynitride. A conductor film and its oxide, nitride, or oxynitride may be formed directly or selectively on the entire surface of the substrate by a droplet discharge method, a spray method, or the like. Note that by forming a hydrophilic film such as the TiOx film 130 or the Ti film 131, adhesion between the gate insulating film 104 and a gate electrode layer to be formed later can be improved. Note that this embodiment can be freely combined with other embodiment modes or embodiments.

  In this embodiment, the case where SAS (semi-amorphous silicon) is used as the semiconductor layer 101 (or the island-shaped semiconductor layer 103) in the structure of the semiconductor device and the manufacturing method thereof according to the present invention will be described.

SAS can be obtained by glow discharge decomposition of a silicide gas. A typical silicide gas is SiH ₄ , and in addition, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4 and the} like can be used. The formation of the SAS can be facilitated by diluting the silicide gas with one or plural kinds of rare gas elements selected from hydrogen, hydrogen and helium, argon, krypton, and neon. It is preferable to dilute the silicide gas in a dilution ratio of 10 to 1000 times. Of course, the reaction of the coating by glow discharge decomposition is performed under reduced pressure, but the pressure may be in the range of about 0.1 to 133 Pa. The power for forming the glow discharge may be high frequency power of 1 to 120 MHz, preferably 13 to 60 MHz. The substrate heating temperature is preferably 300 ° C. or lower, and a substrate heating temperature of 100 to 200 ° C. is recommended.

Further, a carbide gas such as CH ₄ or C ₂ H ₆ or a germanium gas such as GeH ₄ or GeF ₄ is mixed in the silicide gas, so that the energy bandwidth is 1.5 to 2.4 eV, or 0. It may be adjusted to .9 to 1.1 eV.

SAS exhibits weak n-type conductivity when an impurity element for the purpose of valence electron control is not intentionally added. This is because oxygen is easily mixed into the semiconductor layer because glow discharge with higher power is performed than when an amorphous semiconductor is formed. Therefore, for the first semiconductor film provided with the channel formation region of the TFT, the threshold value is controlled by adding an impurity element imparting p-type at the same time as or after the film formation. Is possible. The impurity element imparting p-type is typically boron, and an impurity gas such as B ₂ H ₆ or BF ₃ may be mixed in the silicide gas at a rate of 1 to 1000 ppm. For example, when boron is used as the impurity element imparting p-type conductivity, the concentration of boron is preferably 1 × 10 ^{14 to} 6 × 10 ¹⁶ atoms / cm ³ . A field effect mobility of 1 to 10 cm ² / V · sec can be obtained by configuring the channel region with the SAS. Note that this embodiment can be freely combined with other embodiment modes or embodiments.

  In this example, a method for manufacturing an active matrix EL light-emitting device using the present invention will be described mainly with reference to FIGS.

  In the case where a light-emitting element (typically a light-emitting element using electroluminescence (EL)) including a layer containing an organic compound or an inorganic compound is driven by a thin film transistor (TFT), the EL light-emitting device is shown in FIG. As shown, in order to suppress variation in the ON current of the switching TFT provided in the pixel region, it is general to have at least a two-transistor structure including a driving TFT.

  Here, in the light-emitting element, a layer containing an organic compound or an inorganic compound having different carrier transport properties can be stacked between a pair of electrodes, holes can be injected from one electrode, and electrons can be injected from the other electrode. A phenomenon in which holes injected from one electrode and electrons injected from the other electrode recombine to excite the emission center and emit light when it returns to the ground state. It is an element using

  Note that FIG. 7B is a circuit diagram in the case where light emitting elements are stacked in order. Here, the stacked light emitting element refers to a case where the pixel electrode of the driving TFT 213 serves as a hole injection electrode (anode). Say. Note that FIG. 8B is a circuit diagram in the case where the light emitting elements are reversely stacked. Here, the reverse stacked light emitting element refers to a case where the pixel electrode of the driving TFT 213 serves as an electron injection electrode (cathode). .

  Further, reference numeral 212 in FIG. 7B denotes a switching TFT, which controls ON / OFF of a current flowing to the pixel. Here, as can be seen from FIG. 7A, the drain wiring 225 (or source wiring) of the switching TFT 212 is connected to the gate electrode layer 226 of the driving TFT 213. Since there is a gate insulating film between the drain wiring layer 225 and the drain wiring layer 225, both are electrically connected through the contact hole 115. The above symbols are the same in FIG. 7 and 8, reference numeral 227 denotes a capacitor portion. However, the region for forming the capacitor portion is not limited to this region. The symbols in FIGS. 7 and 8 correspond to those in FIGS.

  A light-emitting device and a manufacturing method thereof using the present invention will be described with reference to FIGS. FIG. 9 shows a cross-sectional structure taken along line XY in FIG. 7A or FIG. 8A. In FIGS. 9 and 10, the capacitor 227 is omitted. In this example, an active matrix EL light-emitting device using a TFT having a tapered gate electrode layer according to Embodiment 2 will be described; however, the structure of the gate electrode layer is not limited to this, It can replace with embodiment or an Example, or can carry out combining them.

  First, the base insulating film 118 is formed over the substrate 100. Here, a stacked structure of SiNO and SiON is used (FIG. 9A), but the material and structure are not limited to this. A material similar to the material used for the gate insulating film described above can be selected.

  Next, the island-shaped semiconductor layer 103 and the gate insulating film 104 are formed over the base insulating film 118 in the manner described in the above embodiment mode or example (FIG. 9A).

  Further, etching is performed using the resist 302 in the manner described in Embodiment 2 to form a tapered gate electrode layer 303 (FIG. 9A). Here, the gate electrode layer 226 of the driving TFT 213 of the pixel portion 215 extends in the direction of the switching TFT 212 in order to be connected to the switching TFT 212 (see FIG. 7A or FIG. 8A). Therefore, in FIG. 9A, the gate electrode layer indicated by 226 is generally composed of the same layer. Note that the gate electrode layer 226 needs to be tapered only in a region where at least the impurity element is introduced. The gate electrode layer may have a stacked structure.

Next, after the resist 200 is formed above the portion where the p-channel TFT 211 of the driver circuit portion 214 is formed (the resist 200 is preferably formed by a droplet discharge method), the gate electrode layer 303, The island-shaped semiconductor layer 103 is doped with an n-type impurity element 201 of the order of 10 ¹⁵ to 10 ¹⁷ atoms / cm ^{3 using} 225 as a mask. Thus, the n-type impurity serving as a source or drain region is formed in the n-channel TFT 210 of the driver circuit portion 214 and the island-like semiconductor layer not covered with the gate electrode layers of the switching TFT 212 and the driving TFT 213 of the pixel portion 215. Region 202 is formed. Further, an n-type low concentration impurity region 203 is formed in a region overlapping the tapered portion of the gate electrode layer. Further, a channel region 204 is formed between them (FIG. 9B). Note that in particular, for the driving TFT 213 in the pixel portion 215, an n-channel TFT or a p-channel TFT may be selected depending on a stacked structure of a light-emitting element 224 to be formed later.

Here, arsenic (As), phosphorus (P), or the like can be used as the n-type impurity element. Thereafter, the resist 200 is removed by O ₂ ashing or the like. At this time, if the resist 302 remains on the gate electrode layer, the resist 302 is also removed at the same time.

Next, the regions to be the n-channel TFT 210 in the driver circuit portion 214, the switching TFT 212 in the pixel portion 215, and the driving TFT 213 are covered with a resist 205 (the resist 205 is preferably formed by a droplet discharge method. ) Using the gate electrode layer 303 as a mask, a p-type impurity element 206 of the order of 10 ¹⁵ to 10 ¹⁷ atoms / cm ³ is doped into the island-shaped semiconductor layer of the p-channel TFT 211. As a result, a p-type impurity region 207 to be a source or drain region of the p-channel TFT 211 is formed. Further, a p-type low concentration impurity region 208 is formed in a region overlapping the tapered portion of the gate electrode layer. Further, a channel region 209 is formed between them (FIG. 9C). Here, boron (B) or the like can be used as the p-type impurity element. Thereafter, the resist 205 is removed by O ₂ ashing or the like. At this time, if the resist 302 remains on the gate electrode layer of the p-channel TFT 211, the resist 302 is also removed at the same time.

  Note that after the doping, the impurity element may be activated by heat treatment.

  Next, a cap insulating film 113 covering the TFT is formed by a plasma CVD method (FIG. 10A). As the cap insulating film 113, a silicon nitride film or a silicon oxynitride film is preferably used; however, the material is not limited to this. Further, the forming method is not limited to the plasma CVD method. Note that it is desirable to form the cap insulating film 113 as much as possible in order to prevent impurities from entering from above the TFT.

  Although not shown, it is desirable to form a passivation film for preventing diffusion of impurities from above the TFT on the source and drain wirings. The passivation film is formed by a thin film formation method such as plasma CVD or sputtering, and silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon (CN) and other insulating materials can be used. Note that these materials may be stacked. Note that the passivation film can also be formed by discharging a composition containing fine particles of an insulator material by a droplet discharge method.

Next, heat treatment for activating the impurity element added to the semiconductor layer is performed. This activation is performed by heating to 500 to 800 ° C. in a furnace having an N ₂ atmosphere. For example, an RTA (rapid thermal annealing) method can be used. Alternatively, activation may be performed by irradiating the semiconductor layer with laser light. In this case, the laser beam may be irradiated only from the substrate rear surface side or the substrate front surface side, or from both sides of the substrate front surface and the rear surface. In addition, when it is desired to simplify the process, the activation process may be omitted.

After that, an insulating film made of a silicon nitride film or a silicon nitride oxide film containing hydrogen is formed by a plasma CVD method, hydrogen is released from the insulating film, and heat treatment is performed to hydrogenate the semiconductor layer. Silicon dangling bonds may be terminated. This heat treatment may be performed at 350 to 450 ° C. (preferably 410 ° C.) in a N ₂ atmosphere using a clean oven. Note that another insulating film containing hydrogen and silicon may be used as the insulating film, and a method other than the plasma CVD method may be used as a forming method.

  Next, an interlayer insulating film 114 is formed on the cap insulating film 113. Here, a solution containing polyimide is applied to the entire surface of the substrate by a spin coating method, but the material and method are not limited thereto. For example, in addition to a polyimide resin, an acrylic resin, a polyamide resin, or an inorganic siloxane containing a Si—O—Si bond among compounds composed of silicon, oxygen, and hydrogen, hydrogen bonded to silicon is methyl or An organic siloxane insulating film substituted with an organic group such as phenyl can be used. Alternatively, the interlayer insulating film 114 can be formed by a droplet discharge method.

  Next, the interlayer insulating film 114, the cap insulating film 113, and the gate insulating film 104 are selectively removed to form contact holes. If an insulating film for hydrogenation is formed, it is also removed. For the contact hole opening, a conventional method can be used in which a resist is applied to the entire surface of the substrate, pre-baked, a mask pattern is formed through an exposure and development process, and the mask pattern is etched to form a contact hole. However, it is desirable from the viewpoint of cost reduction and process simplification to form a mask pattern by selectively discharging a resist by a droplet discharge method.

  After the contact hole is formed, the pixel electrode 216 is formed (FIG. 10B). The pixel electrode 216 may be formed by a droplet discharge method or may be formed through a patterning process. Note that the pixel electrode 216 may be formed before the contact hole is opened.

  Next, wirings 217 and 228 connected to the source and drain regions of each TFT are formed through the contact holes (FIG. 10B). Here, the wiring 217 is a wiring that connects the source or drain region of the switching TFT 212 and the gate electrode layer of the driving TFT 213. The wiring 228 is a wiring that connects the source or drain region of the driving TFT 213 and the pixel electrode 216. These wirings are preferably formed by discharging a composition containing a conductive material. Examples of conductive materials include Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, Ba and other metals, Al, C, Ni alloys, silver halide fine particles, or dispersible nanoparticles can be used.

  These wirings can also have a multilayer structure. For example, a Ti film having a thickness of 50 to 200 nm, an Al film or Al-Si alloy film having a thickness of 250 to 400 nm, and a Ti film having a thickness of 50 to 200 nm are stacked to form a wiring. In addition, of the three-layer structure, Ti is TiN or titanium nitride containing nitrogen at a composition ratio of 50% or less (in this specification, titanium nitride containing nitrogen at a composition ratio of 50% or less is represented as Ti (N). ) Or a structure in which TiN or Ti (N) is newly stacked. Moreover, since Al will generate hillocks at 150 to 200 ° C., it is desirable to contain Si. In this way, particularly when Al is used, there is a problem that Al is corroded if it is brought into direct contact with ITO, but this problem can be solved by using Ti (or TiN) between Al and ITO. . In particular, when an alloy of Al, C, and Ni is used, there is an advantage that direct contact with ITO is possible without using Ti or the like.

  Through the above steps, a driving circuit portion 214 including a CMOS structure including an n-channel TFT 210 and a p-channel TFT 211 and an active matrix substrate including a switching TFT 212, a driving TFT 213, and a pixel portion 215 including a capacitor portion are completed (FIG. 10 (C)). In this embodiment, the semiconductor device according to the present invention is used for both the driver circuit portion and the pixel portion, but it can also be used for at least one of them.

  Further, a partition wall (also referred to as a bank, a bank, or the like) 218 formed using an organic resin film or an inorganic insulating film is selectively formed over the pixel electrode 216 by a droplet discharge method. As the partition wall 218, it is preferable to use a heat-resistant resin such as siloxane, or a resin such as polyimide or acrylic. In particular, by using siloxane, the subsequent vacuum baking process can be performed at a high temperature, and moisture that adversely affects the EL element can be sufficiently removed. Note that the partition 218 is selectively formed to have an opening, and the pixel electrode 216 is exposed in the opening. Note that the partition 218 may be formed by patterning using a resist or the like.

  Next, a layer 219 containing an organic compound (electroluminescent layer) is formed so as to be in contact with the pixel electrode 216 in the opening of the partition 218. The layer 219 containing an organic compound may be formed of a single layer or a stack of a plurality of layers. When composed of a plurality of layers, as viewed from the semiconductor element side (pixel electrode side), (1) anode, hole (hole) injection layer, hole transport layer, light emitting layer, electron transport layer, cathode, (2) anode , Hole injection layer, light emitting layer, electron transport layer, cathode, (3) anode, hole injection layer, hole transport layer, light emitting layer, electron transport layer, electron injection layer, cathode, (4) anode, hole injection layer, hole Transport layer, light emitting layer, hole blocking layer, electron transport layer, cathode, (5) anode, hole injection layer, hole transport layer, light emitting layer, hole blocking layer, electron transport layer, electron injection layer, cathode, etc. What is necessary is just to set it as the element structure made. This is a so-called sequential structure, and the pixel electrode 216 functions as an anode (hole injection electrode). On the other hand, when the cathode comes first when viewed from the semiconductor element side (pixel electrode side), this is called reverse stacking, and the pixel electrode 216 functions as a cathode.

  Next, the counter electrode 220 is formed so as to cover the layer 219 containing an organic compound. The counter electrode 220 functions as an anode or a cathode by a method of laminating a light emitting layer. The light-emitting element 224 is formed by sandwiching the layer 219 containing an organic compound between the pixel electrode 216 and the counter electrode 220.

  Next, a passivation film 221 is formed in order to protect the layer 219 containing an organic compound (particularly the light emitting layer) from moisture. Instead of this, the protective film 221 is packaged (encapsulated) with a protective film (laminate film, ultraviolet curable resin film, etc.) or a cover material that has high air tightness and little outgassing so that the passivation film 221 is not exposed to the outside air. Is preferred. In this specification, the laminate film refers to a laminated film of a base film and an adhesive synthetic resin film, or two or more kinds of laminated films. As the base film, polyesters such as PET and PBT, polyamides such as nylon 6 and nylon 66, inorganic vapor deposition films, or papers may be used. As the adhesive synthetic film, polyolefin such as PE or PP, acrylic synthetic resin, epoxy synthetic resin, or the like may be used. The laminate film is laminated with the object to be processed by thermocompression bonding using a laminating apparatus. In addition, it is preferable to apply | coat an anchor coating agent as pre-processing which performs a lamination process, and can make the adhesion | attachment of a laminate film and a to-be-processed object strong. An isocyanate-based material or the like may be used as the anchor coating agent. Finally, the active matrix substrate was sealed with the sealing substrate 223 through the insulator 222.

  Through the above steps, an EL light-emitting device is completed (FIG. 10C). EL light-emitting devices are roughly classified into a bottom emission type, a top emission type, and a dual emission type according to the emission direction. Hereinafter, the structure of the light emitting element including the pixel electrode 216 and the counter electrode 220 will be described.

  In the case of the bottom emission type, the material of the pixel electrode 216 (in this case, the hole injection electrode) can be a transparent metal, for example, a transparent conductive film such as ITO, ITSO, ZnO, IZO, or GZO. In particular, when ITSO is used, the efficiency of hole injection into the light-emitting layer can be improved while the low resistance between the connection between the TFT and the pixel electrode 216 is maintained by stacking ITSO containing silicon oxides having different concentrations. Can be increased. On the other hand, the material of the counter electrode 220 that becomes the cathode (electron injection electrode) can be Ca, Al, CaF, MgAg, AlLi, or the like having a low work function.

  In the case of the top emission type, in general, the hole injection electrode (pixel electrode 216) and the electron injection electrode (counter electrode 220) in the bottom emission type are interchanged, and the layers containing organic compounds are reversely stacked to control current. By reversing the polarity of the TFT, a top emission type light emitting device capable of extracting light from the light emitting element on the opposite side (upper side) of the substrate can be obtained. For example, a reflective metal such as Al or AlLi is used for the pixel electrode 216, and a transparent conductive film such as ITO, ITSO, ZnO, IZO, or GZO that is light transmissive is used for the counter electrode 220. be able to.

  In the case of the dual emission type, as the material of the hole injection electrode (pixel electrode 216), a transparent conductive film such as ITO, ITSO, ZnO, IZO, GZO or the like can be used as in the case of the bottom emission type. As the electron injection electrode (counter electrode 220), a thin aluminum film having a thickness of 1 to 10 nm, an aluminum film containing a small amount of Li, or the like can be used so as to transmit light from the light emitting layer. As a result, a dual emission type light emitting device capable of extracting light from the light emitting element 224 up and down is obtained. Note that the roles of the pixel electrode 216 and the counter electrode 220 may be interchanged.

  Note that this embodiment can be freely combined with other embodiments and examples.

  An EL television receiver can be completed using the EL display panel 901 including the active matrix EL light-emitting device manufactured according to Embodiment 3. FIG. 11 is a block diagram showing a main configuration of the EL television receiver. In the EL display panel 901, (1) as in Example 3, the pixel portion of the display panel and the scanning line side driving circuit 903 are integrally formed on the substrate, and the signal line side driving circuit 902 is separately mounted as a driver IC. (2) When only the pixel portion of the display panel is formed and the scanning line side driver circuit 903 and the signal line side driver circuit 902 are mounted by the TAB method, (3) the pixel portion of the display panel and its periphery In addition, there are cases where the scanning line side driving circuit 903 and the signal line side driving circuit 902 are mounted by a COG method, but any form may be employed.

  As other external circuit configurations, on the input side of the video signal, among the signals received by the tuner 904, the video signal amplification circuit 905 that amplifies the video signal and the signal output from the signal are red, green, and blue colors And a control circuit 907 for converting the video signal into the input specification of the driver IC. The control circuit 907 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 908 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

  Of the signals received by the tuner 904, the audio signal is sent to the audio signal amplifier circuit 909, and the output is supplied to the speaker 913 via the audio signal processing circuit 910. The control circuit 911 receives control information on the receiving station (reception frequency) and volume from the input unit 912 and sends a signal to the tuner 904 and the audio signal processing circuit 910.

  A television receiver as shown in FIG. 20A can be completed by incorporating such an external circuit and the EL display panel 901 into a housing. Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do. Note that this embodiment can be freely combined with other embodiments and examples.

  In this embodiment, a method for manufacturing an active matrix liquid crystal display device using the present invention will be described with reference to FIGS.

  FIG. 12 is a top view of one pixel of the liquid crystal display device. A switching TFT 212 controls ON / OFF of a current flowing to the pixel. Here, a multi-gate structure is used. Reference numeral 228 denotes a source or drain wiring (also referred to as a 2nd wiring or the like), and 233 denotes a capacitor wiring. A capacitor portion 227 is formed between the capacitor wiring 233 and the pixel electrode 216. Note that the region where the capacitor portion is formed is not limited to this region.

  A liquid crystal display device using the present invention and a manufacturing method thereof will be described with reference to FIGS. 13 to 15 show the XY cross-sectional structure of FIG. In this example, the active matrix EL light-emitting device using the TFT having the double gate electrode layer having different widths described in Embodiment Mode 1 is described; however, the structure of the gate electrode layer is limited to this. Instead, the present invention can be carried out by replacing with other embodiments or examples or combining them.

  First, the base insulating film 118, the island-shaped semiconductor layer 103, the gate insulating film 104, and the gate electrode layers 230 to 232 are formed over the substrate 100 in the same manner as in Example 3 and Embodiment 1 (FIG. 13A). )). However, in this embodiment, only the switching TFT 212 in the pixel portion 215 has a so-called offset structure (also referred to as a Loff structure) in which the low-concentration impurity region does not overlap with the gate electrode layer 232, so that the stacked gates are stacked. The width of the electrode layer 232 was made substantially the same.

  Simultaneously with the gate electrode layers 230 to 232, the capacitor wiring 233 of the capacitor portion 227, the wiring 234 connected to the TFT, and the terminal electrode 235 of the terminal portion 239 connected to an external circuit such as an FPC are formed (FIG. 13). (A)), these may be formed separately.

Next, using the gate electrode layers 230 to 232 as a mask, for example, a low-concentration n-type impurity element 236 of the order of 10 ¹³ to 10 ¹⁴ atoms / cm ³ is doped into the island-shaped semiconductor layer 103 to form a low-concentration impurity region 237. Was formed (FIG. 13B). Note that the low-concentration impurity region 237 is ultimately a low-concentration impurity region of the switching TFT 212 and is not a low-concentration impurity region of the TFT of the drive circuit unit 214. Here, arsenic (As), phosphorus (P), or the like can be used as the n-type impurity element.

Next, portions remaining as low-concentration impurity regions of the p-channel TFT 211 and the switching TFT 212 in the driver circuit portion 214 are covered with a resist 200. Then, using the gate electrode layer 230 and the resist 200 as a mask (the resist 200 is preferably formed by a droplet discharge method), for example, an n-type impurity element 109 of the order of 10 ¹⁵ to 10 ¹⁷ atoms / cm ³ is used. The island-like semiconductor layer 103 was doped. Thus, an n-type impurity region 202 serving as a source or drain region is formed in the island-shaped semiconductor layer that is not covered with the resist 200 of the n-channel TFT 210 and the switching TFT 212 in the driver circuit portion 214. Further, an n-type low-concentration impurity region 203 is formed in a region overlapping with the thin portion of the gate electrode layer. Further, a channel region 204 is formed between them. (FIG. 13C).

On the other hand, in the switching TFT 212, only the high-concentration n-type impurity region 202 serving as a source or drain region is formed (FIG. 13C). Here, arsenic (As), phosphorus (P), or the like can be used as the n-type impurity element. Thereafter, the resist 200 is removed by O ₂ ashing or the like.

Next, the regions of the n-channel TFT 210 in the driver circuit portion 214 and the switching TFT 212 in the pixel portion 215 are covered with a resist 205 (the resist 205 is preferably formed by a droplet discharge method), and then the gate electrode layer. A p-type impurity element 206 of the order of 10 ¹⁵ to 10 ¹⁷ atoms / cm ³ is doped into the island-shaped semiconductor region of the p-channel TFT 211 using 231 as a mask. As a result, a p-type impurity region 207 to be a source or drain region of the p-channel TFT 211 is formed. Further, a p-type low-concentration impurity region 208 is formed in a region overlapping with the thin portion of the gate electrode layer. Further, a channel region 209 is formed between them (FIG. 14A). Here, boron (B) or the like can be used as the p-type impurity element. Thereafter, the resist 205 is removed by O ₂ ashing or the like.

  Note that after the doping, the impurity element may be activated by heat treatment.

  Thus, in the driver circuit portion 214, a TFT having a CMOS structure is obtained with a structure in which the low-concentration impurity region overlaps the gate electrode layer (also referred to as a Lov structure), and in the pixel portion 215, the low-concentration impurity region is An TFT having an offset structure (Loff structure) that does not overlap with the gate electrode layer can be obtained.

  Next, a cap insulating film 113 covering the TFT is formed by plasma CVD in the same manner as in Example 3 (FIG. 14B). The cap insulating film 113 is desirably formed as much as possible in order to prevent impurities from entering from above the TFT. Further, passivation film formation, impurity activation, and hydrogenation treatment may be performed as in the third embodiment.

  In this embodiment, a method for forming a contact hole using a liquid repellent material will be described. First, a liquid repellent material 240 is formed on a substrate by a droplet discharge method, a spin coating method, a slit coater method, a spray method, or the like, and a mask 241 made of PVA, polyimide, or the like is further formed at a location where a contact hole is to be formed. (FIG. 14B). As the liquid repellent material, a fluorine-based silane coupling agent such as FAS (fluoroalkylsilane) can be used. The mask 241 such as PVA or polyimide may be selectively discharged by a droplet discharge method.

Next, the liquid repellent material 240 is removed by etching using PVA or the like as a mask. The liquid repellent material 240 can be removed by O ₂ ashing or atmospheric pressure plasma. Thereafter, the mask is removed by a water washing treatment in the case of PVA, and N300 stripping solution or the like in the case of polyimide.

Next, an interlayer insulating film 114 (or a planarizing film) is formed by a droplet discharge method, a spin coating method, a slit coater method, or the like with a liquid repellent material remaining at a location where a contact hole is to be formed (see FIG. 14 (C)). At this time, since the liquid repellent material 240 exists in the place where the contact hole is formed, the interlayer insulating film is not formed thereon. Further, there is no possibility that the contact hole shape is reversely tapered. The interlayer insulating film is made of an organic resin such as acrylic, polyimide, or polyamide, or an inorganic siloxane containing a Si—O—Si bond among compounds composed of silicon, oxygen, and hydrogen, and hydrogen bonded to silicon is methyl or phenyl. It is preferable to use an organic siloxane-based insulating film substituted with an organic group or the like and to selectively form the film by a droplet discharge method. After the interlayer insulating film 114 is formed, the liquid repellent material 240 is removed by O ₂ ashing or atmospheric pressure plasma. If a passivation film is formed, it is also removed.

  After that, after the pixel electrode 216 is formed, a wiring 228 is formed, and the TFTs, the TFT and the pixel electrode 216, and the TFT and the wiring 234 are connected (FIG. 15A). Note that the pixel electrode 216 selects a transparent conductive material such as ITO or ITSO or a reflective conductive material such as MgAg depending on whether or not light is transmitted. The wiring 228 can be formed using the same material as in the third embodiment. The pixel electrode 216 and the wiring 228 are preferably formed by a droplet discharge method. Note that in the case where a cap film insulating film or the like is present above the terminal electrode 235, the interlayer insulating film 114 or the like is removed as a mask.

  Through the above steps, an active matrix TFT substrate is completed. Further, FIG. 15B shows a state in which a liquid crystal layer 251 is sandwiched between a TFT substrate and a counter substrate 250 and bonded with a sealant 252. A columnar spacer 253 is formed on the TFT substrate. The columnar spacer 253 is preferably formed in accordance with a depression of a contact portion formed on the pixel electrode. The columnar spacer 253 is formed with a height of 3 to 10 μm although it depends on the liquid crystal material to be used. Since the concave portion corresponding to the contact hole is formed in the contact portion, disorder of the alignment of the liquid crystal can be prevented by forming a spacer in accordance with this portion.

  An alignment film 254 is formed on the TFT substrate and a rubbing process is performed. A transparent conductive film 255 and an alignment film 254 are formed on the counter substrate 250. After that, the TFT substrate and the counter substrate 250 are bonded together with a sealant 252 and liquid crystal is injected to form a liquid crystal layer 251.

  Note that the liquid crystal layer 251 is obtained by bonding both substrates through a sealant 252 and then immersing one side of the bonded substrate having a liquid crystal injection port provided in the bonded substrate (cell) in the liquid crystal, thereby causing a capillary phenomenon. Can be formed by using a dip method (suction method) for injecting into the cell or a liquid crystal dropping method shown in FIG. FIG. 16 illustrates a so-called liquid crystal dropping method in which liquid crystal is dropped from a nozzle (dispenser) 326 and a counter substrate 330 is attached to one substrate 321 provided with a sealant 328 and a barrier layer 329. The liquid crystal dropping method is an effective means particularly when the substrate size is increased. Note that the barrier layer 329 in FIG. 16 is provided to prevent a chemical reaction between the liquid crystal molecules 327 and the sealing material 328. When both substrates are bonded together, the alignment marker 322 or 331 formed on both substrates in advance is detected by the image pickup means 323, and the stage 320 on which both substrates are arranged is controlled via the CPU 324 and the controller 325. Do.

  Next, an FPC (Flexible Print Circuit) 256 is attached to the terminal electrode 235 by a known method using an anisotropic conductive film 257.

  Through the above steps, an active matrix LCD device including the pixel portion 215, the driver circuit portion 214, the terminal portion 239, and the capacitor portion 227 is completed (FIG. 15B). In this embodiment, the semiconductor device according to the present invention is used for the drive circuit portion, but may be used for other regions (for example, a pixel portion). Note that this embodiment can be freely combined with other embodiments and examples.

  A liquid crystal television receiver can be completed by a liquid crystal display panel including an active matrix LCD device manufactured according to Embodiment 5. FIG. 17 is a block diagram showing a main configuration of the liquid crystal television receiver. In the liquid crystal display panel 421, (1) as in the third embodiment, the pixel portion of the display panel and the scanning line side driving circuit 423 are integrally formed on the substrate, and the signal line side driving circuit 422 is separately mounted as a driver IC. (2) When only the pixel portion of the display panel is formed and the scanning line side driver circuit 423 and the signal line side driver circuit 422 are mounted by the TAB method, (3) the pixel portion of the display panel and its periphery In addition, there are cases where the scanning line side driver circuit 423 and the signal line side driver circuit 422 are mounted by a COG method, but any form may be employed.

  As other external circuit configurations, on the video signal input side, among the signals received by the tuner 424, the video signal amplification circuit 425 that amplifies the video signal, and the signal output from the signal is red, green, and blue. And a control circuit 427 for converting the video signal into the input specification of the driver IC. The control circuit 427 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 428 may be provided on the signal line side, and an input digital signal may be divided into m pieces and supplied.

  Of the signals received by the tuner 424, the audio signal is sent to the audio signal amplifier circuit 429, and the output is supplied to the speaker 433 through the audio signal processing circuit 430. The control circuit 431 receives the receiving station (reception frequency) and volume control information from the input unit 432 and sends a signal to the tuner 424 and the audio signal processing circuit 430.

  A television receiver as shown in FIG. 20A can be completed by incorporating such an external circuit and a liquid crystal display panel 421 into a housing. Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do. Note that this embodiment can be freely combined with other embodiments and examples.

  In this embodiment, a method for manufacturing various compositions constituting a gate electrode layer and the like using a droplet discharge system in the structure of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIGS. To do. FIG. 18 is a schematic diagram of a droplet discharge system.

  First, circuit design is performed by a circuit design tool 140 such as CAD, CAM, CAE, etc., and an arrangement location of a desired thin film and alignment marker is determined.

  Next, the data 141 of the thin film pattern including the designed thin film and the alignment marker location is input to the computer 142 that controls the droplet discharge device via an information network such as a recording medium or a LAN (Local Area Network). Is done. Based on the thin film pattern data 141, the composition containing the material constituting the thin film among the nozzles (a cylindrical device for ejecting liquid or gas from the narrow hole) of the droplet discharge means 143. Or a nozzle having an optimal discharge port diameter connected to a tank for storing the composition is determined, and then a scanning path (movement path) of the droplet discharge means 143 is determined. If an optimal nozzle is determined in advance, only the movement path of the nozzle need be set.

  Next, the alignment marker 153 is formed on the substrate 144 on which the thin film is formed using a photolithography technique or laser light. Then, the substrate on which the alignment marker is formed is placed on the stage 156 in the droplet discharge device, the position of the alignment marker is detected by the imaging means 145 provided in the device, and the computer 142 is connected via the image processing device 146. Is input as position information 147. In the computer 142, the thin film pattern data 141 designed by CAD or the like is compared with the alignment marker position information 147 obtained by the imaging unit 145, and the substrate 144 and the droplet discharge unit 143 are aligned.

  Thereafter, the droplet discharge means 143 controlled by the controller 148 discharges the composition 154 in accordance with the determined scanning path, whereby a desired thin film pattern 149 is formed. The discharge amount of the composition can be adjusted as appropriate by selecting the diameter of the discharge port, but the moving speed of the discharge port, the interval between the discharge port and the substrate, the discharge speed of the composition, the discharge space Since it varies slightly depending on all conditions such as atmosphere, temperature and humidity of the space, it is desirable to be able to control these conditions. As for these, optimal conditions are obtained in advance by experiments and evaluations, and the results are preferably stored in the database 155 for each material of the composition.

  Here, as the thin film pattern data, for example, a circuit diagram of an active matrix TFT substrate used in a liquid crystal display device, an EL display device or the like can be cited. A circuit diagram in a circle in FIG. 18 schematically shows a conductive film used for such an active matrix TFT substrate. Reference numeral 157 denotes a so-called gate wiring, 158 denotes a source signal line (2nd wiring), and 159 denotes a pixel electrode, a hole injection electrode, or an electron injection electrode. Reference numeral 156 denotes a substrate, and 160 denotes an alignment marker. Naturally, the thin film pattern 149 corresponds to the gate wiring 157 in the thin film pattern information.

  In addition, the droplet discharge unit 143 has a configuration in which the plurality of nozzles 150a to 150c are integrated here, but is not limited thereto. Each nozzle has a single or a plurality of discharge ports 151. The thin film pattern 149 is formed by selecting a predetermined discharge port 151 among the nozzles 150a to 150c.

  The droplet discharge means 143 is provided with a plurality of nozzles having different discharge port diameters, discharge amounts, or nozzle pitches in order to cope with the production of thin film patterns having any line width and to improve the tact time. Is desirable. Further, it is desirable that the interval between the discharge ports be as narrow as possible. Further, in order to perform high-throughput ejection on a large-area substrate having a side of 1 m or more, it is desirable that the droplet ejection unit 143 includes a nozzle having a length of 1 m or more. Further, the droplet discharge means 143 may have an expansion / contraction function so that the interval between the discharge ports can be freely controlled. In order to draw a high resolution, that is, a smooth pattern, it is desirable that the nozzle or the head be inclined obliquely. As a result, a large area such as a rectangular shape can be drawn.

  Further, a head having a different nozzle pitch may be provided in parallel with one head. In this case, the discharge port diameter may be the same or different.

  Further, as described above, in the case of a droplet discharge device using a plurality of nozzles, it is necessary to provide a standby place for storing unused nozzles. By providing a gas supply means and a shower head in this standby place, the atmosphere in the standby place can be replaced with an atmosphere of the same gas as the solvent of the composition, so that drying can be prevented to some extent. . Furthermore, you may equip with the clean unit etc. which supply clean air and reduce the dust of a working area.

  However, when the interval between the discharge ports cannot be reduced due to the specifications of the nozzles 150a to 150c, the nozzle pitch may be designed to be an integer multiple of the pixels in the display device. Accordingly, the composition can be discharged onto the substrate 144 by shifting the nozzles 150a to 150c. As the imaging means 145, a camera using an active element that converts light intensity into an electrical signal, such as a CCD (charge coupled device), may be used.

  In the method described above, the thin film pattern 149 is formed by fixing the stage 152 on which the substrate 144 is placed and scanning the substrate 144 according to the determined path. On the other hand, the thin film pattern 149 may be formed by fixing the droplet discharge means 143 and transporting the stage 152 in the XYθ direction according to the path determined based on the thin film pattern data 141. At this time, in the case where the droplet discharge means 143 has a plurality of nozzles, the composition containing the material constituting the thin film is stored, or the optimal connection to the tank storing the composition is made. It is necessary to determine a nozzle having a discharge port diameter.

  In the above-described method, the thin film pattern 149 is discharged and formed using only one predetermined discharge port of the nozzle 150c. However, a plurality of discharge holes are formed according to the line width and film thickness of the thin film pattern 149 to be formed. The composition may be discharged using the outlet.

  A plurality of nozzles may be used to provide a redundant function. For example, the composition is first ejected from the nozzle 150a (or 150b), but the ejection conditions are controlled so that the same composition is ejected from the nozzle 150c, so that the ejection nozzle is clogged at the front nozzle 150a. Even if the hindrance is caused, since the composition can be discharged from the rear nozzle 150c, at least the disconnection of the wiring can be prevented.

  Further, by controlling the discharge conditions so that the composition is discharged from a plurality of nozzles having different discharge port diameters, a flat thin film can be formed with a shortened tact time. This method is particularly suitable for forming a thin film having a large discharge area of the composition and requiring flatness, such as a pixel electrode in an LCD.

  Furthermore, by controlling the ejection conditions so that the composition is ejected from a plurality of nozzles having different ejection port diameters, patterns having different line widths of wiring can be formed at a time.

  Furthermore, by controlling the discharge conditions so that the composition is discharged from a plurality of nozzles having different discharge port diameters, the composition can be filled into the opening portion having a high aspect ratio provided in a part of the insulating film. it can. According to this method, a flattened wiring can be formed without generating a void (a worm-like hole generated between the insulating film and the wiring).

  In a droplet discharge system used for forming a thin film or wiring, as described above, for inputting a data indicating a thin film pattern and discharging a composition containing a material constituting the thin film based on the data By setting the moving means of the nozzle, a setting means for setting the moving path of the nozzle, an imaging means for detecting the alignment marker formed on the substrate, and a control means for controlling the moving path of the nozzle, a droplet is formed. It is necessary to accurately control the movement path of the nozzle or the substrate during discharge. By reading a composition discharge condition control program into a computer that controls the droplet discharge system, the nozzle or substrate moving speed, the discharge amount of the composition, the injection distance, the injection speed, Various conditions such as the atmosphere / temperature / humidity of the discharge environment and the substrate heating temperature can be controlled accurately.

  As a result, a thin film or wiring having a desired thickness, thickness, and shape can be accurately produced at a desired location under a short tact time and a high throughput. The production yield of an active element such as a TFT manufactured in this way, a liquid crystal display (LCD) manufactured using the active element, a light emitting device such as an organic EL display, LSI, or the like can be improved. In particular, by using the present invention, a thin film or wiring pattern can be formed at an arbitrary location, and the thickness, thickness, and shape of the pattern to be formed can be adjusted. It can be manufactured with good yield.

  As an example of an electronic device using the EL light-emitting device or the liquid crystal display device of the above embodiment, a television receiver, a portable book (electronic book), and a mobile phone illustrated in FIG. 20 can be completed.

  In the television receiver in FIG. 20A, a display module 2002 using liquid crystal or an EL element is incorporated in a housing 2001, and general television broadcasting is received by a receiver 2005, and wired via a modem 2004. Alternatively, by connecting a television receiver to a wireless communication network, information communication in one direction (from a transmitter to a receiver) or in both directions (between a transmitter and a receiver, or between receivers) can be performed. The television receiver can be operated by a switch incorporated in the housing or a separate remote control device 2006. Even if this remote control device is provided with a display portion 2007 for displaying information to be output. good.

  In addition, the television receiver may have a configuration in which a sub screen 2008 is formed using the second display module in addition to the main screen 2003 to display a channel, a volume, and the like. In this configuration, the main screen 2003 may be formed using an EL display module with an excellent viewing angle, and the sub screen 2008 may be formed using a liquid crystal display module capable of displaying with low power consumption. In order to prioritize low power consumption, the main screen 2003 may be formed using a liquid crystal display module, the sub screen 2008 may be formed using an EL display module, and the sub screen 2008 may be blinkable.

  Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do. In addition to receiving video, the present invention can also be applied to a device capable of bidirectional communication such as a digital television.

  FIG. 20B illustrates a portable book (electronic book), which includes a main body 3101, display portions 3102 and 3103, a storage medium 3104, operation switches 3105, an antenna 3106, and the like.

  FIG. 20C illustrates a mobile phone, where 3001 is a display panel, and 3002 is an operation panel. The display panel 3001 and the operation panel 3002 are connected at a connection portion 3003. An angle θ between the surface of the connection unit 3003 on which the display unit 3004 of the display panel 3001 is provided and the surface of the operation panel 3002 on which the operation keys 3006 are provided can be arbitrarily changed. Further, an audio output unit 3005, operation keys 3006, a power switch 3007, an audio input unit 3008, an antenna 3009, and the like are provided.

  Further, the present invention is characterized in that it includes a gate electrode layer having a single layer structure or a stacked structure having a film thickness difference. Such a gate electrode layer can be simplified by adopting a droplet discharge method in particular. The convenience of the droplet discharge method can be maximized. In addition, the present invention includes a gate electrode layer having a single layer structure or a stacked structure having a difference in film thickness, whereby a Lov structure TFT can be easily manufactured.

  The semiconductor device, the light emitting device using the semiconductor device, and the liquid crystal display device according to the present invention have configurations that can reduce the number of steps and material costs, and actively use the droplet discharge method. Is possible. Therefore, the above devices can be manufactured with a small number of steps, low cost, high throughput, high yield, and short tact time, and it is a significant invention among those requiring low cost and high quality. Industrial applicability is extremely high.

8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. 8A and 8B illustrate a semiconductor device and a manufacturing method thereof according to the present invention. Diagram explaining ground pretreatment Pixel top view of a light emitting device according to the present invention Pixel top view of a light emitting device according to the present invention Manufacturing process of light-emitting device according to the present invention Manufacturing process of light-emitting device according to the present invention The block diagram which shows the main structures of the television receiver using the light-emitting device which concerns on this invention. Pixel top view of a liquid crystal display device according to the present invention Manufacturing process diagram of liquid crystal display device according to the present invention Manufacturing process diagram of liquid crystal display device according to the present invention Manufacturing process diagram of liquid crystal display device according to the present invention Illustration of liquid crystal dropping method The block diagram which shows the main structures of the television receiver using the liquid crystal display device which concerns on this invention Illustration of droplet discharge system Illustration of the structure of conductive particles FIG. 6 illustrates an example of an electronic device manufactured using the present invention.

Explanation of symbols

100 Substrate 101 Semiconductor layer 102 Resist 103 Island-like semiconductor layer 104 Gate insulating film 105 Gate electrode layer 106 Gate electrode layer 109 Impurity element 110 Impurity region 111 Low-concentration impurity region 112 Channel region 113 Cap insulating film 114 Interlayer insulating film 115 Contact hole 116 Source electrode 117 Drain electrode 118 Base insulating film 120 Nozzle 121 Nozzle 122 Nozzle 123 Nozzle 130 TiOx film 131 Ti film 140 Circuit design tool 141 Data 142 Computer 143 Droplet ejection means 144 Substrate 145 Imaging means 146 Image processing device 147 Position information 148 Controller 149 Thin film pattern 150 Nozzle 151 Discharge port 152 Stage 153 Alignment marker 154 Composition 155 Database 156 Stage 157 Gate wiring 301 Gate electrode layer 302 Resist 303 Gate electrode layer 310 Cu
311 Ag
312 Buffer layer 400 Gate electrode layer 401 Insulator 402 Gate electrode layer 500 Gate electrode layer 501 Organic layer 502 Impurity element 200 Resist 202 N-type impurity region 203 Low-concentration impurity region 204 Channel region 205 Resist 207 p-type impurity region 208 Low-concentration impurity Region 209 Channel region 210 n-channel TFT
211 p-channel TFT
212 Switching TFT
213 Driving TFT
214 driving circuit portion 215 pixel portion 216 pixel electrode 217 wiring 218 partition 219 layer containing organic compound 220 counter electrode 221 passivation film 222 insulator 223 sealing substrate 224 light emitting element 225 drain wiring 226 gate electrode layer 227 capacitor portion 228 wiring 230 gate Electrode layer 231 Gate electrode layer 232 Gate electrode layer 233 Capacitor wiring 234 Wiring 235 Terminal electrode 236 N-type impurity element 237 Low concentration impurity region 239 Terminal portion 240 Liquid repellent material 241 Mask 250 Counter substrate 251 Liquid crystal layer 252 Sealing material 253 Spacer 254 Alignment film 255 Transparent conductive film 256 FPC
257 Anisotropic conductive film 901 EL display panel 902 Signal line side drive circuit 903 Scan line side drive circuit 904 Tuner 905 Video signal amplification circuit 907 Control circuit 908 Signal division circuit 909 Audio signal amplification circuit 910 Audio signal processing circuit 911 Control circuit 912 Input unit 913 Speaker 320 Stage 321 Substrate 322 Alignment marker 323 Imaging means 324 CPU
325 Controller 326 Nozzle 327 Liquid crystal molecule 328 Sealing material 329 Barrier layer 330 Counter substrate 421 Liquid crystal display panel 422 Signal line side drive circuit 423 Scan line side drive circuit 424 Tuner 425 Video signal amplification circuit 426 Video signal processing circuit 427 Control circuit 428 Signal division Circuit 429 Audio signal amplification circuit 430 Audio signal processing circuit 431 Control circuit 432 Input unit 433 Speaker 2001 Case 2002 Display module 2003 Main screen 2004 Modem 2005 Receiver 2006 Remote control device 2007 Display unit 2008 Sub-screen 3101 Main body 3102 Display unit 3104 Storage Medium 3105 Operation switch 3106 Antenna 3001 Display panel 3002 Operation panel 3003 Connection unit 3004 Display unit 3005 Audio output unit 3006 Operation keys 007 power switch 3008 speech input unit

Claims (16)

A semiconductor layer including a channel region, a pair of impurity regions, and a pair of low-concentration impurity regions;
A plurality of gate electrode layers having different widths formed in contact with the semiconductor layer via a gate insulating film,
The pair of low-concentration impurity regions is formed so as to overlap a thin portion of the plurality of gate electrode layers. A semiconductor layer including a channel region, a pair of impurity regions, and a pair of low-concentration impurity regions;
A tapered gate electrode layer formed in contact with the semiconductor layer via a gate insulating film,
The pair of low-concentration impurity regions is formed to overlap with a tapered portion of the gate electrode layer. A semiconductor layer including a channel region, a pair of impurity regions, and a pair of low-concentration impurity regions;
A gate electrode layer made of a single layer having a different film thickness formed in contact with the semiconductor layer through a gate insulating film,
The pair of low-concentration impurity regions are formed so as to overlap a thin portion of the gate electrode layer. In any one of Claims 1 thru | or 3,
The semiconductor device, wherein the gate electrode layer is formed in contact with a hydrophilic film. In any one of Claims 1 thru | or 4,
The semiconductor device, wherein the gate electrode layer includes at least one selected from Ag, Cu, Au, Al, Al-Si, Ni, NiB, W, W-Si, TaN, Ti, and TiN.   An EL display device comprising the semiconductor device according to claim 1 in one or both of a pixel portion and a driver circuit portion.   A liquid crystal display device comprising the semiconductor device according to claim 1 in one or both of a pixel portion and a driver circuit portion. Forming a gate insulating film on the semiconductor layer;
Forming a plurality of gate electrode layers having different widths on the gate insulating film;
A pair of impurity regions and a pair of low-concentration impurity regions are formed by introducing impurities into the semiconductor layer using the plurality of gate electrode layers as a mask,
The pair of low-concentration impurity regions is formed so as to overlap a thin portion of the plurality of gate electrode layers. Forming a gate insulating film on the semiconductor layer;
Forming a gate electrode layer on the gate insulating film;
Etching is performed using an insulator formed on the gate electrode layer as a mask, and the gate electrode layer is tapered.
Using the tapered gate electrode layer as a mask, by introducing impurities into the semiconductor layer, a pair of impurity regions and a pair of low-concentration impurity regions are formed,
The pair of low-concentration impurity regions is formed so as to overlap with a tapered region in the gate electrode layer. Forming a gate insulating film on the semiconductor layer;
Forming a gate electrode layer on the gate insulating film;
Forming an insulating material having heat resistance on the gate electrode layer;
By heating the gate electrode layer in an atmosphere containing oxygen and nitrogen, the thickness of the portion of the gate electrode layer where the insulator is not formed is reduced, and a gate electrode layer having a different thickness is obtained.
A pair of impurity regions and a pair of low-concentration impurity regions are formed by introducing impurities into the semiconductor layer using the gate electrode layer as a mask,
The pair of low-concentration impurity regions is formed so as to overlap a thin portion of the gate electrode layer. Forming a gate insulating film on the semiconductor layer;
Forming a gate electrode layer on the gate insulating film;
A pair of impurity regions are formed by introducing impurities into the semiconductor layer using the gate electrode layer as a mask,
By heating the gate electrode layer in an atmosphere containing oxygen and nitrogen, the thickness and width of the gate electrode layer is reduced,
A method for manufacturing a semiconductor device, wherein a pair of low-concentration impurity regions is formed by introducing low-concentration impurities into the semiconductor layer using the gate electrode layer with reduced thickness and width as a mask. In any one of Claims 10 or 11,
A method for manufacturing a semiconductor device , wherein a composition ratio of oxygen in the atmosphere is 10 to 25%. In any one of claims 8 to 12,
The method for manufacturing a semiconductor device is characterized in that the gate electrode layer is formed in contact with a hydrophilic film. In any one of Claims 8 thru | or 13,
The gate electrode layer includes at least one selected from Ag, Cu, Au, Al, Al—Si, Ni, NiB, W, W—Si, TaN, Ti, and TiN. Method.   An EL display device comprising the semiconductor device manufactured according to claim 8 in one or both of a pixel portion and a driver circuit portion.   A liquid crystal display device comprising the semiconductor device manufactured according to claim 8 in one or both of a pixel portion and a driver circuit portion.

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