JP2005333058A - Solid-state image pickup element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fine solid-state image pickup element driven at high speed by making resistance of a charge transmission electrode to be low and thin and flattening a film. <P>SOLUTION: The solid-state image pickup element is provided with a photoelectric converter and a charge transmitter having the charge transmission electrode transmitting a charge caused in the photoelectric converter. In the charge transmission electrode, a first electrode formed of a first layer conductive film and a second electrode formed of a second layer conductive film are alternately arranged. The first layer and the second layer conductive films contain metals or metal silicide. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device and a method for manufacturing the same, and more particularly to a charge transfer electrode of a solid-state imaging device.

  A solid-state imaging device using a CCD used for an area sensor or the like includes a photoelectric conversion unit including a photodiode and a charge transfer unit including a charge transfer electrode for transferring a signal charge from the photoelectric conversion unit. . A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer path formed on the semiconductor substrate, and are sequentially driven.

In recent years, with the increase in the number of pixels of a CCD, the demand for higher resolution and higher sensitivity is increasing in solid-state imaging devices, and the number of imaging pixels is increasing to more than gigapixels.
In order to realize further high-speed driving in such a situation, there is a high demand for lowering the resistance of the charge transfer electrode, and vertical shrinkage is essential for miniaturization.
Conventionally, a device provided with a shunt wiring has been proposed for high-speed driving of a CCD (see Patent Documents 1 to 4).

However, as the miniaturization progresses, vertical shrinkage becomes important in pattern miniaturization, and there is a problem that improvement in sensitivity cannot be expected with shunt wiring.
Further, in the multi-electrode structure in which the second layer electrode is superimposed on the first layer electrode, the second layer or subsequent electrode separation is performed on the first layer electrode. It becomes.

Therefore, a single-layer electrode structure in which electrodes are juxtaposed with an interelectrode insulating film interposed therebetween has been proposed (Patent Documents 5 and 6).
For example, in Patent Document 5, as shown in FIG. 10A, a buried channel layer or the like is formed on a silicon substrate 101, and a first layer conductive layer made of a polycrystalline silicon layer is formed on the surface via a gate insulating film 102. The conductive film 103a is formed and patterned to form a first electrode, and a silicon oxide film 104 is formed around the first electrode.

Thereafter, as shown in FIG. 10B, a second-layer conductive film 103b made of a polycrystalline silicon layer is further formed thereon.
Then, as shown in FIG. 10C, the surface is flattened by CMP to form a charge transfer portion having a single-layer electrode structure.

In this method, flattening is possible, but the charge transfer electrode is composed of a polycrystalline silicon layer, and there is a limit to reducing the resistance.
On the other hand, a charge transfer electrode having a so-called polycide structure in which a metal silicide layer is formed on a polycrystalline silicon layer has been proposed in order to reduce the resistance of the electrode.

  In this case, since it is difficult to apply the CMP method, a method of forming a gap in a conductive layer formed by one film formation and patterning is used instead of a method of stacking and planarizing. . In this method, it is necessary to narrow the gap beyond the pattern limit as the miniaturization progresses. Therefore, for example, as shown in FIGS. 11A to 11C, patterning is performed by photolithography to form a gap between electrodes, and then a sidewall is formed by leaving the sidewall of polycrystalline silicon, thereby narrowing the gap between electrodes. A method to do this has been proposed (Patent Document 7).

  In this method, for example, as shown in FIG. 11A, a first layer conductive film 103a made of a polycrystalline silicon layer and a metal silicide 103m are formed on a silicon substrate 101 via a gate insulating film 102. Is patterned to form a first electrode.

  Thereafter, as shown in FIG. 11B, a second-layer conductive film 103b made of a polycrystalline silicon layer is further formed thereon, and a sidewall is formed on the side wall of the first electrode by anisotropic etching. Let it remain.

  Then, as shown in FIG. 11C, a silicon oxide film 104 is filled in the interelectrode region narrowed by the sidewall by the CVD method.

  In this method, the distance between the electrodes is defined by the sidewalls, and there is a problem that variations tend to occur and stable formation is difficult.

  In addition, after forming the electrodes, it is necessary to embed an insulating film such as a silicon oxide film in a narrow gap between the electrodes, and void V is likely to be generated, which may cause a leak, and charge transfer capable of fine and high-speed operation. It was difficult to stably obtain the element.

Japanese Patent Laid-Open No. 11-274445 Japanese Patent Laid-Open No. 11-186540 JP 11-168204 A JP 2001-135811 A JP 11-26743 A JP-A-8-274307 Japanese Patent Laid-Open No. 5-129583

As described above, in the conventional solid-state imaging device, the shrinkage in the vertical direction is slowed down, and at the time of miniaturization, it is extremely difficult to increase the speed by reducing the resistance of the electrode material.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a solid-state imaging device that can be driven at high speed and can be miniaturized.

  Accordingly, the present invention provides a solid-state imaging device including a photoelectric conversion unit and a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit, wherein the charge transfer electrode is a first layer. The first electrode made of a conductive film and the second electrode made of a second layer conductive film are alternately juxtaposed, and both the first layer and the second layer conductive film contain metal or metal silicide. It is characterized by.

  According to the above configuration, the first electrode and the second electrode are alternately juxtaposed, and both are configured to include metal or metal silicide, so that planarization is possible and low resistance is achieved. Also, no shunt wiring is required, and both vertical shrinking and high speed are possible. Accordingly, miniaturization is possible, and it is possible to form a solid-state imaging device with high sensitivity and high reliability.

In the invention, the second layer conductive film includes a metal silicide.
According to this configuration, since the second layer conductive film can be formed by silicidation, patterning is easy.

  The present invention includes the first layer conductive film and the second layer conductive film made of polymetal.

  The present invention includes the first layer conductive film and the second layer conductive film made of metal silicide.

In the invention, it is preferable that the first electrode is surrounded by a sidewall insulating film.
Since reliable and fine intervals can be formed in a self-aligning manner, it is highly reliable.

In the solid-state imaging device of the present invention, an interelectrode distance between the first and second electrodes is 0.1 μm or less.
When the distance between the electrodes is 0.1 μm or less, it is difficult to add the insulating film. However, according to this method, the CVD oxide film can be easily formed by leaving the side wall by anisotropic etching or surface oxidation. Therefore, a fine pattern can be easily formed.

The present invention is also a method for manufacturing a solid-state imaging device including a photoelectric conversion unit and a charge transfer unit including a charge transfer electrode that transfers a charge generated in the photoelectric conversion unit, the charge transfer unit The electrode manufacturing process includes a step of forming a first electrode made of a first layer conductive film containing metal or metal silicide, a step of forming an insulating film on a side wall of the first electrode, A second layer conductive film is formed on the upper layer, and the second layer on the first electrode is separated to separate the second layer conductive film so that the second electrode is positioned between the first electrodes. Including a step of removing and planarizing the conductive film, forming a metal or metal silicide layer on the surface of the separated conductive film, and forming the second electrode.
According to this method, a charge transfer electrode with easy control and low resistance can be easily formed.

  In the present invention, the planarization step may be a resist etch back step.

In the present invention, the planarization step may include a step of planarizing by chemical mechanical polishing (CMP).
Since the metal or metal silicide on the upper surface of the first electrode acts as an etching stopper when the second electrode is patterned, a flat surface can be efficiently formed without reducing the film thickness.

In the present invention, the pattern of the first electrode includes a dummy pattern having no electrical connection in the peripheral portion.
By forming the dummy pattern, it is possible to prevent film loss due to overpolishing by CMP and overetching by resist etchback at the peripheral edge of the substrate.
In the method of the present invention, the step of forming the second electrode includes forming a silicon-based conductive film as the second-layer conductive film, planarizing and separating the first electrode, and then separating the metal layer. And forming a silicide, and removing the metal layer that has not been silicided.
As a result, the second electrode can be patterned between the first electrodes in a self-aligned manner without using photolithography.

  According to the present invention, the charge transfer electrode is flattened and thinned, and both the first layer and the second layer conductive film contain metal or metal silicide, so that low-resistance and high-sensitivity solid-state imaging is achieved. An element can be formed.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
As shown in FIGS. 1 and 2, the solid-state imaging device includes a first electrode A in which the charge transfer electrode is formed of a first-layer conductive film having a polymetal structure including a polycrystalline silicon layer 3a and a tungsten silicide film 4a. And a second electrode B made of a second conductive film having a silicide structure made of a polycrystalline silicon layer 3b and a titanium silicide 4S, and formed in a single layer electrode structure, To do.

  According to the above configuration, the first electrode A and the second electrode B are alternately arranged in parallel, and both are configured to include metal or metal silicide. Therefore, planarization is possible and low resistance is achieved. Therefore, no shunt wiring is required, and both vertical shrinking and high speed are possible. Accordingly, miniaturization is possible, and it is possible to form a solid-state imaging device with high sensitivity and high reliability.

The other structure is the same as that of a conventional solid-state imaging device, and includes a photoelectric conversion unit 30 and a charge transfer unit 40 that includes a charge transfer electrode that transfers charges generated by the photoelectric conversion unit 30. A light-shielding film (not shown) formed to have an opening in the conversion part, and a flattening film made of a BPSG (borophosphosilicate glass) film filled in the photoelectric conversion part so that the surface is substantially flat. An intermediate layer 70 is provided, and a filter 50 and a lens 60 are formed on the intermediate layer.
As a result, the surface can be satisfactorily flattened, and the thickness can be greatly reduced.

  The gate oxide film 2 is composed of a three-layer structure film of a silicon oxide film 2a, a silicon nitride film 2b, and a silicon oxide film 2c.

  1 is a schematic cross-sectional view, and FIG. 2 is a schematic plan view. A plurality of photodiode regions 30 are formed on the silicon substrate 1, and a charge transfer unit 40 for transferring signal charges detected in the photodiode regions 30 is formed between the photodiode regions 30.

  Although not shown in FIG. 2, the charge transfer channel through which the signal charge transferred by the charge transfer electrode moves is formed in a direction crossing the direction in which the charge transfer unit 40 extends.

  In FIG. 2, the description of the interelectrode insulating film formed near the boundary between the photodiode region 30 and the charge transfer portion 40 is omitted.

  As shown in FIG. 1, a photodiode 30, a charge transfer channel (not shown), a channel stop region (not shown), and a charge readout region (not shown) are formed in the silicon substrate 1. A gate oxide film 2 is formed on the surface of the substrate 1. On the surface of the gate oxide film 2, charge transfer electrodes (a first electrode A composed of a first layer polycrystalline silicon film 3a and a tungsten film 4a, a second layer composed of a second layer polycrystalline silicon film 3b and a tungsten silicide 4S) are formed. Electrode B) and the interelectrode insulating film 8 made of a silicon oxide film formed on the side wall of the first electrode A are formed side by side to constitute a single-layer electrode structure.

  Although the charge transfer unit 40 is as described above, an intermediate layer 70 is formed on the upper surface of the charge transfer electrode of the charge transfer unit 40 as shown in FIG. A light-shielding film (not shown) and an antireflection layer made of a silicon nitride film are provided except for the photodiode region 30 (photoelectric conversion portion), and a flattening film made of a BPSG film is formed in the recess. A passivation film made of a transparent resin film is provided on the upper layer.

A color filter 50 and a microlens 60 are further provided above the intermediate layer 70. Further, a flattening layer made of an insulating transparent resin or the like may be filled between the color filter 50 and the microlens 60 as necessary.
In this example, a so-called honeycomb-structured solid-state imaging device is shown, but it goes without saying that the present invention can also be applied to a square lattice type solid-state imaging device.

Next, the manufacturing process of the solid-state imaging device will be described in detail with reference to FIGS. 3 to 9.
First, a 15 nm thick silicon oxide film 2a, a 50 nm thick silicon nitride film 2b, and a 10 nm thick silicon oxide film are formed on the surface of an n-type silicon substrate 1 having an impurity concentration of about 1.0 × 10 ¹⁶ cm ^−3. A film 2c is formed, and a gate oxide film 2 having a three-layer structure is formed.

  Subsequently, a first polycrystalline silicon film 3a having a thickness of 50 to 300 nm is formed on the gate oxide film 2 by a low pressure CVD method. The substrate temperature at this time shall be 500-600 degreeC. Then, a tungsten silicide film 4a having a thickness of 100 to 300 nm is formed on this upper layer by CVD. Further, a silicon nitride film 5 having a thickness of 50 to 100 nm and a silicon oxide film 6 having a thickness of 100 to 200 nm using plasma TEOS are sequentially laminated on this upper layer by CVD (FIG. 3A).

  Thereafter, a first resist pattern is formed by photolithography (FIG. 3B).

Then, the silicon oxide film 6 and the silicon nitride film 5 are etched by reactive ion etching using CHF ₃ , C ₂ F ₆ , O ₂ and He (FIG. 3C), and a resist pattern R 1 is obtained by ashing. Is removed to form a hard mask (FIG. 3D).

The tungsten silicide film 4a and the first-layer polycrystalline silicon film 3a are etched using the hard mask composed of the two-layer film of the silicon oxide film 6 and the silicon nitride film 5 thus obtained (FIG. 4A). ). In this etching, reactive ion etching using a mixed gas of HBr and O ₂ is performed to form wiring for the first electrode and the peripheral circuit. Here, it is desirable to use an etching apparatus such as an ECR (Electron Cyclotoron Resonance) system or an ICP (Inductively Coupled Plasma) system.

Thereafter, the surface is thermally oxidized in an N ₂ + O ₂ atmosphere at 900 ° C., thereby forming a silicon oxide film 7 having a film thickness of 15 nm on the side wall of the first electrode (FIG. 4B).

  Then, an HTO (silicon oxide) film 8 having a film thickness of 200 to 400 nm is formed on this upper layer by low pressure CVD (FIG. 4C).

  Then, the silicon oxide film 8 deposited on the horizontal portion by reactive ion etching is removed and left on the side wall to form a side wall (insulating film) (FIG. 4D). At this time, in order to reduce the damage caused by the reactive ion etching on the substrate surface, it is made to remain slightly in the horizontal portion.

  Subsequently, the silicon oxide film remaining on the horizontal portion is removed by wet etching (FIG. 5A).

Thereafter, the surface of the NO film (silicon oxide film 2a and silicon nitride film 2b) is further oxidized by thermally oxidizing the surface in an N ₂ + O ₂ + H ₂ atmosphere at 950 ° C., and the silicon oxide removed by wet etching is used. The membrane is replenished (FIG. 5 (b)). At this time, since the substrate surface is the silicon nitride film 2b, only a small amount of the silicon oxide film is formed.

  Further, an HTO (silicon oxide) film 8S having a film thickness of 3 to 10 nm is formed as a top oxide film of the ONO film on this upper layer by a low pressure CVD method (FIG. 5C).

  Subsequently, a second-layer polycrystalline silicon film 3b is formed on the upper layer by a low pressure CVD method so as to be equal to or higher than the height of the first electrode. The substrate temperature at this time is set to 500 to 600 ° C. (FIG. 6A).

  Further, the projecting second layer polycrystalline silicon film 3b is removed by CMP to planarize the surface (FIG. 6B).

  Further, a titanium film 4b having a thickness of 50 to 300 nm is formed (FIG. 6C), and silicidation is performed by annealing at 650 to 750 ° C. for 30 to 120 seconds by the RTA method to form titanium silicide 4S (FIG. 6). 7 (a)).

  Thereafter, the unreacted film is removed by SC-1 treatment (ammonia hydrogen peroxide treatment), and an annealing treatment at 750 to 850 ° C. for 30 to 120 seconds is performed (FIG. 7B).

Then, patterning of the electrode is performed to open the window of the photoelectric conversion unit.
First, similarly to the patterning of the first electrode, a silicon nitride film 9 having a thickness of 50 to 100 nm for forming a hard mask and a silicon oxide film 10 having a thickness of 100 to 200 nm are formed using plasma TEOS (see FIG. FIG. 7 (c)).

  Thereafter, a second resist pattern R2 is formed by photolithography (FIG. 8A).

Then, this silicon oxide film 10 is etched by reactive ion etching using CHF ₃ , CF ₄ and Ar (FIG. 8B), and the resist pattern R 2 is removed by ashing to form a hard mask (FIG. 8). (C)).

The tungsten silicide layer 4S and the second-layer polycrystalline silicon film 4a are etched using the hard mask composed of the two-layer film of the silicon oxide film 10 and the silicon nitride film 9 thus obtained (FIG. 9A). ). In this etching, reactive ion etching using a mixed gas of HBr and O ₂ or Cl ₂ and O ₂ is performed to form a window of the photoelectric conversion portion. Here, it is desirable to use an etching apparatus such as ECR or ICP.

  Then, an HTO (silicon oxide) film 11 having a thickness of 500 nm is formed (FIG. 9B).

  Then, the silicon oxide film 11 deposited on the horizontal portion is removed by reactive ion etching and left on the side wall to form a side wall (FIG. 9C). At this time, in order to reduce the damage caused by the reactive ion etching on the substrate surface, it is made to remain slightly in the horizontal portion.

  Subsequently, the silicon oxide film 11 remaining on the horizontal portion is removed by wet etching (FIG. 9D).

  In this way, a low resistance charge transfer electrode is formed.

  Then, an intermediate layer 70 such as an antireflection film, a light shielding layer, and a flattening film is formed, and a color filter 50, a microlens 60, and the like are formed, and a solid-state imaging device as shown in FIGS. 1 and 2 is obtained.

  According to this solid-state imaging device, the charge transfer electrode includes a first electrode composed of the polycrystalline silicon layer 3a and the tungsten silicide film 4a, and a second electrode composed of the polycrystalline silicon layer 3b and the titanium silicide layer 4S. Since the electrodes are alternately arranged through the sidewalls formed of the silicon oxide films 8 and constitute a low-resistance single-layer structure electrode, no shunt wiring is required, and high speed and miniaturization are possible.

  According to this method, it is possible to form a miniaturized structure having an interelectrode distance of about 0.1 μm.

Further, in the planarization step, film loss can be prevented by using an etching stopper or using a dummy pattern. This may be effective in planarization by CMP. The dummy pattern used here may not have electrical connection with the peripheral circuit portion.
It may also serve as an etching stopper layer and an antireflection layer, and is a material having etching or polishing selectivity with respect to a BPSG film as a planarizing film, such as a silicon nitride (plasma SiN) film or a silicon oxynitride (SiON) film. I just need it. Further, a light shielding film may be used as an etching stopper. Note that the antireflection layer may be removed by etching, but the light shielding film has etching selectivity, so that film loss due to overpolishing can be prevented.

(Second Embodiment)
In the first embodiment, the first electrode and the second electrode are made of different materials, but both may have a structure in which a metal silicide layer is formed on the surface.
Further, the metal is not limited to tungsten, and can be appropriately changed such as titanium (Ti), cobalt (Co), nickel (Ni). Further, the silicon layer is not limited to polycrystalline silicon, and can be appropriately changed such as an amorphous silicon layer or a microcrystal silicon layer.

  In addition, about a manufacturing method, it can change suitably, without being limited to the said embodiment.

  As described above, according to the present invention, since the charge transfer electrode having a low-resistance and thin single-layer electrode structure is configured, the vertical shrinkage can be achieved and the margin for the light incident angle is reduced. Therefore, it is effective for forming a fine and highly sensitive solid-state imaging device such as a small camera.

It is sectional drawing which shows the solid-state image sensor of the 1st Embodiment of this invention. It is a top view which shows the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows the manufacturing process of the solid-state image sensor of the 1st Embodiment of this invention. It is a figure which shows an example of the manufacturing process of the solid-state image sensor of a prior art example. It is a figure which shows an example of the manufacturing process of the solid-state image sensor of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3a 1st layer polycrystalline silicon film 3b 2nd layer polycrystalline silicon film 4a Tungsten silicide film 4S Titanium silicide film 5 Silicon nitride film 6 Silicon oxide film 8 Silicon oxide film 9 Silicon nitride film 10 Silicon oxide Film 30 Photodiode region 40 Charge transfer unit 50 Color filter 60 Micro lens 70 Intermediate layer

Claims (10)

In a solid-state imaging device including a photoelectric conversion unit, and a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit,
The charge transfer electrode is formed by alternately arranging first electrodes made of a first layer conductive film and second electrodes made of a second layer conductive film,
A solid-state imaging device, wherein both the first layer and the second layer conductive film contain metal or metal silicide. The solid-state imaging device according to claim 1,
A solid-state imaging device characterized in that at least the surface of the second layer conductive film is made of metal silicide. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein the first layer conductive film and the second layer conductive film are made of polymetal. The solid-state imaging device according to any one of claims 1 to 3,
The solid-state imaging device, wherein the first electrode is surrounded by a sidewall insulating film. The solid-state imaging device according to any one of claims 1 to 4,
A solid-state imaging device, wherein an inter-electrode distance between the first and second electrodes is 0.1 μm or less. A method of manufacturing a solid-state imaging device comprising a photoelectric conversion unit and a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit,
The charge transfer electrode manufacturing process comprises:
Forming a first electrode made of a first layer conductive film containing metal or metal silicide;
Forming an insulating film on a sidewall of the first electrode;
A second layer conductive film is formed on the insulating film, and the second layer conductive film is separated on the first electrode so that the second electrode is located between the first electrodes. Forming the second electrode by forming a metal or metal silicide layer on the surface of the separated conductive film, and forming the second electrode. Method. It is a manufacturing method of the solid-state image sensing device according to claim 6,
The planarization step is a method for manufacturing a solid-state imaging device, which is a resist etch-back step. It is a manufacturing method of the solid-state image sensing device according to claim 6,
The method of manufacturing a solid-state imaging device, wherein the planarizing step is a step of planarizing by chemical mechanical polishing (CMP). A method for manufacturing a solid-state imaging device according to any one of claims 6 to 8,
The method of manufacturing a solid-state imaging device, wherein the pattern of the first electrode includes a dummy pattern having no electrical connection at a peripheral portion. A method for manufacturing a solid-state imaging device according to any one of claims 6 to 9,
The step of forming the second electrode includes forming a silicon-based conductive film as the second-layer conductive film, planarizing and separating by the first electrode, forming a metal layer, siliciding, A method of manufacturing a solid-state imaging device, comprising a step of removing the metal layer that has not been silicided.

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