JP2004103616A - Solid-state imaging device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge transfer element which is kept free from a breakdown voltage failure at a narrow gap between the electrodes or a short circuit between the electrodes even when rising occurs in a silicifying process, and to provide a method of manufacturing a solid-state imaging device which is easily manufactured and very reliable. <P>SOLUTION: The method of manufacturing the solid-state imaging device comprises a first process of forming a polycrystalline silicon film on the surface of a semiconductor substrate which is surrounded with an inter-electrode insulating film and equipped with a gate oxide film formed on it so as to make its upper end located below the upper end of the inter-electrode insulating film, a second process of forming a metal film on the polycrystalline silicon film, a third process of silicifying the metal film by heating, and a fourth process of selectively removing the metal film which is not silicified. The metal silicide layer is so formed as to enable the upper end of the inter-electrode insulating film to protrude. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a method for manufacturing the same, and more particularly to silicidation of a charge transfer electrode.
[0002]
[Prior art]
A CCD solid-state imaging device used for an area sensor or the like has a charge transfer electrode for transferring a signal charge from a photoelectric conversion unit. A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer path formed on the semiconductor substrate, and are sequentially driven.
[0003]
In the solid-state imaging device, the number of imaging pixels is increasing, but with the increase in the number of pixels, high-speed transfer of signal charges, that is, driving with a high-speed pulse of the charge transfer electrode is required. Is required. As a method for reducing the resistance, it has been proposed that the charge transfer electrode has a two-layer structure of a silicon-based conductive material such as polycrystalline silicon and a metal silicide.
[0004]
However, unlike a polycrystalline silicon electrode, it is technically difficult to process a metal electrode. For example, the surface of the electrode metal material has a higher surface reflectance than that of polycrystalline silicon, causing halation problems when patterning, and a new technique and apparatus are required to process the metal material.
Therefore, a salicide process, which is a process for processing sources and drains and electrodes in a selective and self-alignment manner, which has been put into practical use in logic, etc., has attracted attention. By using this technique, electrode processing is first performed using only polycrystalline silicon, so there is no problem of halation due to surface reflection, and no new technique or apparatus for metal processing is required.
However, in the case of a charge transfer element, the distance between the electrodes is narrow, so that a short circuit between the electrodes and a defective withstand voltage become a problem due to the so-called “rising” phenomenon during silicidation.
[0005]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and provides a charge transfer element that does not cause a breakdown voltage failure or a short-circuit between electrodes even if a “swelling” phenomenon occurs in a silicidation process. For the purpose.
[0006]
It is another object of the present invention to provide a method for manufacturing a solid-state imaging device that is easy to manufacture and highly reliable.
[0007]
[Means for Solving the Problems]
Therefore, in the present invention, the charge transfer electrode of the solid-state imaging device has an upper end higher than the upper end of the interelectrode insulating film in a region surrounded by a wall-like interelectrode insulating film formed to stand on the surface of the semiconductor substrate. Is formed of a silicon-based conductive film formed so as to be positioned below and a metal silicide layer formed on the silicon-based conductive film.
[0008]
According to such a configuration, in order not to be affected by the rising phenomenon, the silicon-based conductivity is lowered and the inter-electrode insulating film is protruded upward. Therefore, it is possible to form a solid-state imaging device with low resistance and high reliability.
[0009]
Further, in the method of the present invention, a silicon-based material is insulated and separated so that the upper end is located below the upper end of the interelectrode insulating film on the surface of the semiconductor substrate surrounded by the interelectrode insulating film and formed with the gate oxide film. A step of forming a conductive film, a step of forming a metal film on the silicon-based conductive film, a step of heating the metal film to perform silicidation, and a metal film remaining without silicidation are selected. A metal silicide layer is formed so that the upper end of the interelectrode insulating film protrudes.
[0010]
According to such a configuration, the low resistance electrode can be formed in a self-aligned manner, so that the resistance of the electrode can be reduced without being affected by misalignment in the photolithography process or halation due to reflection on the surface specific to the metal material. It is possible to measure.
In addition, the silicon-based conductive film is formed so that the upper end thereof is positioned below the upper end of the interelectrode insulating film by a certain height, and a metal film is formed thereon. Even if the rising occurs, the silicide film can be formed in a self-aligned manner without causing a short circuit. The fixed height is a height that does not cause a short circuit even if a rise occurs due to the formation of the metal silicide film. In addition, when the silicon is diffused into the metal film and silicide is formed, the region where Si is exposed is silicided, and then Si diffuses into the surrounding metal and silicidation proceeds. The so-called lateral growth occurs, which extends along the interelectrode insulating film side wall.
In addition, a photolithography process and an etching process necessary for forming a low resistance layer such as a metal layer are not required, and the yield can be improved by reducing the number of processes.
[0011]
When the charge transfer electrode has a single layer structure, it can be formed by the same process. For the formation of the electrode pattern, a silicon conductive film pattern is formed by a single photolithography process, and a metal silicide is formed on the pattern. By forming, a low-resistance charge transfer electrode including a metal silicide film can be formed in a self-aligning manner.
[0012]
When the charge transfer electrode has a two-layer structure, the step of forming the silicon-based conductive film includes a step of forming a pattern of the first-layer silicon-based conductive film, and a step of forming the first-layer silicon-based conductive film. An interelectrode insulating film is formed so as to protrude from the side wall of the pattern, and is lifted on the pattern of the first-layer silicon-based conductive film through the insulating film from between the patterns of the first-layer silicon-based conductive film The step of forming the pattern of the second-layer silicon-based conductive film formed as described above can be used.
[0013]
In silicidation, the first layer silicon-based conductive film and the second layer silicon-based conductive film and the interelectrode insulating film are formed, and then a metal film is formed and heated. By forming a metal silicide layer by an interfacial reaction between the first layer silicon-based conductive film and the second layer silicon-based conductive film, two layers of silicide can be formed in one heating step, and heat treatment is performed. It becomes possible to reduce.
[0014]
Furthermore, if the surface of the silicon-based conductive film or the first-layer silicon-based conductive film and the second-layer silicon-based conductive film is etched to form a recess, a short circuit can be generated even if a rise occurs. There is no risk of inviting.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 shows a schematic configuration of the solid-state imaging device according to the first embodiment of the present invention. Fig.1 (a) is a schematic plan view which shows from the photoelectric conversion part to a charge transfer electrode, and FIG.1 (b) is AA sectional drawing.
This solid-state imaging device has a polycrystalline silicon film arrayed on a surface of a silicon substrate 1 on which a desired element region is formed via a gate oxide film 2 as shown in a cross-sectional view of the main part in FIG. A plurality of charge transfer electrodes 40 composed of a two-layer structure film of titanium and titanium silicide are surrounded by an interelectrode insulating film 3 composed of a silicon oxide film that forms a wall-like pattern standing up to a position higher than the upper end of the polycrystalline silicon film In other words, a solid-state imaging device free from defective withstand voltage or short circuit is formed. Here, the wall-shaped pattern is formed to have a width of about 0.1 μm.
[0016]
This solid-state imaging device is formed in an array on the surface of a silicon substrate 1 on which a desired device region is formed via a gate oxide film 2 as shown in FIG. The titanium film 4S is formed on the polycrystalline silicon films 4a and 4b in which the charge transfer electrode 40 having a two-layer structure is formed such that the upper end is located below the upper end of the interelectrode insulating film, and silicidation is performed. Then, by selectively removing the titanium film remaining without being silicided, a metal silicide layer is formed so that the upper end of the interelectrode insulating film protrudes in a self-aligning manner.
[0017]
The interelectrode insulating film 3 is formed of a so-called sidewall oxide film in which a silicon oxide film formed on the pattern of the first layer polycrystalline silicon film as the first layer electrode is left only on the sidewall by anisotropic etching. Thus, a fine pattern is obtained without going through a lithography process.
[0018]
Further, a second-layer polycrystalline silicon film 4b is formed on the first-layer polycrystalline silicon film 4a through the insulating film 6 from between the first-layer polycrystalline silicon film 4a constituting the first-layer electrode. Has been.
[0019]
As shown in FIG. 1, a plurality of photodiodes 30 are formed on the silicon substrate 1, and the charge transfer electrodes 40 for transferring signal charges detected by the photodiodes have a meandering shape between the photodiodes 30. It is formed to exhibit.
Although not shown in FIG. 1A, the charge transfer channel 31 through which the signal charge transferred by the charge transfer electrode 40 moves has a meandering shape in a direction crossing the direction in which the charge transfer electrode 40 extends. It is formed to exhibit. In FIG. 1A, the description of the interelectrode insulating film 3 formed near the boundary between the photodiode region and the charge transfer electrode 40 is omitted.
[0020]
As shown in FIG. 1B, a photodiode 30, a charge transfer channel 31, a channel stop region 32, and a charge readout region 33 are formed in the silicon substrate 1, and a gate oxide film 2 is formed on the surface of the silicon substrate 1. Is formed. An interelectrode insulating film 3 made of a silicon oxide film and a charge transfer electrode 40 are formed on the surface of the gate oxide film 2.
[0021]
Although the charge transfer electrode 40 is as described above, a silicon oxide film (not shown) as an interlayer insulating film is formed on the upper surface of the charge transfer electrode 40.
[0022]
Above the solid-state imaging device, a light shielding film 50 is provided except for the photodiode 30, and a color filter 60 and a microlens 70 are further provided. Further, an insulating transparent resin or the like is filled between the charge transfer electrode 40 and the light shielding film 50 and between the light shielding film 50 and the color filter 60. Except for the charge transfer electrode 40 and the interelectrode insulating film 3, the description is omitted because it is the same as the usual one. Further, FIG. 1 shows a so-called honeycomb-structured solid-state imaging device, but it goes without saying that the present invention can also be applied to an interline-type solid-state imaging device.
[0023]
Next, the manufacturing process of this solid-state image sensor will be described.
First, a silicon oxide film having a thickness of 15 nm, a silicon nitride film having a thickness of 50 nm, and a silicon oxide film having a thickness of 10 nm are formed on the surface of the n-type silicon substrate 1 to form a gate insulating film 2 having a three-layer structure. To do.
[0024]
Subsequently, as shown in FIG. 2A, a first layer polycrystal having a thickness of 0.4 μm is formed on the gate insulating film 2 by a low pressure CVD method using SiH ₄ diluted with He as a reactive gas. A silicon film 4a is formed. The substrate temperature at this time shall be 600-700 degreeC. Thereafter, heat treatment is performed at 900 ° C. in a mixed gas atmosphere of POCl ₃ , N _2, and O ₂ to dope the first-layer polycrystalline silicon film 4a (phosphoric acid treatment).
[0025]
Subsequently, a positive resist is applied to the upper layer so as to have a thickness of 0.5 to 1.4 μm.
[0026]
Then, exposure is performed using a desired mask by photolithography, development and water washing are performed to form a resist pattern R having a pattern width of 0.3 to several μm as shown in FIG.
[0027]
Thereafter, as shown in FIG. 2C, the first-layer polycrystalline silicon is formed by reactive ion etching using a mixed gas of HBr and O ₂ using the resist pattern R as a mask and the gate insulating film 2 as an etching stopper. After selectively removing the film 4a by etching, the resist pattern R is peeled off. Here, it is desirable to use an etching apparatus such as ECR or ICP.
[0028]
Subsequently, as shown in FIG. 3D, second insulating films 3 and 6 made of a silicon oxide film having a thickness of 80 nm are formed on the surface of the first polycrystalline silicon film 4a by thermal oxidation. Here, the silicon oxide film (upper insulating film) on the upper surface of the first-layer polycrystalline silicon film 4 is assumed to be 6.
[0029]
In this way, the interelectrode insulating film 3 and the upper insulating film 6 which are sidewall insulating films of the first layer polycrystalline silicon film 4 are formed.
[0030]
Next, as shown in FIG. 3E, a second-layer polycrystalline silicon film 4b having a film thickness of 0.4 to 0.7 μm is formed by a low pressure CVD method using SiH ₄ gas, and the first-layer polycrystalline film is formed. Similar to the case of the silicon film 4a, patterning is performed by photolithography. Also here, phosphoric acid treatment is performed in the same manner as the first-layer polycrystalline silicon film.
[0031]
Then, as shown in FIG. 3F, a silicon oxide film 7 is formed on the upper layer by thermal oxidation.
[0032]
Thereafter, as shown in FIG. 4G, a silicon oxide film 8 is formed by a low pressure CVD method.
[0033]
Further, as shown in FIG. 4H, a thick resist R is applied and patterned so as to cover the photodiode formation region and the like.
[0034]
Further, as shown in FIG. 4 (i), the first and second polycrystalline silicon films are exposed by anisotropic etching while the peripheral portion is covered with a thick resist R, and the first The silicon oxide films 7 and 8 are left on the side walls of the first and second layer polycrystalline silicon films 4a and 4b. This is an interelectrode insulating film of the second layer electrode made of the second layer polycrystalline silicon film.
[0035]
Thereafter, as shown in FIG. 5 (j), the resist R is removed, and as shown in FIG. 5 (k), the first layer is formed by reactive ion etching using a mixed gas of HBr and O _2. The surfaces of the crystalline silicon film 4a and the second-layer polycrystalline silicon film 4b are removed by etching. In this step, the surface of the first layer polycrystalline silicon film 4a is lower than the upper end surface of the interelectrode insulating film 3, and the surface of the second layer polycrystalline silicon film 4b is lower than the upper end surfaces of the silicon oxide films 7 and 8. ing.
[0036]
Then, as shown in FIG. 5L, a titanium film 9 having a thickness of 50 to 300 nm is formed on the polycrystalline silicon films 4a and 4b by sputtering or the like.
[0037]
Subsequently, as shown in FIG. 6 (m), RTA (rapid heat treatment) at 800 ° C. for 90 seconds is performed, and titanium silicide is simultaneously formed on the interface between the first and second polycrystalline silicon films 4a and 4b and the titanium film 9. 4S is formed.
[0038]
Thereafter, as shown in FIG. 6 (n), SC-1 treatment is performed to remove the unreacted titanium film, and a charge transfer electrode having a two-layer structure of a polycrystalline silicon film and titanium silicide is formed.
Then, an insulating film, a light shielding film, and the like are formed on this upper layer to obtain a solid-state imaging device as shown in FIG.
[0039]
According to this method, the surfaces of the first layer and the second layer polycrystalline silicon films are etched to be higher than the upper ends of the interelectrode insulating film 3 and the silicon oxide films 7 and 8 as the second layer interelectrode insulating films. Therefore, even if a rising phenomenon occurs during silicidation, a breakdown voltage failure or a short circuit does not occur. Therefore, it is possible to obtain a solid-state imaging device with high reliability.
[0040]
Further, it is not necessary to pattern a metal film that has a high surface reflectance and is difficult to process due to halation or the like. That is, the pattern of the polycrystalline silicon film is formed without lowering the accuracy due to the influence of the surface reflection, silicidation is caused only on this pattern, and the metal silicide film is selectively formed, so that 2 A charge transfer electrode having a layer structure can be formed in a self-aligning manner. In addition, since the charge transfer electrode having a two-layer structure is silicided in one silicidation process, the number of high-temperature processes can be reduced. Therefore, it is possible to form a solid-state imaging device having a highly accurate and reliable charge transfer electrode without mask displacement.
[0041]
Further, when the photodiode is formed, if the metal surface is exposed when the silicon surface is exposed, contamination may be caused. In this example, the metal film is formed and the heat treatment for silicidation is performed only once, and RTA is used. It takes a short time. Therefore, even when the electrodes are formed after the formation of the photodiode, a high-quality solid-state imaging device can be formed with little displacement of the joint surface due to the extension of the diffusion length. Therefore, contamination of the photodiode by metal ions can be prevented, and reliability can be improved.
[0042]
In the above embodiment, the heat treatment temperature for silicidation was set to 800 ° C. and a titanium silicide film having a C54 structure was formed at once. However, high reliability could be maintained without a short circuit due to rising. When the heat treatment temperature is raised, the rise tends to occur, but in the case of the present embodiment, there is neither a breakdown voltage failure nor a short circuit. This is because the surfaces of the first layer and second layer polycrystalline silicon films are etched so that they are lower than the upper ends of the interelectrode insulating film 3 and the silicon oxide films 7 and 8 as the second layer interelectrode insulating films. It is thought that it is because.
In the above embodiment, the heat treatment temperature for silicidation is set to 800 ° C., and a titanium silicide film having a C54 structure is formed at once. After removing the unnecessary titanium film, a heat treatment at 800 ° C. for about 90 seconds may be performed to reduce the resistance to a C54 structure.
[0043]
As the metal film used here, in addition to titanium silicide, silicide of tantalum, tungsten, molybdenum, nickel, cobalt, platinum, or the like can be applied.
[0044]
(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the first embodiment, the charge transfer electrode having a two-layer structure formed so that the second layer runs on the first layer has been described. However, the charge transfer electrode having a single layer structure will be described.
[0045]
FIG. 7 shows a manufacturing process of the solid-state imaging device according to the second embodiment of the present invention.
Although only the charge transfer electrode portion is shown in FIG. 7, the other portions are the same as those in the first embodiment, and thus the description thereof is omitted.
[0046]
In this example, an interelectrode insulating film 3 is formed on a gate oxide film 2 formed on the surface of a silicon substrate 1, and a polycrystalline silicon film 4a and a titanium silicide film are formed in a region surrounded by the interelectrode insulating film 3. A charge transfer electrode made of 4S is formed. Further, the upper end of the interelectrode insulating film protrudes sufficiently high with respect to the upper surface of the polycrystalline silicon film before silicidation, and even if a rising phenomenon occurs due to silicidation, the interelectrode insulating film is sufficiently formed. Is configured to be higher than the silicide film.
[0047]
FIGS. 7A to 7D are process diagrams.
First, a silicon oxide film having a thickness of 15 nm, a silicon nitride film having a thickness of 50 nm, and a silicon oxide film having a thickness of 10 nm are formed on the surface of the n-type silicon substrate 1 to form a gate oxide film 2 having a three-layer structure. To do. Subsequently, a polycrystalline silicon film 4a having a film thickness of 0.4 to 0.7 μm is formed on the gate oxide film 2 by a low pressure CVD method using SiH ₄ gas as a reactive gas. _Then , patterning is performed by reactive ion etching using a mixed gas of ₂ to form an electrode pattern as shown in FIG. Here, the polycrystalline silicon film is doped by performing a heat treatment at 900 ° C. in a mixed gas atmosphere of POCl ₃ , N _2, and O ₂ before or after patterning as in the case of the first embodiment ( Phosphoric acid treatment).
[0048]
Then, as shown in FIG. 7B, the periphery of the polycrystalline silicon film is oxidized by thermal oxidation, and the upper surface is etched to leave the silicon oxide film only on the sidewalls, thereby forming the interelectrode insulating film 3. Here, an insulating film may be formed by CVD instead of thermal oxidation.
Thereafter, as shown in FIG. 7C, the surface of the polycrystalline silicon film is removed by reactive ion etching using a mixed gas of HBr and O ₂ . In this step, the surface of the polycrystalline silicon film 4a is lower than the upper end surface of the interelectrode insulating film 3 by a certain height.
[0049]
Then, a titanium film having a film thickness of 50 to 200 nm is formed on the polycrystalline silicon film 4a by a sputtering method or the like, and RTA (rapid heat treatment: first annealing) is performed at 700 ° C. for 2 minutes, thereby the polycrystalline silicon film 4a. Titanium silicide 4S is formed at the interface between the silicon film and the titanium film. Here, it has a C49 structure.
[0050]
Thereafter, SC-1 treatment is performed to remove the unreacted titanium film, and finally a heat treatment (second annealing) is performed for 30 to 120 seconds in a temperature range of 750 to 850 ° C. so that the titanium silicide film has a C54 structure. As a result, as shown in FIG. 7D, a charge transfer electrode having a two-layer structure of a polycrystalline silicon film and titanium silicide is formed.
Then, an insulating film, a light shielding film, and the like are formed on this upper layer to obtain a solid-state imaging device.
[0051]
Also by this method, it is possible to form a charge transfer electrode free of breakdown voltage as in the first embodiment.
[0052]
According to this method, the insulating film formed on the side wall of the dummy pattern is formed by leaving the side wall by anisotropic etching when forming the insulating film pattern as the inter-electrode insulating film, and is fine and reliable. A high interelectrode insulating film is easily formed.
[0053]
In the above-described embodiment, RTA as the first annealing step for silicidation is set to 700 ° C. for 90 seconds, but may be in the range of 650 to 750 ° C. and in the range of 30 to 120 seconds. Here, the titanium silicide film has a C49 structure.
And finally, as a 2nd annealing process, the temperature range of 750-850 degreeC and the heat processing for 30 to 120 second are performed, and low resistance can be achieved by making a titanium silicide film into a C54 structure.
[0054]
Also in the second embodiment, the titanium silicide film can be made into a C54 structure by performing heat treatment at a time in one annealing step (temperature range of 750 to 850 ° C., 30 to 120 seconds). . In this case, the rising is more likely to occur. However, since the upper end of the polycrystalline silicon film is formed sufficiently lower than the upper end of the interelectrode insulating film, a breakdown voltage failure or a short circuit does not occur.
[0055]
In the above embodiment, the silicide is formed by the interface reaction between the polycrystalline silicon film and the metal film. However, the silicide is not limited to the polycrystalline silicon film, and any silicon-based conductive film such as amorphous silicon or microcrystal silicon may be used. .
[0056]
【The invention's effect】
As described above, according to the present invention, a low-resistance layer can be formed in a self-aligned manner, so that it is not affected by misalignment in the photolithography process or halation due to surface reflection unique to the metal material. The resistance of the electrode can be reduced.
In addition, the photolithography process and the etching process are not required, and it is possible to improve the yield by reducing the number of processes, the manufacturing period, and the manufacturing cost.
Further, according to the present invention, it is possible to provide a solid-state imaging device having a charge transfer electrode with low resistance and high reliability.
In addition, it is possible to provide a low power consumption solid-state imaging device with low wiring resistance and capable of high-speed transfer.
In addition, the resistance of the charge transfer electrode can be reduced, and the height of the electrode can be further reduced and the surface can be flattened. Therefore, the sensitivity can be improved and the amount of damage can be reduced.
In addition, since high-speed transfer is possible, optical characteristics such as smear can be improved, and a high-quality and highly reliable solid-state imaging device can be obtained.
In addition, according to the present invention, it is possible to provide a solid-state imaging device having a single-layer electrode structure that can obtain a flat surface and does not have a sensitivity reduction.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 5 is a diagram showing a part of the manufacturing process of the solid-state imaging device according to the first embodiment of the present invention;
FIG. 6 is a diagram illustrating a part of the manufacturing process of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 7 is a diagram illustrating a part of the manufacturing process of the solid-state imaging device according to the second embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3 Interelectrode insulating film 4a (First layer) Polycrystalline silicon film 4b Second layer polycrystalline silicon film 4S Titanium silicide film 5 Silicon oxide film

Claims (6)

The charge transfer electrode of the solid-state image sensor
Silicon-based conductivity formed in a region surrounded by a wall-like interelectrode insulating film formed to stand on the surface of the semiconductor substrate so that the upper end is located below the upper end of the interelectrode insulating film A solid-state imaging device comprising a film and a metal silicide layer formed on the silicon-based conductive film. Forming a silicon-based conductive film on the surface of the semiconductor substrate surrounded by an interelectrode insulating film and having a gate oxide film formed so that the upper end is positioned below the upper end of the interelectrode insulating film;
Forming a metal film on the silicon-based conductive film;
Heating the metal film to perform silicidation;
And a step of selectively removing a metal film remaining without being silicided, and forming a charge transfer electrode comprising a silicon-based conductive film and a metal silicide layer. 3. The method of manufacturing a solid-state imaging device according to claim 2, wherein the charge transfer electrode has a single-layer structure and is formed in an entire region surrounded by an interelectrode insulating film in the same process. The step of forming the silicon-based conductive film includes a step of forming a pattern of the first-layer silicon-based conductive film, and a step of forming the first-layer silicon-based conductive film on a sidewall of the pattern of the first-layer silicon-based conductive film. An interelectrode insulating film is formed so that the upper end is located above the upper end of the conductive film, and the first-layer silicon-based conductive film is interposed between the patterns of the first-layer silicon-based conductive film via the insulating film. The method for producing a solid-state imaging device according to claim 2, further comprising a step of forming a pattern of the second-layer silicon-based conductive film formed so as to be lifted up. Further, after forming the pattern of the first layer silicon-based conductive film and the second layer silicon-based conductive film and the interelectrode insulating film,
5. The solid-state imaging device according to claim 4, wherein a metal film is formed and heated to form a metal silicide layer on the first layer silicon-based conductive film and the second layer silicon-based conductive film. Production method. 6. The method according to claim 1, further comprising a step of etching the surfaces of the silicon-based conductive film or the first-layer silicon-based conductive film and the second-layer silicon-based conductive film to form a recess. The manufacturing method of the solid-state image sensor in any one of.

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