JP2004335801A - Solid state imaging device and its fabricating process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable high sensitivity solid state imaging device by planarizing the surface of a charge transfer device employing a charge transfer electrode of single layer structure while holding flexibility in the process without lowering the yield even for a large and shrunk device having multiple pixels, and enhancing the processing accuracy at a photodiode part. <P>SOLUTION: A solid state imaging device of single layer electrode structure having a planar surface is fabricated by forming an interelectrode insulating film 6 on the sidewall of a first electrode 3 and then etching back a second electrode 7 using mask patterns 4 and 5 for forming the pattern of the first electrode as an etching stopper. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a solid-state imaging device, and more particularly to formation of a solid-state imaging device having a single-layer electrode CCD (charge coupled device) structure.
[0002]
[Prior art]
A solid-state imaging device using a CCD used for an area sensor or the like includes a photoelectric conversion unit such as a photodiode and a charge transfer unit including a charge transfer electrode for transferring a signal charge from the photoelectric conversion unit. A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer path formed on the semiconductor substrate, and are sequentially driven.
[0003]
In recent years, in solid-state imaging devices, the number of imaging pixels has increased to more than gigapixels, but with the increase in the number of pixels, high-speed transfer of signal charge, that is, driving with high-speed pulses of the charge transfer electrode is necessary, There is a need to reduce the resistance of charge transfer electrodes. In addition, an increase in size such as a brownie size has been promoted, and it has become difficult to maintain high transfer efficiency during charge transfer.
[0004]
In a conventional solid-state imaging device using a charge transfer electrode having a single layer structure, a polycrystalline silicon layer is used as the charge transfer electrode, and after forming the first layer wiring, the pattern surface of the first layer wiring is oxidized, A polycrystalline silicon layer serving as a second transfer electrode is deposited and the entire surface is etched to form a single layer of the electrode (see Patent Document 1).
[0005]
In addition, after forming an interelectrode insulating film first, a polycrystalline silicon layer or the like to be an electrode is deposited, and a resist etchback or chemical mechanical polishing method (hereinafter referred to as CMP method) is performed to form a single layer of the electrode. Therefore, there has been a problem that the flatness of the electrode cannot be obtained, and the exposure accuracy when processing the photodiode portion is lowered.
[0006]
In addition, a conventional solid-state imaging device having a charge transfer electrode having a two-layer electrode structure (see Patent Document 2) has a structure that overlaps with an adjacent electrode, and therefore has a high height.
[0007]
As described above, when the height is increased due to the overlap of the charge transfer electrodes, the step between the charge transfer electrode and the photoelectric conversion unit such as the photodiode becomes large, so that the angle at which the light source is viewed from the opening above the photodiode should be widened. Cannot be achieved, and sufficient sensitivity cannot be obtained.
[0008]
In addition, due to the deterioration of flatness, the thickness of various films such as a flattening film, inner lens, microlens, and color filter above the charge transfer electrode will be uneven and the shape variation will increase, shading, Sensitivity variation and smear deterioration due to stray light occur.
[0009]
For this reason, the method as described above has a problem that it is difficult to cope with further improvement in sensitivity.
[0010]
[Patent Document 1]
JP-A-3-246971 [Patent Document 2]
Japanese Patent Laid-Open No. 10-107254
[Problems to be solved by the invention]
As described above, in the conventional solid-state imaging device, it is difficult to flatten the charge transfer electrode having a single-layer electrode structure, and there is a problem that the yield decreases with miniaturization and high integration.
[0012]
The present invention has been made in view of the above circumstances, and in a charge transfer device using a charge transfer electrode having a single-layer structure, the yield is maintained while ensuring the degree of freedom of the process even when miniaturizing, increasing the number of pixels, and increasing the size. An object of the present invention is to provide a highly sensitive and reliable solid-state imaging device by flattening the surface without causing a decrease and improving the processing accuracy of the photodiode portion.
[0013]
[Means for Solving the Problems]
Therefore, in the present invention, when forming a solid-state imaging device having a single-layer electrode structure, an interelectrode insulating film is formed on the side wall of the first electrode, and then a mask pattern for forming the pattern of the first electrode is used as an etching stopper. The second electrode is etched back to form a solid-state imaging device having a single-layer electrode structure having a flat surface.
[0014]
That is, in a method for manufacturing a solid-state imaging device including a photoelectric conversion unit and a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit, a gate oxide film is formed on the surface of a semiconductor substrate. A step of forming a first silicon-based conductive film constituting the first electrode, a step of forming a mask layer pattern on an upper layer of the first silicon-based conductive film, and the mask layer pattern Patterning the first silicon-based conductive film as an etching mask to form a first electrode pattern; forming an interelectrode insulating film so as to cover at least a sidewall of the first electrode pattern; Forming a second silicon-based conductive film constituting the second electrode; and etching the second silicon-based conductive film using the mask layer pattern as an etching stopper Tsu and a step of click, the first electrode and the second electrode is characterized in that it is arranged alternately in a plane through the inter-electrode insulating film.
[0015]
According to this configuration, since the second electrode is etched back using the mask layer pattern for forming the first electrode as an etching stopper, a flat surface can be efficiently formed.
For this reason, the electrode wiring can be made into a single layer, and the electrode can be made low, so that the sensitivity characteristic is improved. Further, since the flatness is improved and the exposure accuracy is also improved, microfabrication is possible, and it is possible to form a solid image pickup device with high accuracy and high reliability.
[0016]
Thus, it is only necessary to use a photolithography process in the patterning process of the silicon-based conductive film, and it is possible to form an interelectrode insulating film at the end of this pattern and obtain a flat surface.
In addition, since the interelectrode insulating film is formed in a self-aligned manner, no alignment margin is required, and it becomes possible to achieve fine and high accuracy.
[0017]
The etch back step includes a step of forming a resist so as to cover the second silicon-based conductive film prior to the etch back step, and performing a resist etch back. To do.
Accordingly, it is possible to efficiently planarize the surface by selecting a condition in which the etching rates of the resist and the silicon-based conductive film are approximately equal.
Further, planarization may be performed using CMP instead of resist etch back. In this case, the second electrode is formed using the mask layer pattern for forming the first electrode as an etching stopper. And a flat surface can be efficiently formed.
[0018]
Further, the mask layer pattern is composed of a two-layer film of a silicon oxide film and a silicon nitride film formed thereon, so that a sufficient etching selectivity with respect to the silicon-based conductive film can be obtained. It becomes possible to efficiently planarize the silicon film as an etching stopper.
[0019]
In addition, the step of forming the interelectrode insulating film includes the step of surface oxidizing the first electrode pattern and oxidizing the side wall of the first electrode pattern, so that the silicon nitride film acts as an antioxidant film. A silicon oxide film can be selectively and efficiently formed only on the side wall.
[0020]
Further, the step of forming the interelectrode insulating film includes a step of forming an insulating film on the side wall of the first electrode pattern by a CVD method. It becomes possible to form.
[0021]
In addition, by including a step of etching the second silicon-based conductive film in the region to be the second electrode to be sufficiently lower than the upper end of the interelectrode insulating film, insulation isolation can be ensured. It is possible to prevent short circuit failure.
[0022]
In addition, the resistance of the electrode can be reduced by including a step of etching away the mask layer pattern on the first electrode and a step of forming a metal film on the first and second electrodes. Can be driven at high speed.
[0023]
A silicidation step of forming a metal silicide at the interface between the first and second electrodes and the metal film by a heat treatment; and a step of selectively removing the metal film remaining without being silicidized, By forming a charge transfer electrode composed of a silicon-based conductive film and a metal silicide layer, the resistance of the electrode can be further reduced, and a highly reliable solid-state imaging device electrode can be formed without short-circuit defects It becomes possible to do.
[0024]
In addition, by etching the silicon-based conductive film to a position sufficiently lower than the upper edge of the interelectrode insulating film, even if a rise occurs during silicidation, the silicide film does not cause a short circuit in a self-aligning manner. It becomes possible to form. Here, when the silicon is diffused into the metal film and silicide is formed, the silicon is diffused into the surrounding metal after the silicon is exposed to the entire area where the silicon is exposed to silicide. It progresses, and so-called lateral growth occurs, which extends along the sidewall insulating film.
[0025]
Further, by using silicidation, a photolithography process and an etching process necessary for forming a low-resistance layer such as a metal layer are not necessary, and the yield can be improved by reducing the number of processes.
[0026]
The step of forming the silicon-based conductive film includes a step of forming a polycrystalline silicon film and a step of adding impurities to the polycrystalline silicon film.
[0027]
Further, the step of forming the silicon-based conductive film includes a step of forming an amorphous silicon film while adding impurities.
Thus, an impurity implantation step is not required, and a film that is easy to manufacture and highly reliable can be formed.
[0028]
Further, if titanium silicide is used as the metal silicide film, the resistance can be further reduced.
[0029]
More preferably, if cobalt silicide is used as the metal silicide film, it is possible to form a silicide film having a lower resistance without aggregation due to heat in the subsequent process.
[0030]
Also, nickel, palladium, platinum, or tantalum silicide may be used as the metal silicide film.
[0031]
In addition, titanium, cobalt, nickel, palladium, platinum, tantalum or their nitrides, alloys, compounds, and composites are added to the top of the metal silicide layer to prevent high resistance due to aggregation of the lower layer. Is possible.
[0032]
Furthermore, prior to an etching step for planarization by anisotropic etching or the like, at least the photoelectric conversion portion or the photoelectric conversion portion forming region including the peripheral circuit region is covered with a resist pattern, and the resist is left as it is. By forming the metal film, the region where no silicide is formed is covered and protected with a resist so that the metal film is not formed.
[0033]
Further, after the step of selectively removing the metal film, an annealing step for reducing the resistance of the metal silicide film by heat treatment may be included.
[0034]
Note that this silicidation step is preferably heated to 690 to 800 ° C. in a nitrogen atmosphere.
[0035]
If the metal film remaining without being silicided is removed and then heated to 800 ° C. or higher, the low resistance of the silicide film can be achieved.
As described above, by silicidation at a low temperature of about 690 to 800 ° C. and heating at 800 ° C. or higher, a charge transfer electrode having low resistance and no fear of short circuit failure can be formed.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
1 to 3 show a method for manufacturing a solid-state imaging device according to the first embodiment of the present invention.
[0037]
As shown in FIGS. 1 to 3, the solid-state imaging device is formed by forming polycrystalline silicon on the surface of a silicon substrate 1 on which a desired device region is formed via a gate oxide film 2. An etching stopper having a two-layer structure of the silicon oxide film 4 and the silicon nitride film 5 is formed on the crystalline silicon and then patterned, and the polycrystalline silicon film is patterned using the etching stopper as a hard mask. An insulating film to be an interelectrode insulating film 6 is formed around the film, and the polycrystalline silicon film 7 is etched back on the insulating film. Then, a resist pattern R2 is formed in a region except on the photodiode portion 30, and the polycrystalline silicon film 7 on the photodiode portion 30 is removed by etching using this resist pattern as a mask.
[0038]
In this manner, a solid-state imaging device free from defective withstand voltage or short circuit is formed in order to flatten the charge transfer electrode.
This gate oxide film is constituted by a three-layer structure film of a silicon oxide film 2a, a silicon nitride film 2b, and a silicon oxide film 2c.
[0039]
4 and 5, a plurality of photodiodes 30 are formed on the silicon substrate 1, and a charge transfer unit 40 for transferring signal charges detected by the photodiodes is provided. , Between the photodiodes 30 to form a meandering shape.
[0040]
Although not shown in FIG. 4, the charge transfer channel 31 through which the signal charge transferred by the charge transfer electrode moves is formed to have a meandering shape in a direction intersecting with the direction in which the charge transfer unit 40 extends. Is done.
[0041]
In FIG. 4, the description of the interelectrode insulating film 3 formed near the boundary between the photodiode region and the charge transfer portion 40 is omitted.
[0042]
As shown in FIG. 5, a photodiode 30, a charge transfer channel 31, a channel stop region 32, and a charge readout region 33 are formed in the silicon substrate 1, and a gate oxide film 2 is formed on the surface of the silicon substrate 1. The An interelectrode insulating film 6 made of a silicon oxide film and a charge transfer electrode (first electrode 3 and second electrode 7) are formed on the surface of the gate oxide film 2.
[0043]
Although the charge transfer unit 40 is as described above, a silicon oxide film 70 as an interlayer insulating film is formed on the upper surface of the charge transfer electrode of the charge transfer unit 40.
[0044]
A light-shielding film (not shown) is provided above the solid-state imaging device except for the photodiode 30, and a color filter 50 and a microlens 60 are further provided. In addition, an insulating transparent resin or the like is filled between the charge transfer unit 40 and the light shielding film and between the light shielding film and the color filter 50. Except for the charge transfer portion 40 and the interelectrode insulating film 3, the description is omitted because it is the same as the usual one. FIG. 4 shows a so-called honeycomb-structured solid-state imaging device, but it goes without saying that the present invention can also be applied to a square lattice type solid-state imaging device.
[0045]
Next, the manufacturing process of this solid-state image sensor will be described in detail.
First, a 30-nm-thick silicon oxide film, a 50-nm-thick silicon nitride film, and a 10-nm-thick oxide film are formed on the surface of an n-type silicon substrate 1 on which a pn junction constituting the photodiode of the photoelectric conversion unit is formed. A silicon film is formed, and a gate oxide film 2 having a three-layer structure is formed.
[0046]
Subsequently, a first polycrystalline silicon film having a thickness of 0.4 μm is formed on the gate oxide film 2 by a low pressure CVD method using SiH ₄ diluted with He as a reactive gas. The substrate temperature at this time shall be 600-700 degreeC. Thereafter, heat treatment is performed at 900 ° C. in a mixed gas atmosphere of POCl ₃ , N _2, and O ₂ to dope the first-layer polycrystalline silicon film 3 (phosphoric acid treatment).
[0047]
Thereafter, a silicon oxide film 4 having a thickness of 10 nm and a silicon nitride film 5 having a thickness of 50 nm are formed by low pressure CVD.
Subsequently, a positive resist is applied to the upper layer so as to have a thickness of 0.5 to 1.4 μm.
[0048]
Then, exposure is performed using a desired mask by photolithography, development and water washing are performed to form a resist pattern R1 having a pattern width of 0.3 to several μm (FIG. 1A).
[0049]
Thereafter, the silicon oxide film 4 and the silicon nitride film 5 are etched by reactive ion etching using a mixed gas of CHF ₃ , C ₂ F ₆ , O ₂ , and He, and used for patterning the first electrode. A mask pattern is formed (FIG. 1B).
Then, the resist pattern is removed by ashing (FIG. 1C).
[0050]
Thereafter, the first polycrystalline silicon film 3 is selectively formed by reactive ion etching using a mixed gas of HBr and O ₂ using the mask pattern as a mask and the silicon nitride film 2b of the gate oxide film 2 as an etching stopper. The first electrode is formed by etching away (FIG. 1D). Here, it is desirable to use an etching apparatus such as ECR or ICP.
[0051]
Subsequently, an interelectrode insulating film 6 made of a silicon oxide film having a thickness of 80 nm is formed on the surface of the first electrode pattern by a low pressure CVD method (FIG. 2A).
[0052]
Next, a second-layer polycrystalline silicon film 7 having a film thickness of 0.8 μm is formed by a low pressure CVD method using SiH ₄ gas (FIG. 2B). At this time, the film thickness t2 of the second layer polycrystalline silicon film 7 needs to be larger than the total film thickness t1 of the film thickness of the first layer polycrystalline silicon film and the silicon oxide film and silicon nitride film thereabove. There is. Thereby, complete planarization is possible. Also here, phosphoric acid treatment is performed in the same manner as the first-layer polycrystalline silicon film.
[0053]
Then, as shown in FIG. 2C, the second-layer polycrystalline silicon film 7 is planarized by CMP. Here, an etch back method may be used.
Thereafter, as shown in FIG. 2D, a resist is applied and patterned to coat the surface other than the photodiode 30 with a resist pattern R2.
[0054]
Then, as shown in FIG. 3A, the polycrystalline silicon film on the photodiode 30 is removed by etching using the resist pattern R2 as a mask.
[0055]
Then, as shown in FIG. 3B, the resist pattern R2 is removed by ashing to form a solid-state imaging device electrode having a flat surface.
Note that the width of the interelectrode insulating film 6 can be controlled by the thickness of the silicon oxide film. As the thickness of the silicon oxide film is increased, the width of the interelectrode insulating film is increased, and the short-circuit margin between adjacent electrodes is increased. Can be spread. This silicon oxide film is formed by a low pressure CVD method, but may be a thermal oxide film or a laminated structure of a thermal oxide film and a silicon oxide film formed by the CVD method.
[0056]
Then, after forming a P-TEOS film having a thickness of 100 nm on this upper layer, a BPSG film having a thickness of 700 to 1000 nm is formed, reflowed at 850 to 900 ° C. and planarized to obtain the insulating film 70. Thereafter, a light-shielding film, a color filter 50, a microlens 60, and the like are formed to obtain a solid-state imaging device as shown in FIGS.
[0057]
In the above embodiment, the electrode is composed of a doped polycrystalline silicon film. However, the present invention is not limited to this, and an amorphous silicon film may be used. In this case, it is not necessary to implant impurities after film formation, and impurities can be implanted while forming a film.
[0058]
Of the two-layer film of the silicon oxide film and the silicon nitride film used as the mask pattern, the thickness of the silicon nitride film may be in the range of 50 to 150 nm.
Further, LP-TEOS may be used instead of the silicon nitride film.
For reactive ion etching for forming a mask pattern, a mixed gas of CF ₄ , CHF ₃ , Ar is used instead of a mixed gas of CHF ₃ , C ₂ F ₆ , O ₂ , and He. Also good.
The thickness of the gate oxide film 2 may be 25 to 35 nm for the lower silicon oxide film, and is preferably about 8 to 10 for the upper silicon oxide film.
Furthermore, the first layer polycrystalline silicon film may be 0.3 to 0.4 μm.
[0059]
(Second Embodiment)
A method for manufacturing a solid-state imaging device according to the second embodiment of the present invention will be described.
[0060]
This solid-state imaging device is characterized in that the interelectrode insulating film is formed by thermal oxidation instead of low-pressure CVD, as shown in FIGS.
That is, the first electrode is thermally oxidized using a two-layer film of a silicon oxide film and a silicon nitride film used as an etching stopper when planarizing the patterning mask of the first electrode and the second electrode as an antioxidant film. Thus, a silicon oxide film is selectively formed on the side wall of the first electrode, and this is used as an inter-electrode insulating film. The resist pattern R1 is formed in the same manner as in the first embodiment shown in FIGS. 1 to 3 except that the width of the resist pattern R1 is increased so as to increase the width.
Here, the steps of FIGS. 6A to 6D are the same as those of the first embodiment except that the width of the resist pattern R1 is increased so as to increase the width of the first electrode as described above. It is formed in the same way as the form.
Then, as shown in FIG. 7A, heat treatment is performed for 30 minutes in an oxygen atmosphere at 900 ° C. using silicon nitride 5 as an antioxidant film, thermal oxidation is performed, and a thickness of 80 nm is formed on the side wall of the first polycrystalline silicon film. The interelectrode insulating film 6S is formed. The rest is the same as in the first embodiment, and as shown in FIGS. 8A and 8B, a charge transfer electrode having a flat surface is formed.
According to such a configuration, since the interelectrode insulating film is dense, there is no short-circuit failure with a small gap, so that a finer electrode structure can be obtained.
[0061]
(Third embodiment)
In the first and second embodiments, the electrode structure is a single layer of a polycrystalline silicon film. In this example, the resistance is reduced by forming an electrode with a metal silicide layer. To do.
FIG. 9 shows a method for manufacturing a solid-state imaging device according to the third embodiment of the present invention.
[0062]
According to the method of the first and second embodiments, a charge transfer electrode forming step is formed. In this solid-state imaging device, after forming a charge transfer electrode having a single layer structure in the steps of FIGS. 1 to 3, the silicon nitride film 5 is removed by etching as shown in FIG. 9A. Thus, the silicon nitride film in the photodiode portion is removed.
Then, as shown in FIG. 9B, after the silicon oxide film 4 is removed, the polycrystalline silicon film 7 is etched back using etching conditions that are selective to the silicon oxide film 4.
In this way, the surfaces of the polycrystalline silicon films 3 and 7 are made lower than the interelectrode insulating film 6.
[0063]
Then, a titanium film having a thickness of 50 to 300 nm is formed on the polycrystalline silicon film constituting the first electrode 3 and the second electrode 7 by a sputtering method or the like.
Here, prior to sputtering of the titanium film, sputter etching with argon plasma is performed in the sputtering apparatus, and after removing the natural oxide film on the surface of the polycrystalline silicon film, sputtering of the titanium film is continuously performed without exposure to the atmosphere. By doing so, the resistance can be stably reduced.
[0064]
Subsequently, as shown in FIG. 9C, RTA (rapid heat treatment) at 760 ° C. for 90 seconds is performed, and titanium is simultaneously formed on the interface between the polycrystalline silicon film and the titanium film of the first and second electrodes 3 and 7. Silicide 8 is formed. Note that the heating temperature for silicidation is optimal at 760 ° C. for polycrystalline silicon doped with phosphorus to a degenerate concentration.
[0065]
Here, since n + polycrystalline silicon, which has a slower silicidation reaction than p + polycrystalline silicon, is unlikely to rise due to silicidation, it may be heated at a temperature of 760 ° C. or higher in preference to low resistance. it can.
[0066]
At this time, the reaction between the polycrystalline silicon and titanium occurs only on the first and second electrodes, and titanium on the photodiode covered with the interelectrode insulating film 6 or on the peripheral circuit covered with the insulating film. Remains unreacted.
[0067]
Thereafter, SC-1 treatment using a mixed solution of ammonia and hydrogen peroxide is performed to remove the unreacted titanium film, and an annealing process is performed at 800 ° C. for 90 seconds to reduce the resistance of titanium silicide. A charge transfer electrode having a two-layer structure of a crystalline silicon film and titanium silicide is formed.
[0068]
According to this method, the sidewall insulating film is formed on the sidewalls of the polycrystalline silicon film constituting the first and second electrodes, and the titanium silicide film is formed on the surface of the polycrystalline silicon film exposed from the sidewall insulating film. Therefore, no breakdown voltage failure or short circuit occurs. Accordingly, it is possible to obtain a fine and highly reliable solid-state imaging device.
[0069]
The ion implantation for forming the photoelectric conversion portion is performed before the formation of the charge transfer electrode. However, the present invention is not limited to this, and the ion implantation may be performed during or after the formation of the charge transfer electrode.
[0070]
As the metal silicide film used here, in addition to titanium silicide, silicide of tantalum, tungsten, molybdenum, nickel, cobalt, platinum, or the like can be applied. Further, nitrides, alloys, compounds, and composites of titanium, tantalum, tungsten, molybdenum, nickel, cobalt, platinum may be formed on the upper layer of these metal silicides.
[0071]
In the above embodiment, a polycrystalline silicon film is used as the silicon-based conductive film. However, the present invention is not limited to the polycrystalline silicon film, and other silicon-based conductive films such as amorphous silicon and microcrystal silicon are used. May be.
[0072]
【The invention's effect】
As described above, according to the solid-state imaging device of the present invention, the second electrode is planarized by using the mask pattern for patterning the first electrode as an etching stopper. Thus, it is possible to improve the exposure accuracy and the exposure accuracy. By improving the processing accuracy of the photodiode portion, it is possible to form a solid-state imaging device with high sensitivity and high reliability.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a manufacturing process of a solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention.
FIG. 4 is a diagram illustrating a solid-state imaging element according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing the solid-state imaging element according to the first embodiment of the present invention.
FIG. 6 is a diagram illustrating a manufacturing process of the solid-state imaging device according to the second embodiment of the present invention.
FIG. 7 is a diagram illustrating a manufacturing process of the solid-state imaging device according to the second embodiment of the present invention.
FIG. 8 is a diagram showing a manufacturing process of the solid-state imaging device according to the second embodiment of the present invention.
FIG. 9 is a diagram illustrating a part of the manufacturing process of the solid-state imaging device according to the third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3 1st electrode (1st layer polycrystalline silicon film)
4 Silicon oxide film 5 Silicon nitride film 6 Interelectrode insulating film 7 Second electrode (second layer polycrystalline silicon film)
8 Titanium silicide film 6S Interelectrode insulating film 30 Photodiode part 40 Charge transfer part 50 Color filter 60 Micro lens 70 Silicon oxide film

Claims (8)

In a method for manufacturing a solid-state imaging device, comprising: a photoelectric conversion unit; and a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit.
The step of forming the charge transfer electrode comprises:
Forming a first silicon-based conductive film constituting the first electrode on a semiconductor substrate surface via a gate oxide film;
Forming a mask layer pattern on an upper layer of the first silicon-based conductive film;
Patterning the first silicon-based conductive film using the mask layer pattern as an etching mask to form a first electrode pattern;
Forming an interelectrode insulating film so as to cover at least the side wall of the first electrode pattern;
Forming a second silicon-based conductive film constituting the second electrode;
Etching back the second silicon-based conductive film using the mask layer pattern as an etching stopper,
A method of manufacturing a solid-state imaging device, wherein a charge transfer electrode in which a first electrode and a second electrode are alternately arranged on a plane via an interelectrode insulating film is formed. The step of etching back includes a step of forming a resist so as to cover the second silicon conductive film prior to the etch back step, and performing a resist etch back. Item 2. A method for manufacturing a solid-state imaging device according to Item 1. 3. The method of manufacturing a solid-state imaging device according to claim 1, wherein the mask layer pattern is a two-layer film of a silicon oxide film and a silicon nitride film formed thereon. 4. The solid-state imaging device according to claim 3, wherein the step of forming the interelectrode insulating film includes a step of surface oxidizing the first electrode pattern and oxidizing a side wall of the first electrode pattern. 5. Production method. 4. The method of manufacturing a solid-state imaging device according to claim 3, wherein the step of forming the interelectrode insulating film includes a step of forming an insulating film on a sidewall of the first electrode pattern by a CVD method. 6. The method according to claim 1, further comprising: etching the second silicon-based conductive film in a region to be the second electrode so as to be sufficiently lower than an upper end of the interelectrode insulating film. The manufacturing method of the solid-state image sensor in any one of. Etching away the mask layer pattern on the first electrode;
The method of manufacturing a solid-state imaging device according to claim 6, further comprising: forming a metal film on the first and second electrodes. A silicidation step of forming a metal silicide at an interface between the first and second electrodes and the metal film by heat treatment;
And a step of selectively removing the metal film remaining without being silicided, and forming a charge transfer electrode comprising a silicon-based conductive film and a metal silicide layer. Manufacturing method of imaging device.

Images