JP2005323200A - Differential output circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce radiation noise and power supply/ground noise and to attain low power consumption. <P>SOLUTION: A differential output circuit comprises resistors 21 to 23 which are connected in series to form potential points 24, 25 obtained by dividing potential between power supply potential and ground potential, a smoothing capacitor 26 connected between both the potential points 24, 25, a first switch 27 inserted between the potential point 24 having higher potential out of the potential points 24, 25 and a first output terminal 28, a second switch 30 inserted between the potential point 25 having lower potential out of the potential points 24, 25 and the first output terminal 28, a third switch 33 inserted between the potential point 25 and a second output terminal 34, and a fourth switch 36 inserted between the potential point 24 and the second output terminal 34. The first and second switches 27, 30 and the third and fourth switches 33, 36 are respectively complementarily opened and closed to simultaneously obtain logical output signals to be transited to mutually opposite polarities from the first and second output terminals 28, 34. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a differential output circuit suitable for application to a logic output circuit.

  Conventionally, a CMOS (complementary metal oxide semiconductor) inverter type output circuit as shown in FIG. 3 has been widely used as a logic output circuit. In FIG. 3, reference numeral 1 denotes a data input terminal. This input terminal 1 is connected to the gate of the p-type MOS transistor 2 and to the gate of the n-type MOS transistor 3, and a power supply voltage of, for example, 2.5 V is applied. The power supply terminal 4 to be supplied is connected to the source of the MOS transistor 2, the drain of the MOS transistor 2 is connected to the drain of the MOS transistor 3, the source of the MOS transistor 3 is grounded, and each of the MOS transistors 2 and 3 is connected. The output terminal 5, which is a connection point of the drains, is grounded via a capacitive load 6, for example.

  Since the amplitude of the logic output signal of the logic output circuit shown in FIG. 3 is the same as the power supply voltage, for example, 2.5 V, the noise radiation from the signal line is large, and when the capacitive load 6 is driven, Since the pulsed current generated by charging / discharging flows into the power supply or ground via the driving transistor, there is a disadvantage that large noise is generated in these.

  Conventionally, as shown in FIG. 4, a differential output circuit having a CML (current mode logic) circuit configuration composed of a load resistor, a source-coupled (or emitter-coupled) differential switch, and a constant current source has been proposed.

  4, in FIG. 4, reference numeral 10 denotes a power supply terminal to which a power supply voltage of, for example, 2.5 V is supplied. The power supply terminal 10 is connected to a differential switch via a load resistor 11 a of 3.3 KΩ, for example. The power source terminal 10 is connected to the drain of the n-type MOS transistor 12b constituting the differential switch through the load resistor 11b of 3.3 KΩ, for example, while being connected to the drain of the n-type MOS transistor 12a.

  The sources of the MOS transistors 12 a and 12 b are connected to each other, and the connection point of the sources is grounded via the constant current circuit 13. Data obtained at the data input terminal 14a is supplied to the gate of the MOS transistor 12a, and inverted data obtained at the data input terminal 14b is supplied to the gate of the MOS transistor 12b.

  The connection point between the load resistor 11a and the drain of the MOS transistor 12a is connected to one output terminal 15a. The one output terminal 15a is grounded via the capacitive load 16a and the drain of the load resistor 11b and the MOS transistor 12b is connected. The connection point is connected to the other output terminal 15b, and the other output terminal 15b is grounded via the capacitive load 16b.

  Since the differential output circuit composed of the CML circuit of FIG. 4 can obtain a differential logic output signal with a small amplitude, the noise radiation from the signal line is small, and the current when driving the capacitive loads 16a and 16b is the power supply. In addition, there is no significant noise on the ground.

  However, in the differential output circuit as shown in FIG. 4, a constant current corresponding to the value obtained by dividing the amplitude voltage of the logic output signal by the resistance value of the load resistors 11a and 11b must be kept flowing, resulting in large current consumption. There is an inconvenience.

  For example, even when the switching of the differential switch is infinitely fast when the amplitude of the logic output signal is 500 mV, the output transition is caused by the integration time constant formed by the load resistors 11a and 11b, for example, 3.3 KΩ and the capacitive loads 16a, 16b, for example, 2 pF Is limited.

  For example, in order to swing a 25 MHz logic output signal up to 500 mV amplitude, the integration time constant needs to be 6.7 nS or less, which is 1/3 of a half cycle of 20 nS, which makes the load resistances 11 a and 11 b less than 3.3 KΩ. Therefore, in order to obtain the amplitude of the logic output signal of 500 mV, the constant current of the constant current circuit 13 needs to be 150 μA or more.

  Therefore, in Patent Documents 1 and 2, a high-level signal having a voltage lower than the power supply voltage and a low-level signal having a voltage higher than the ground level are formed by a regulator circuit, and the regulator circuit for the high-level signal and the regulator for the low-level signal A switch in which a complementary open / close switch is provided between a circuit and an output terminal to obtain a logic output signal at the output terminal is described.

According to the techniques described in Patent Document 1 and Patent Document 2, a logic output signal having a small amplitude can be obtained, so that a large radiation noise can be prevented and a differential output circuit composed of the above-described CML circuit is used. Since a large current that constantly flows is not necessary, power consumption is small.
Japanese Patent No. 3142416 JP 2000-68813 A

  However, since the regulator circuit used in the techniques described in Patent Document 1 and Patent Document 2 is a source follower circuit or a source-grounded amplifier circuit that feeds back the drain voltage to the gate, its output impedance is small, and the capacitance The pulsating current that drives the capacitive load flows through these regulator circuits via a switch and flows into the power supply and ground.

  Therefore, the techniques described in Patent Document 1 and Patent Document 2 also have a disadvantage that noise generated in the power supply and ground is as large as that of the CMOS inverter type logic output circuit of FIG.

  In view of the above, an object of the present invention is to reduce radiation noise, power supply, and ground noise and to reduce power consumption.

  The differential output circuit of the present invention divides a potential between a power supply potential and a ground potential to form first and second potential points that obtain first and second potentials, and are connected in series. And a third resistor, a smoothing capacitor connected between the first and second potential points, a first potential point having a higher potential of the first and second potential points, and a first output terminal And a second switch inserted between the first output terminal and the second potential point having a lower potential among the first and second potential points. A third switch inserted between the second potential point and the second output terminal, and a fourth switch inserted between the first potential point and the second output terminal. The first and second switches and the third and fourth switches are complementarily opened and closed, and the first and second outputs. Is obtained so as to obtain a logic output signal that transitions to the opposite polarity at the same time to the terminal.

  According to the present invention, the first and second potentials are obtained by dividing the potential between the power supply potential and the ground potential by the first, second, and third resistors, and the first and second potentials are obtained. Since the logic output signal is a high level signal and a low level signal and the output signal is obtained differentially, the logic output signal can be a differential small amplitude signal, and radiation noise from the output signal line can be reduced. Can be very small.

  According to the present invention, since the smoothing capacitor is provided between the first and second potentials, the first and second potentials are stable, and the resistances of the first, second, and third resistors are stable. Since the value can be made relatively large, the current flowing through the series circuit of the first, second and third resistors is reduced, and the power consumption can be reduced.

  Further, in the present invention, the drive current at the rising transition flows through the smoothing capacitor and hardly passes through the power source / ground, so that the power source / ground noise becomes extremely small.

  An example of the best mode for carrying out the differential output circuit of the present invention will be described below with reference to FIG.

  In FIG. 1, reference numeral 20 denotes a power supply terminal to which a power supply voltage of 2.5 V, for example, is supplied. The resistance values of the resistors 21, 22 and 23 are relatively high, for example, 10 KΩ.

  In this example, a high level signal (first potential) H of the logic output signal is obtained at the connection point 24 of the resistors 21 and 22, and the low level signal of the logic output signal is obtained at the connection point 25 of the resistors 22 and 23. (Second potential) L is obtained.

  In this example, the connection point 24 is connected to the connection point 25 via a relatively large capacity, for example, a smoothing capacity (bypass capacity) 26 of 5 pF.

  In this example, the connection point 24 from which the high level signal H is obtained is connected to the drain of the n-type MOS transistor 27 constituting the switch, and the source of the MOS transistor 27 is connected to one output terminal 28. One output terminal 28 is grounded via a capacitive load 29.

  Further, the connection point 25 from which the low level signal L is obtained is connected to the drain of the n-type MOS transistor 30 constituting the switch, and the source of the MOS transistor 30 is connected to one output terminal 28. In this case, the MOS transistors 27 and 30 are driven complementarily by the data supplied to the data input terminals 31 and 32 and the inverted data.

  The connection point 25 from which the low level signal L is obtained is connected to the drain of the n-type MOS transistor 33 constituting the switch, the source of the MOS transistor 33 is connected to the other output terminal 34, and the other output terminal is connected. 34 is grounded via a capacitive load 35.

  Further, the connection point 24 from which the high level signal H is obtained is connected to the drain of the n-type MOS transistor 36 constituting the switch, and the source of the MOS transistor 36 is connected to the other output terminal 34. In this case, the MOS transistors 33 and 36 are driven in a complementary manner by the data supplied to the data input terminals 31 and 32 and the inverted data.

  In order to obtain the high level signal H and the low level signal L of the logic output signal of the differential output circuit shown in FIG. 1, the MOS transistors 27, 30, 33 and 36 and the capacitive loads 29 and 35 constituting the switch are switched capacitors. Calculated as the resistance of the configuration.

Here, when the frequency of the data is f and the capacitance value of the capacitive loads 29 and 35 is CL, the resistance Rsc of the switched capacitor configuration is as follows.
Rsc = 1 / f × 2 × CL

When the power supply voltage is VDD and the resistance values of the resistors 21, 22 and 23 are R1, R2 and R3, the average values of the high level signal H and the low level signal L are determined by the following voltage division formulas. The resistor 22 is connected in parallel with the switched capacitor resistor Rsc.
VDD: H: L = (R1 + R2 // Rsc + R3): (R2 // Rsc + R3): R3
When the capacitance value of the smoothing capacitor 26 is sufficiently increased, the high level signal H and the low level signal L are substantially constant values determined by this partial pressure expression.

  Therefore, according to the present example, differential logic output signals having small amplitudes of the high level signal H and the low level signal L are obtained at the one and other output terminals 28 and 34, respectively.

  As a specific example, the power supply voltage is 2.5 V, the capacitance values of the capacitive loads 29 and 35 are 2 pF, the data frequency is 25 MHz, and the amplitude of the high level signal H and the low level signal L is 500 mV. I will explain the case.

In this case, the switched capacitor resistor Rsc is Rsc = 1 / (25 × 10 6 × 4 × 10 -12) = 10 6/100 = 10KΩ
It is.
Considering the case where the signal to be transmitted is not a continuous clock but an NRZ signal, the resistance value R2 of the resistor 22 in parallel with the switched capacitor resistor Rsc is set to this resistor in order to avoid a large fluctuation in output level due to the signal pattern. It is set to 10 KΩ equivalent to the resistance value of Rsc, and R2 // Rsc is set to 5 KΩ.

  In order to set the amplitudes of the high level signal H and the low level signal L to 500 mV which is 1/5 of the power supply voltage 2.5V, the resistance values R1 and R3 of the resistors 21 and 23 may be set to 10 KΩ. In this case, the larger the smoothing capacity 26 is, the better, but it may be about 5 times the capacity value of the capacitive loads 29 and 35.

In this specific example, the current consumption is 2.5 V / (10 KΩ + 5 KΩ + 10 KΩ) = 100 μA
Thus, the constant current is smaller than 150 μA in FIG.

  Further, the drive current when charging the capacitive load 29 and discharging the capacitive load 35 at the rising transition of the differential output circuit is as shown by an arrow a. Smoothing capacitor 26 → MOS transistor 27 → one output terminal 28 → capacitive load 29 → ground → capacitive load 35 → the other output terminal 34 → MOS transistor 33 → smoothing capacitor 26, and the same applies when the capacitive load 35 is charged and the capacitive load 29 is discharged. Yes, the power supply / ground noise is extremely small because it hardly passes through the power supply / ground.

  According to this example, the first and second potentials H and L are obtained by dividing the potential between the power supply voltage and the ground potential by the first, second, and third resistors 21, 22, and 23, Since the first and second potentials H and L are set to the high level signal H and the low level signal L of the logic output signal and the output signal is obtained differentially, the logic output signal is changed to the differential small amplitude signal. The radiation noise from the output signal line can be made very small.

  In addition, according to the present example, since the smoothing capacitor 26 is provided between the first and second potentials H and L, the first and second potentials H and L are stable. Since the resistance values R1, R2 and R3 of the third resistors 21, 22 and 23 can be made relatively large, the current flowing through the series circuit of the first, second and third resistors 21, 22 and 23 is reduced. , Power consumption can be reduced.

Further, in this example, since the drive current at the rising transition flows through the smoothing capacitor 26 and hardly passes the power source / ground, the power source / ground noise becomes extremely small.
Further, since the bias of this example is generated by a simple circuit composed of passive elements, there is no risk of causing abnormal oscillation or instability, and it is easy to manufacture because only the resistance ratio needs to be accurate.

  FIG. 2 shows another example of the best mode for carrying out the present invention. In the description of FIG. 2, the same reference numerals are given to the portions corresponding to FIG.

  In the example of FIG. 2, the resistor 22 of FIG. 1 is configured by a variable resistor 37, and the automatic resistance control circuit 38 detects the voltage difference between the high level signal H and the low level signal L. The control is performed so as to be 500 mV. The rest of the configuration is the same as in FIG.

  2, when the input data is toggled at the maximum frequency, it is assumed that the minimum switched capacitor resistance Rsc is 10 KΩ, and the voltage difference between the high level signal H and the low level signal L at this time. That is, in order to make the logical amplitude 500 mV, the resistance values of the resistors 21 and 23 are set to 20 KΩ. The state variable resistor 37 is adjusted so that the resistance value becomes infinite. In this case, the resistance value of the variable resistor 37 can be varied from 10 KΩ to ∞.

  When the data is at or near the static state, the resistance value of the switched capacitor resistor Rsc approaches infinity. In this case, if the resistance value of the variable resistor 37 is adjusted to 10 KΩ, the amplitude of the logic output signal can be maintained at 500 mV. it can.

  If the parallel resistance value of the switched capacitor resistor Rsc and the resistance value R4 of the variable resistor 37 is adjusted to 10 KΩ between the static state and the maximum frequency toggle state, the high level signal H and the low level signal L The amplitude, ie the amplitude of the logic output signal, can be kept at 500 mV.

  In this example, the automatic resistance control circuit 38 detects the voltage difference between the high level signal H and the low level signal L, and for example, the drain is connected to the connection point 24 and the source is connected to the connection point 25 so that the voltage difference is maintained at 500 mV. An output signal corresponding to the difference of the automatic resistance control circuit 38 is supplied to the base of the connected MOS transistor.

  In the example of FIG. 2, it can be easily understood that the same effect as that of the example of FIG. 1 can be obtained.

  In the above-described example, an example in which the switch is configured by using a MOS transistor has been described, but it is needless to say that the switch may be configured by other switch elements.

  Further, the present invention is not limited to the above-described examples, and various other configurations can be adopted without departing from the gist of the present invention.

It is a block diagram which shows the example of the best form for implementing this invention differential output circuit. It is a block diagram which shows the other example of the best form for implementing this invention. It is a block diagram which shows the example of the conventional logic output circuit. It is a block diagram which shows the example of the conventional differential output circuit.

Explanation of symbols

  20... Power supply terminal 21, 22, 23... Resistor 26... Smoothing capacity 27, 30, 33, 36 MOS transistor 28 28 One output terminal 29 35 Capacitive load 31, 32 ... Data input terminal

Claims (3)

First, second and third resistors connected in series to divide the potential between the power supply potential and the ground potential to form first and second potential points for obtaining the first and second potentials;
A smoothing capacitor connected between the first and second potential points;
A first switch inserted between a first potential point of a higher potential of the first and second potential points and a first output terminal;
A second switch inserted between a second potential point having a lower potential of the first and second potential points and the first output terminal;
A third switch inserted between the second potential point and a second output terminal;
A fourth switch inserted between the first potential point and the second output terminal, and the first and second switches are complementary to the third and fourth switches, respectively. The differential output circuit is characterized in that a logic output signal that opens and closes at the same time and transitions to the opposite polarity at the first and second output terminals simultaneously is obtained. The differential output circuit according to claim 1,
The differential output circuit characterized in that the second resistor is composed of a variable resistor, and the potential difference between the first and second potential points is controlled. The differential output circuit according to claim 1,
The differential is characterized in that the second resistor is constituted by a variable resistor, and the variable resistor is controlled by an automatic resistance control circuit so that the potential difference between the first and second potential points is constant. Output circuit.

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