JP2005322993A - Doherty type amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Doherty type amplifier with a higher efficiency the matching ratio of which is selected lower. <P>SOLUTION: The Doherty type amplifier includes: a carrier signal amplifier section for amplifying an input signal; a peak signal amplifier section for amplifying only a peak component of the input signal; a first output matching circuit located at a post-stage of the carrier signal amplifier section; a first impedance conversion section located at a post-stage of the first output matching circuit and whose impedance is Z1; a second output matching circuit located at the post-stage of the carrier signal amplifier section; and a composite section for composing the signal amplified by the carrier signal amplifier section with the signal amplified by the peak signal amplifier section and whose impedance is Z2, and is characterized in that a relation of Z1<Z0 holds in the case of Z2<Z0/2, wherein Z0 is a load impedance, a relation of Z1<Z0/2 holds in the case of Z2<Z0/4, and a relation of Z1<Z0/4 holds in the case of Z2<Z0/8. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an amplifier for a base station apparatus, a relay amplification apparatus, and the like provided in a wireless communication system such as a mobile communication system, and more particularly to a Doherty amplifier that improves the efficiency of the apparatus.

  Here, as the wireless communication system, for example, various systems such as a mobile phone system, a simple mobile phone system (PHS: Personal Handy Phone System), and a data communication system using those infrastructures may be used.

As communication methods, for example, various methods such as a CDMA (Code Division Multiple Access) method, a W (Wide Band) -CDMA method, a TDMA (Time Division Multiple Access) method, and an FDMA (Frequency Division Multiple Access) method are available. May be used.

  Here, the configuration of the amplification device and the like according to the present invention is not necessarily limited to the above-described configuration, and various configurations may be used.

  The application field of the present invention is not necessarily limited to the above-described fields, and the present invention can be applied to various fields.

In recent years, in the field of wireless communication, downsizing of devices has been demanded as represented by mobile terminals such as mobile phones, but the same applies to base stations and the like. High efficiency is required. Further, in base stations, miniaturization of high frequency amplifiers installed in the vicinity is required in order to reduce cable loss between antennas.

In general, the power efficiency of a high-frequency power amplifier using a semiconductor element increases as the output increases, and the efficiency is highest near the saturated output. Further, the level of saturation output depends on the size of the semiconductor element to be used. For this reason, if an amplifier with a low saturation output level is made using a small semiconductor element in order to improve the efficiency at the time of low output, the output required at the time of high output cannot be obtained. Conversely, if a large semiconductor element is used to make an amplifier that is highly efficient at high output, the efficiency will be reduced at low output.

As described above, it is very difficult to construct an amplifier having a high output level and higher efficiency. However, a Doherty amplifier has been developed that compensates for the two conditions of high output level and high efficiency. The Doherty amplifier is described in Patent Document 1, for example.
Japanese Patent No. 127944 (page 2-3, Fig. 1)

A basic configuration of the Doherty amplifier will be described with reference to FIG. In FIG. 1, 1 is an input terminal, 2 is a distributor, 3 is a phase converter that shifts the phase by 90 degrees, 4 is a Doherty combiner, 5 is a λ / 4 impedance converter, 6 is an output, and 7 is an output load. . The output load 7 is basically fixed.

10 is an input matching circuit, 11 is an amplifying element called a carrier amplifier in the Doherty amplifier, 12 is an output matching circuit, 20 is an input matching circuit, 21 is an amplifying element called a peak amplifier in the Doherty amplifier, and 22 is an output matching circuit. is there.
Further, 41 provided in the Doherty synthesis unit 4 is a λ / 4 impedance conversion unit, and 42 is a synthesis point.

Next, the operation will be described.
The high frequency signal input to the input terminal 1 is distributed by the distributor 2. One is input to the amplifying element 11 through the input matching circuit 10, amplified, output to the output matching circuit 12, and further converted by the λ / 4 impedance converter 41.
The other distributed high-frequency signal is input to the phase conversion unit 3 and shifted in phase by 90 degrees, input to the amplification element 21 through the input matching circuit 20, amplified, and output to the output matching circuit 22.

The signal that has passed through the input matching circuit 10 → the amplifying element 11 → the output matching circuit 12 → the λ / 4 impedance converter 41 and the signal that has passed through the phase converter 3 → the input matching circuit 20 → the amplifying element 21 → the output matching circuit 22 are It is synthesized at the synthesis point 42 of the Doherty synthesis unit 4.
The impedance Z1 of the λ / 4 impedance converter 41 of the Doherty combiner is set to 1/2 of the impedance Z0 of the load resistor 7 of the output 6.

The amplifying element 11 is biased to class A or class AB, performs an amplifying operation regardless of the input level of the input signal, and outputs an output signal. On the other hand, the amplifying element 21 is biased to class B or class C, and does not operate when the instantaneous input is small. The DC power consumption of the amplifying element 21 is 0 or sufficiently small, and the efficiency as an amplifier is high. . On the other hand, when the instantaneous input power is sufficiently large, the amplifying element 21 enters an operating state, amplifies the input signal to the amplifying element 21 and generates an output signal. Here, by combining the output power of the amplifying element 11 and the output power of the amplifying element 21, an amplifier having a large saturation power is formed as a result. However, the Doherty amplifier is not simply obtained as a circuit combining an amplifier biased to class A or class AB and an amplifier biased to class B or class C, but is provided on the output side of the amplifying element 11. By further changing the apparent load impedance of the amplifying element 11 based on the function of the λ / 4 impedance conversion unit 41, higher efficiency is realized.

The state of this efficiency is theoretically as shown in FIG. In FIG. 2, the horizontal axis back-off indicates that the input level at which both the amplifying element 11 and the amplifying element 21 are saturated is 0 dB, and the numerical value on the horizontal axis indicates a value when the input is lowered. b indicates the efficiency when the general B class operation is performed, and a indicates the efficiency of the Doherty amplifier.
In a, in the area A, only the amplifying element 11 which is a carrier amplifier is operating.
The state of B which is a transition region is a state where the amplifying element 21 which is a peak amplifier is operating in addition to the carrier amplifier. Region C is in a state in which the maximum output is output for both the carrier amplifier and the peak amplifier.

で表される。 The area A will be described as shown in FIG. As can be seen, only the route of the amplifying element 11 which is a carrier amplifier operates. Therefore, the final load of the carrier amplifier is Z0 / 2. Here, the impedance Z2 when the load 7 is viewed from the λ / 4 impedance converter 5 is expressed by Equation 1:

It is represented by

Further, since the maximum output is output in both areas C, the output side circuit is as shown in FIG. However, Z2 is separated into two for easy consideration. Therefore, the final loads of the amplifying element 11 as the carrier amplifier and the amplifying element 21 as the peak amplifier are Z0.

となる。 The transition region B is as shown in FIG. The final load of each amplifier is Z0 / 2 to Z0 for the amplifying element 11, and ∞ to Z0 for the amplifying element 21. More specifically, the impedance viewed from the output matching circuit 12 of the amplifying element 11 is expressed by Equation 2:

It becomes.

As described above, the Doherty amplifier is theoretically efficient. However, in reality, when the output is increased, there is a problem that the output and efficiency as designed cannot be obtained.
Common high-frequency elements are often single-ended. This is because the impedance of the amplifying element is as high as several Ω and it is easy to obtain matching with the load impedance Z0. However, the high output type in which the amplifying element is large is about 0, several Ω, and the impedance ratio is high, and matching with the load impedance Z0 cannot be easily achieved.

Therefore, the high-power amplifying element is generally forced to be a push-pull transistor. When an attempt is made to supply the load Z0 with a push-pull transistor, the load of each amplifying element is Z0 / 2, and the impedance ratio is halved compared to the single-ended type.

The impedance of the Doherty amplifier as seen from the load impedance output matching circuit 12 in the area A in FIG. 2 is 2Z0, which is twice that of the normal single-ended type, and four times that of the push-pull type. Yes. In general CDMA signals and multicarrier signals, the peak factor (peak power / average power) is around 10 dB, and the efficiency around back-off 10 dB in FIG. 2 is extremely important. Therefore, the load impedance of the carrier amplifier of the Doherty amplifier is very high, and it is difficult to obtain matching. In particular, the back-off is about 10 dB in the A region, and therefore the efficiency of the carrier amplifier is very important for the efficiency of the Doherty amplifier.

The present invention has been made to solve the above-described problems, and makes it easy to achieve output matching for both peak and carrier by reducing the load impedance of the carrier amplifier and the peak amplifier.

  In order to solve the above problems, a carrier signal amplification unit that amplifies an input signal, a peak signal amplification unit that amplifies only a peak component of the input signal, and a first stage provided after the carrier signal amplification unit An output matching circuit; a first impedance converter having an impedance value Z1 provided at a stage subsequent to the first output matching circuit; a second output matching circuit provided at a stage subsequent to the peak signal amplifier; The signal amplified by the carrier signal amplifying unit and the peak signal amplifying unit is combined and composed of a combining unit whose impedance value is Z2, and when the load impedance is Z0 and Z2 <Z0 / 2, Z1 <Z0. A Doherty-type amplifier is provided.

  A carrier signal amplifying unit for amplifying the input signal; a peak signal amplifying unit for amplifying only a peak component of the input signal; a first output matching circuit provided at a subsequent stage of the carrier signal amplifying unit; A first impedance converter having an impedance value Z1 provided at the subsequent stage of the output matching circuit, a second output matching circuit provided at the subsequent stage of the peak signal amplifier, the carrier signal amplifier, and the peak signal amplifier A Doherty-type amplifier comprising a combining unit that synthesizes signals amplified by the unit and having an impedance value of Z2, and Z1 <Z0 / 2 when the load impedance is Z0 and Z2 <Z0 / 4. provide.

  A carrier signal amplification unit that amplifies the input signal; a peak signal amplification unit that amplifies only the peak component of the input signal; a first output matching circuit that is provided after the carrier signal amplification unit; A first impedance converter having an impedance value Z1 provided at the subsequent stage of the output matching circuit, a second output matching circuit provided at the subsequent stage of the peak signal amplifier, the carrier signal amplifier, and the peak signal amplifier Provided is a Doherty amplifier characterized in that the signal amplified by the unit is combined and the impedance value is Z2, and when the load impedance is Z0 and Z2 <Z0 / 8, Z1 <Z0 / 4 .

According to the present invention, it is possible to reduce the impedance of the Doherty combining unit, thereby reducing the load impedances of the carrier and the peak, facilitating output matching, and improving the performance. Furthermore, since the width of the strip line employed in the Doherty combining unit and the impedance converting unit can be increased, the loss is reduced. Further, if the strip line width is made the same as the conventional one, the thickness of the printed board becomes thin, and the printed board having a high material becomes inexpensive.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3, 4, and 5. 4 and 5, the same reference numerals as those in FIG. 3 have the same configuration, and the description thereof is omitted.

A first embodiment of the present invention will be described with reference to FIG.
The area A in FIG. 2A, that is, the state where only the amplifying element 11 which is a carrier amplifier is operating will be described as shown in FIG. FIG. 3B is a diagram of the region C. Reference numeral 411 denotes a λ / 4 impedance converter of the Doherty synthesizer 4 provided at the subsequent stage of the amplifying element 11 which is a carrier amplifier.

As can be seen from FIG. 3A, only the route of the amplifying element 11 which is a carrier amplifier operates in the region A. A typical CDMA signal or multicarrier signal has a peak factor (peak power / average power) of about 10 dB, and therefore, the efficiency of about 10 dB back-off in FIG. 2 is extremely important. The back-off region around 10 dB is the region A, and the efficiency of the amplifying element 11 that is a carrier amplifier is important.

Here, the impedance of the output matching circuit of the amplifying element 11 which is a carrier amplifier is set to 2Z0 or less. At this time, the impedance Z1 of the λ / 4 impedance converter 411 can be set to Z1 <Z0, and Z2 is set to Z0 / 2 or less.

Thus, by lowering the impedance of the Doherty combining unit, output matching can be easily achieved and performance can be improved.

A first embodiment of the present invention will be described with reference to FIG.
The area A in FIG. 2A, that is, the state where only the amplifying element 11 that is a carrier amplifier is operating will be described as shown in FIG. 4A. FIG. 4B is a diagram of the region C. Reference numeral 412 denotes a λ / 4 impedance converter of the Doherty synthesizer 4 provided at the subsequent stage of the amplifying element 11 which is a carrier amplifier.

As can be seen from FIG. 4A, in the region A, only the route of the amplifying element 11 that is a carrier amplifier operates. A typical CDMA signal or multicarrier signal has a peak factor (peak power / average power) of about 10 dB, and therefore, the efficiency of about 10 dB back-off in FIG. 2 is extremely important. The back-off region around 10 dB is the region A, and the efficiency of the amplifying element 11 that is a carrier amplifier is important.

Here, the impedance of the output matching circuit of the amplifying element 11 which is a carrier amplifier is set to be 2Z0 or less to Z0 or less in the conventional A region. At this time, the impedance Z1 of the λ / 4 impedance conversion unit 412 can be set to ½ or less of the normal value, and Z2 is set to Z0 / 4 or less. At this time, as can be seen from Equation 1, the impedance Z3 of the λ / 4 impedance conversion unit 5 is Z0 / 4 or less, so that the normal value Z0 / √ (2) is Z0 / 2 or less. More specifically, if the impedance Z2 at the synthesis point is Z0 / 4, Z1 becomes Z0 / 2, and the load impedance of the output matching circuit 12 decreases from Z0 (A region) to Z0 / 2 (C region). When Z2 is smaller than Z0 / 4, the other impedances are reduced proportionally.

Thus, by lowering the impedance of the Doherty combining unit, output matching can be easily achieved and performance can be improved.

A second embodiment of the present invention will be described with reference to FIG.
2A, that is, a state where only the amplifying element 11 that is a carrier amplifier is operating, a state shown in FIG. 5A is obtained. FIG. 5B is a diagram of the region C. Reference numeral 413 denotes a λ / 4 impedance converter of the Doherty combiner provided at the subsequent stage of the amplifier element 11 which is a carrier amplifier.

As can be seen from FIG. 5A, only the route of the amplifying element 11 as a carrier amplifier operates in the region A. In general CDMA signals and multicarrier signals, the peak factor (peak power / average power) is around 10 dB, and therefore the efficiency around 10 dB back-off in FIG. 2 is extremely important. The back-off is about 10 dB in the A region, and the efficiency of the amplifying element 11 that is a carrier amplifier is important.

Here, the impedance of the output matching circuit of the amplifying element 11 which is a carrier amplifier is set to 2Z0 to Z0 / 2 or less in the conventional A region. At this time, the impedance Z1 of the λ / 4 impedance converter 413 is changed from the normal value Z0 to Z0 / 4 or less, and Z2 is set to Z0 / 8. At this time, since the impedance Z3 of the λ / 4 impedance converter 5 is Z0 / 8 or less as can be seen from the equation 1, the normal value Z0 / √ (2) to Z0 / 2√ (2) or less. become. More specifically, if the impedance Z2 at the composite point is Z0 / 8, Z1 becomes Z0 / 4, and the load impedance of the output matching circuit 12 changes from Z0 / 2 (A region) to Z0 / 4 (C region). Go down. When Z2 is smaller than Z0 / 8, the other impedances are reduced proportionally.

Thus, by lowering the impedance of the Doherty combining unit, output matching can be easily achieved and performance can be improved.

With the configuration as described above, the load of the peak amplifier 21 is more fluctuating than the conventional load, but it is easy to obtain matching in the C region.

With this configuration, the impedance of the Doherty combining unit 4 is lowered and the conversion ratio of the λ / 4 impedance converting unit 5 is increased. However, since the impedance ratio from the output impedance of the amplifying element to the Doherty combining unit is small, there is a problem here. No.
Here, as a circuit of the λ / 4 impedance converter 5, a method of converting without increasing Q can be considered, but there are many existing techniques. Further, the amplification element is mounted on a printed circuit board and supplies power to the load 7 of the output 6 while combining Doherty, but the load line conversion λ / 4 line of the Doherty combining unit 4 is changed from the conventional 50Ω to 12.5Ω, When the impedance of the Doherty combining unit is 6.25Ω, the λ / 4 line of the λ / 4 impedance converting unit is changed from 35Ω to 17Ω, the line becomes thicker and the loss reduction is small. If the width of the stripline is made the same as before, the substrate thickness can be reduced, and a Doherty amplifier can be produced economically and inexpensively. There is a further advantage by lowering the impedance of this Doherty combining section.

In the above description, the impedance Z2 at the Doherty combining point is described as being equal to or lower than Z0 / 4. However, the present invention is not limited to this.

Basic drawing of Doherty amplifier. The figure showing the efficiency of a Doherty type amplifier. FIG. 6 is an operation explanatory diagram of the Doherty amplifier according to the present invention. FIG. 6 is an operation explanatory diagram of the Doherty amplifier according to the present invention. FIG. 6 is an operation explanatory diagram of the Doherty amplifier according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Input 2 ... Divider 3 ... Phase conversion part 4 ... Doherty synthesis part 411, 412, 413, 5 ... (lambda) / 4 impedance conversion part 6 ... Output 7 ... Load 11, 21 ... Amplifying element 10, 20 ... Input matching circuit ,
12, 22 ... Output matching circuit 42 ... Composite point

Claims (3)

A carrier signal amplification unit that amplifies the input signal, a peak signal amplification unit that amplifies only the peak component of the input signal, a first output matching circuit provided at a subsequent stage of the carrier signal amplification unit, and the first output matching A first impedance converter having an impedance value Z1 provided at the subsequent stage of the circuit, a second output matching circuit provided at the subsequent stage of the peak signal amplifier, the carrier signal amplifier, and the peak signal amplifier. A Doherty type that combines amplified signals and is composed of a combining unit having an impedance value of Z2 and a load resistor having a load impedance of Z0, and Z1 <Z0 when Z2 <Z0 / 2. amplifier. A carrier signal amplification unit that amplifies the input signal, a peak signal amplification unit that amplifies only the peak component of the input signal, a first output matching circuit provided at a subsequent stage of the carrier signal amplification unit, and the first output matching A first impedance converter having an impedance value Z1 provided at the subsequent stage of the circuit, a second output matching circuit provided at the subsequent stage of the peak signal amplifier, the carrier signal amplifier, and the peak signal amplifier. A Doherty that combines amplified signals and is composed of a combining unit having an impedance value of Z2 and a load resistance having a load impedance of Z0, and Z1 ≦ Z0 / 2 when Z2 ≦ Z0 / 4. Type amplifier. A carrier signal amplification unit that amplifies the input signal, a peak signal amplification unit that amplifies only the peak component of the input signal, a first output matching circuit provided at a subsequent stage of the carrier signal amplification unit, and the first output matching A first impedance converter having an impedance value Z1 provided at the subsequent stage of the circuit, a second output matching circuit provided at the subsequent stage of the peak signal amplifier, the carrier signal amplifier, and the peak signal amplifier. The amplified signal is composed of a combining unit having an impedance value of Z2 and a load resistor having a load impedance of Z0. When Z2 ≦ Z0 / 8, Z1 ≦ Z0 / 4 is satisfied. Type amplifier.

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