JP2009213090A - Power amplification circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power amplification circuit increasing the band of a frequency characteristic, increasing the efficiency of output power, and reducing the size of the circuit, without using a matching circuit. <P>SOLUTION: The power amplification circuit 1 includes: a LINC signal separation circuit 10; FETs 11 and 12; a parasitic device component 13; a jBs device which is an inductive device; a -jBs device which is a capacitive device; transmission line paths 14 and 16 having a predetermined electrical length L1 and a predetermined characteristic impedance Z1, where an electrical length from the FETs 11 and 12 to a synthesis point 18 is set to be λ/4 or less, taking the parasitic device component 13 into consideration; and the synthesis point 18. A lossless synthesizer having the transmission line path characteristics Z1 and L1 is designed by a design procedure of a Chireix synthesizer, and thereafter, a susceptance device is selected based on a designed output characteristic required by the power amplification circuit. The susceptance device is added to the lossless synthesizer to obtain a Chireix synthesizer 5. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  More particularly, the present invention relates to a high power power amplifier circuit for amplifying a high frequency signal.

  A base station wireless device that amplifies high-frequency power requires a high output, and therefore requires a highly efficient linear amplifier circuit. As one of means for realizing a high-efficiency linear amplifier circuit, a linear amplifier circuit using a saturation amplifier by a LINC (Linear Amplification with Nonlinear Components) system is known.

  FIG. 10 shows a conventional power amplifier circuit 100, which is a LINC type power amplifier circuit including a LINC signal separation circuit 10 and a lossless combiner 101. The power amplifier circuit 100 in FIG. 10 includes a LINC signal separation circuit 10, FETs 11 and 12, and transmission lines 23 and 24. Here, the FETs 11 and 12 of the actual devices have a drain-source C component (Cds) and a wire L component (Lw) which are parasitic element components 13. For this reason, matching circuits 31 and 32 for compensating for the parasitic element component 13 are provided in the actual device. Further, since the matching circuits 31 and 32 are provided, the electrical length from the FET to the synthesis point 18 needs to be an odd length multiple of λ / 4 (3λ / 4 or more). , 24 is provided with a necessary electrical length.

  When the modulation signal Sin accompanied by the envelope variation is input to the power amplifier circuit 100 of FIG. 10, first, the LINC signal separation circuit 10 decomposes into two constant envelope phase modulation signals S1, S2. Next, the decomposed S1 signal is input to the gate of the FET 11, and similarly, the S2 signal is input to the gate of the FET 12, and amplified by the saturation operation of the FETs 11 and 12, respectively. The amplified S1 signal and S2 signal are synthesized at the synthesis point 18 from the drain end via the transmission lines 23 and 24, and the synthesized signal is output from Sout.

  FIG. 12 is a LINC signal vector diagram showing the relationship of Sout in which the amplitude varies depending on the phase relationship between the S1 signal and the S2 signal output from the LINC signal separation circuit 10. When the S1 signal and the S2 signal, which are the output signals of the FETs 11 and 12, are in phase, all power is output as Sout, but when the phases are different, power is output to the Sout output side and the transmission line side. Will be distributed.

  Here, since the signal e shown in FIG. 12 is out of phase, the impedance is 0 at the synthesis point 18, and the impedance is infinite at the drain end of the FET that is separated from the synthesis point 18 by an electrical length of 3λ / 4. Power consumption becomes zero. However, the impedance at this time does not become infinite as a pure resistance, but has an admittance component according to the magnitude of the signal e. For this reason, there is a problem that the power consumption does not become “0” and the efficiency is lowered. Therefore, Non-Patent Document 1 discloses a technique that cancels this admittance component and makes it appear as a pure resistance component.

  In order to solve the above problem, the power amplifying circuit 200 of FIG. 11 includes a jBs element that is an inductive element and a capacitive element after the FETs 11 and 12 that respectively input the signals separated by the LINC signal separation circuit 10. There is a Chirex synthesizer 201 to which a certain -jBs element is added.

  Patent Document 1 discloses a class F amplifier as another circuit configuration for increasing the efficiency of the amplifier. The class F amplifier has an output matching circuit that is short-circuited to the even-order high-frequency signal and open to the odd-order high-frequency signal at the output end of the amplifying FET, etc. All the generated power is converted into high frequency power of the fundamental wave.

JP-A-11-112252 FREDERICK H. RAAB, “Efficiency of RF Power-Amplifier Systems”, IEEE TRANSACTIONS ON COMMUNICATIONS. VOL. COM-33, NO, 10 OCTOBER 1985. 1094-1099

  FIG. 13 is a diagram showing the load impedance viewed from the FET side on the Smith chart in the lossless combiner and the Chirex combiner. In the lossless synthesizer of FIG. 13A, the load impedance has a susceptance component when α is between 0 ° and 90 °, and the efficiency deteriorates, but when α is 90 °, the load impedance seen from each FET. Becomes open, and the power consumption of the FET becomes “0”.

  In the Chailex synthesizer shown in FIG. 13B, + jBs, −jBs cancels the susceptance component, and the susceptance component becomes “0” (a portion overlapping the real axis) at α determined by Bs. It becomes efficiency.

  However, since the power amplifier circuits 100 and 200 described above handle parasitic element components and in-phase and anti-phase signals, the matching circuit from the FET to the synthesis point 18 is an odd multiple of λ / 4 or more (3λ / 4). The electrical length is required. As the distance from the FET to the synthesis point 18 increases, the output power efficiency decreases and the frequency characteristic band is narrowed.

  In order to solve such problems, the power amplifier circuit according to the present invention is a power amplifier circuit that can realize a wide frequency characteristic, improved output power efficiency, and further downsizing the circuit without using a matching circuit. The purpose is to provide.

  In order to achieve the above object, a power amplifier circuit according to the present invention includes a distributor for separating the amplitude of a high-frequency signal input from an input terminal into two signals having a constant phase difference, and a distributor. An amplifier that amplifies the two signals separated by the combiner, a power combiner that transmits the signal amplified by the amplifier through the two transmission lines, and combines them at the combining point, and an output terminal that outputs the combined signal The power combiner is a lossless combiner having a transmission line having a first characteristic impedance and a first electrical length as a matching circuit that compensates for parasitic element components of the amplifier and the transmission line. When the two signals separated by the distributor are in phase, the distance from the amplifier to the synthesis point is λ / 4 with respect to the fundamental wave of the high frequency signal, and when the two signals separated by the distributor are in reverse phase, The second characteristic impedance and the second electrical length calculated under the condition that the distance from the amplifier is λ / 2 with respect to the fundamental wave of the high-frequency signal, and the power combiner It is a chirex synthesizer in which a susceptance element having a predetermined output efficiency characteristic is added to a lossless synthesizer having a characteristic impedance of 2 and a second electrical length.

  Further, in the power amplifier circuit according to the present invention, the power combiner has a second characteristic impedance and a second electrical length, and is lossless for combining at a distance of λ / 4 with respect to the fundamental wave of the high frequency signal from the amplifier. The synthesizer is a chirex synthesizer in which the position of the synthesis point is shifted by an offset length corresponding to a susceptance element that has a predetermined output efficiency characteristic.

  By using the power amplifier circuit according to the present invention, there is an effect that it is possible to broaden the frequency characteristics, improve the output power efficiency, and further reduce the size of the circuit without using a matching circuit.

  Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings.

ここで、誘導性素子であるｊＢｓ素子は、例えば、３λ／８オープンスタブであり、容量性素子である−ｊＢｓ素子は、例えば、λ／８オープンスタブ等で構成されている。 (First embodiment)
FIG. 1 shows a configuration of a power amplifier circuit 1 according to the first embodiment. The power amplifier circuit 1 considers the LINC signal separation circuit 10, the FETs 11 and 12, the parasitic element component 13, the jBs element that is an inductive element, the -jBs element that is a capacitive element, and the parasitic element component 13. The transmission lines 14 and 16 having a predetermined electrical length L1 and characteristic impedance Z1 at which the electrical length from the FETs 11 and 12 to the synthesis point 18 is λ / 4 or less, and the synthesis point 18 are provided.

Here, the jBs element that is an inductive element is, for example, a 3λ / 8 open stub, and the −jBs element that is a capacitive element is, for example, a λ / 8 open stub.

  The characteristic feature of the present invention is that the design required for the power amplifier circuit after designing the lossless synthesizer 6 having the characteristics of the transmission lines 14 and 16 (Z1, L1) by the design procedure of the CHIEX synthesizer described later. The chirex synthesizer 5 is designed by selecting a susceptance element according to the above output characteristics and adding a susceptance element to the lossless synthesizer.

  FIG. 2 shows the flow of the design procedure of the chirex synthesizer which is one of the features of the present invention. Hereinafter, the flow of the design procedure will be described with reference to FIGS. The design procedure is as follows: (1) The lossless combiner 6 is designed (step S10). (2) Z1 and L1 by in-phase and reverse phase are calculated (step S12). (3) The value of the susceptance element is selected based on the efficiency characteristics so as to maximize the efficiency at a desired output level (step S14).

  FIG. 3 shows the configuration of the power amplifier circuit 2 having the lossless combiner 6 that is the source of the Chirex combiner according to the first embodiment. In order for the lossless combiner 6 to operate, in the case of an in-phase signal where α = 0 degrees, the distance from the FET to the synthesis point (output terminal) is λ / 4, and in the case of a reverse-phase signal where α = 90 degrees. It is necessary to satisfy the condition of λ / 2 between the two FETs. Therefore, an equivalent Chirex synthesizer considered as a lossless synthesizer is shown.

  FIG. 4 shows an equivalent chirex synthesizer in the same phase, and FIG. 5 shows an equivalent chirex synthesizer in the reverse phase. Here, an equivalent chirex synthesizer in which the sum of the electrical lengths E1 and E2 of the actual device is λ / 4 at the same phase shown in FIG. 4 is examined, and the electrical length of the actual device at the opposite phase shown in FIG. Consider an equivalent Chirex synthesizer where the sum of E1, E2, E2, and E1 is λ / 2, and calculate Z1, L1. Since the jBs element and the −jBs element shown in FIGS. 4 and 5 are assumed to be negligibly small elements, this circuit can be regarded as a lossless combiner.

  First, when the FET to the output terminal in FIG. 4 are represented on the left side: real device and the right side: equivalent circuit by the F matrix, Equation 1 is established.

  Similarly, when the FET on one side to the FET on the other side in FIG. 5 is represented by an F matrix with the left side: an actual device and the right side: an equivalent circuit, Expression 2 is established.

  From Equation 1 and Equation 2,

となる。この行列式を展開すると、式４，式５，式６，式７が得られる。

It becomes. When this determinant is expanded, Equation 4, Equation 5, Equation 6, and Equation 7 are obtained.

  From the above equations 4, 5, and 6, Z1 and L1 become equations 8 and 9.

  With the above processing, Z1 and L1 based on in-phase and anti-phase in step S12 in FIG. 2 are calculated. Next, in step S14 of FIG. 2, the value of the susceptance element is selected for the lossless combiner obtained by the above processing.

  FIG. 6 shows efficiency characteristics with respect to output power, FIG. 6 (A) shows the efficiency of output power when Bs is changed, and FIG. 6 (B) shows the efficiency of output power when Bs is changed with respect to α. The characteristics are shown. For example, in a power amplifying circuit with a saturation output power of 50 dBm, linearity that is about 10 dB lower than the saturation output power (backoff = 0 dB) is usually used at a good and efficient output level. That is, the backoff is the difference between the average output level and the output saturation power level.

  When it is desired to maximize the efficiency when the back-off is reduced by, for example, 14 dB due to the design requirement of the power amplifier circuit, Bs = 0.03 is selected from FIG. Therefore, by setting the Bs obtained for the jBs element and the −jBs element of the chirex synthesizer 5 of FIG. 1, it is possible to omit the matching circuit that has been conventionally required. As a result, the electrical length can be shortened, and the frequency characteristics can be widened and the circuit can be miniaturized.

(Second Embodiment)
FIG. 7 shows the configuration of the power amplifier circuit according to the second embodiment, FIG. 8 shows another example of the equivalent chirex synthesizer 5 in the same phase, and FIG. 9 shows the equivalent chief in the opposite phase. 3 shows another example of a Rex synthesizer. In addition, description is abbreviate | omitted regarding the structure same as 1st Embodiment.

  As shown in FIGS. 8 and 9, the characteristic of this embodiment is that the position of the synthesis point is shifted by the offset length (Eoff) corresponding to Bs of the jBs element and the −jBs element used in the first embodiment. Thus, Bs is omitted and further miniaturization is achieved.

  In FIG. 7, the difference from the first embodiment is that Bs is omitted and the electrical lengths of the transmission lines 21 and 22 are shifted by the offset length. In this case, α = 75 degrees corresponding to Bs = 0.03 is selected based on the efficiency when α in FIG. 6B is changed, and transmission is performed so that the offset length (90−75 = 15 degrees) is obtained. This can be realized by setting Eoff in the lines 21 and 22.

  As described above, by using the power amplifier circuit according to the present embodiment, it is possible to widen the frequency characteristics, improve the output power efficiency, and further reduce the size of the circuit without using a matching circuit.

  The power amplifier circuit according to the present embodiment is used for a power amplifier circuit for a base station of a 2-3 GHz band, W-CDMA mobile phone, but is not limited to this application, and other mobile phones, Needless to say, it can be used as a power amplifying circuit for various communication devices such as commercial radio and broadcasting equipment.

It is a block diagram which shows the structure of the power amplifier circuit which concerns on the 1st Embodiment of this invention. It is a flowchart figure which shows the flow of the design procedure of the chirex synthesizer which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the power amplifier circuit used as the origin of the chirex synthesizer which concerns on the 1st Embodiment of this invention. It is explanatory drawing explaining the equivalent chirex synthesizer at the time of an in-phase. It is explanatory drawing explaining the equivalent chilex synthesizer at the time of reverse phase. It is a characteristic view which shows the characteristic of the efficiency with respect to output power. It is a block diagram which shows the structure of the power amplifier circuit which concerns on the 2nd Embodiment of this invention. It is explanatory drawing explaining another example of the equivalent chirex synthesizer in the same phase. It is explanatory drawing explaining another example of the equivalent chirex synthesizer at the time of reverse phase. It is a block diagram which shows the structure of the conventional power amplifier circuit. It is a block diagram which shows the structure of another example of the conventional power amplifier circuit. It is explanatory drawing explaining a LINC signal vector diagram. It is explanatory drawing explaining the load impedance seen from FET side.

Explanation of symbols

  1, 2, 100, 200 Power amplifier circuit, 5,201 Chirex synthesizer, 6,101 Lossless synthesizer, 10 LINC signal separation circuit, 11, 12 FET, 13 Parasitic element component, 14, 16, 21, 22, 22 23, 24 Transmission line, 18 Composite point, 31, 32 Matching circuit.

Claims (2)

A divider that separates the amplitude of the high-frequency signal input from the input terminal into two signals having a constant phase difference, an amplifier that amplifies each of the two signals separated by the divider, and an amplifier that is amplified In a power amplifier circuit having a power combiner that transmits a signal through two transmission lines and combines at a combining point, and an output terminal that outputs the combined signal,
The power combiner
A lossless combiner having a transmission line of a first characteristic impedance and a first electrical length as a matching circuit that compensates for parasitic element components of the amplifier and the transmission line;
When the two signals separated by the distributor are in phase, the distance from the amplifier to the synthesis point is λ / 4 with respect to the fundamental wave of the high frequency signal,
When the two signals separated by the distributor are in reverse phase, the distance between the two amplifiers is λ / 2 with respect to the fundamental wave of the high frequency signal,
A second characteristic impedance and a second electrical length calculated under the following conditions:
Further, the power combiner is a chirex combiner in which a susceptance element that has a predetermined output efficiency characteristic is added to a lossless combiner having a second characteristic impedance and a second electrical length. A power amplifier circuit. The power amplifier circuit according to claim 1,
The power combiner is a lossless combiner having a second characteristic impedance and a second electrical length and combining the fundamental wave of the high frequency signal from the amplifier at a distance of λ / 4, and has a predetermined output efficiency characteristic. A power amplifying circuit, wherein the power amplifier circuit is a Chirex synthesizer in which the position of the synthesis point is shifted by an offset length corresponding to a susceptance element.

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