JP4700470B2 - amplifier - Google Patents

Description

The present invention relates to an amplifier, and more particularly to an amplifier having improved power supply efficiency using a Doherty amplifier.

Conventionally, when amplifying power of code-multiplexed or frequency-multiplexed radio frequency signals such as CDMA signals and multi-carrier signals, a common amplifier with distortion compensation means is used to extend the operating range of the common amplifier to the vicinity of the saturation region. In order to reduce power consumption. As distortion compensation means, there are feedforward distortion compensation and predistortion distortion compensation. However, the distortion compensation alone is approaching the limit of low power consumption. Therefore, in recent years, Doherty amplifiers have attracted attention as high-efficiency amplifiers.

FIG. 1 is a configuration diagram of a conventional Doherty amplifier 1.
A signal input from the input terminal is distributed by the distributor 2.
One of the distributed signals is input to the carrier amplifier circuit 4. The carrier amplifier circuit 4 includes an input matching circuit 41 that matches the input side of the amplifying element 42, an amplifying element 42, and an output matching circuit 43 that matches the output side of the amplifying element 42. The output of the carrier amplifier circuit 4 is impedance-converted by a transmission line (λ / 4 transformer) 61.
The other of the distributed signals is delayed in phase by 90 degrees by the phase shifter 3 and input to the peak amplifier circuit 5. Like the carrier amplifier circuit 4, the peak amplifier circuit 5 includes an input matching circuit 51, an amplifier element 52, and an output matching circuit 53.
The outputs of the transmission line 61 and the peak amplifier circuit 5 are combined at a node (combining point) 62. The synthesized signal is impedance-converted by the λ / 4 transformer 7 in order to match the output load Z ₀ . The transmission line 61 and the node 62 are collectively referred to as a Doherty combining unit 6.
The output of the λ / 4 transformer 7 is connected to the output load 8 via the output terminal.

The carrier amplifying circuit 4 and the peak amplifying circuit 5 are different in that the amplifying element 42 is biased to class AB and the amplifying element 52 is biased to class B or C. Therefore, the amplifying element 42 operates alone until the input at which the amplifying element 52 operates, and when the amplifying element 42 enters the saturation region, that is, when the linearity of the amplifying element 42 starts to break down, the amplifying element 52 starts to operate and amplifies. The output of the element 52 is supplied to the load and drives the load together with the amplifying element 42. At this time, the load line of the amplification output matching circuit 43 moves from a high resistance to a low resistance as will be described later. However, since the amplification element 42 is in the saturation region, the efficiency is good.
As the input from the input terminal further increases, the amplifying element 52 begins to saturate, but since both the amplifying elements 42 and 52 are saturated, the efficiency is also good at this time.

FIG. 2 is a diagram illustrating theoretical collector efficiency or drain efficiency of the Doherty amplifier of FIG. The collector efficiency here means the ratio of the radio frequency output power that can be extracted from the collector to the product of the voltage (DC) of the power source applied to the collector and the current (DC) supplied from the power source. The same applies to efficiency.
The horizontal axis of FIG. 2 is the back-off, and shows the input level to the input terminal where both of the amplifying elements 42 and 52 are saturated, that is, the compression point is 0 dB, and the input level has a margin with respect to the compression point. It is a numerical value.

In FIG. 2, the dotted line shows the efficiency of a general class B amplifier, and the solid line shows the efficiency of the Doherty amplifier in a simple model.
When the input level is in the A section, only the carrier amplifier circuit 4 basically operates. The carrier amplifier circuit 4 starts to saturate near the backoff of 6 dB, and the efficiency reaches near the maximum efficiency of the class B amplifier. When the maximum output of Dohachii amplifier and at P _0, the output of the carrier amplifier 4 at this time is about P _0/4.
In the B section where the back-off is 6 dB or less, as the input level increases, the output of the carrier amplifier circuit 4 increases from about P _0/4 to P _0/2 , and the output of the peak amplifier circuit 5 increases from approximately 0 to P _0. Increase to / 2. At this time, the sum of the output power of the carrier amplifier circuit 4 and the peak amplifier circuit 5 is proportional to the input power to the input terminal with the same proportionality constant as in the A section. In other words, the carrier amplifier circuit 4 is designed so as to obtain good linearity as if the characteristics in the section A are extended as they are. When the peak amplifier circuit 5 starts to operate, the efficiency once decreases, but reaches a peak again at the compression point at which the peak amplifier circuit 5 also starts to saturate. At the compression point, the outputs of the carrier amplifier circuit 4 and the peak amplifier circuit 5 are equal.
In general, a CDMA signal and a multicarrier signal have a high peak factor, that is, a ratio of peak power to average power. However, in a normal amplifier, a point corresponding to 7 to 12 dB is reduced from the compression point. Is the normal operating point.

となる。ただし伝送線路６１は、一定の特性インピーダンスＺ₁を有し、線路長はλ／４とする。Ｂ区間において、Ｚ₄及びＺ₅は、Ａ区間の時の値とＣ区間の時の値との間をそれぞれ遷移する。 Returning to FIG. 1, the impedance of each part will be described. Since the output load Z ₀ is defined to be constant, this is the starting point. The impedance Z ₇ when the λ / 4 transformer ₇ is viewed from the node 62 is Z ₂ , where the characteristic impedance of the λ / 4 transformer 7 is Z ₂ .
Z ₇ = Z ₂ ² / Z ₀
It becomes.
The impedance Z _{4 when the} transmission line 61 is viewed from the output matching circuit 43 is obtained in the same manner as described above because the output impedance of the output matching circuit 53 is substantially infinite in the A section, and the load is equally shared in the C section. Therefore, the load impedance of the transmission line 61 (the contribution of the amplifier circuit 4 at the node 62) and the load impedance of the matching circuit 53 are 2Z ₇ respectively.

It becomes. However, the transmission line 61 has a constant characteristic impedance Z ₁ and the line length is λ / 4. In the B section, Z ₄ and Z ₅ transition between a value in the A section and a value in the C section, respectively.

When the Doherty amplifier is applied to a high frequency region, the following description may be easier to understand than the above description.
That is, Z ₄ is ½ times larger when the input signal level is large (C section) than the impedance value when the input signal level is small (S section A). In other words, Z ₄ is twice the load. Cause fluctuations. For example, if Z ₇ = 25Ω and Z ₁ = 50Ω, Z ₄ varies between 100 and 50Ω. Therefore, the load impedance of the amplifying element 42 also varies.

In addition to the above-described conventional Doherty amplifier, a Doherty amplifier that compensates for deterioration in characteristics by controlling the gate bias voltage according to the drain current for a carrier amplifier circuit is known (see, for example, Patent Document 1). .
In addition, there is known one in which each amplifier circuit constituting the Doherty amplifier is constituted by two or more stages (for example, see Patent Document 2).
In addition, an amplifier that synthesizes so as to cancel the harmonic components is known (see, for example, Patent Document 3).

JP 2004-260232 A JP 2004-173231 A Japanese Patent Publication No. 6-82998

However, in the conventional Doherty amplifier, if amplifiers are simply connected in multiple stages to form a common amplifier having a large gain, there is a problem that the distribution loss of the distributor 2 is large and the power supply efficiency (power supply additional efficiency) is not improved.
FIG. 3 is a configuration diagram of a common amplifier having a two-stage configuration. The signal amplified by the preamplifier 9 is equally divided into two by the distributor 2, which means 3 dB loss. That is, since the input impedance changes in a complicated manner depending on the input level, it cannot be expected that all the distributed power is used effectively. All power distributed to the peak amplifier circuit at least in the A section is wasted. That is, most of the power distributed to the peak amplifier is reflected, and the reflected wave is usually consumed by an isolator (not shown) or a dummy resistor (not shown) if the distributor 2 is a Wilkinson type. Also, part of the B section is reflected. However, as the input level increases, the output power of the B and C class amplifier circuits gradually increases and the reflected power also decreases. Therefore, Doherty synthesis maintains the gain in the A region (that is, maintains linearity). Can be done).
Therefore, it is necessary to expect a loss of about 3 dB in the distributor 2, and this is hereinafter referred to as a distribution loss of the distributor 2.

FIG. 4 is a graph for explaining the power sharing of the Doherty amplifier. A single input power-output power characteristic of the carrier amplifier circuit 4 corresponding to the case where there is no distribution loss of 3 dB is also described. The output of the peak amplifying circuit 5 suddenly rises from the vicinity of the back-off 6 dB, and the carrier amplifying circuit 4 and the peak amplifying circuit 5 share the load in the B section below the back-off 6 dB. Compared with the carrier amplifier circuit 4 alone, the output of the Doherty amplifier is greatly affected by a decrease in gain or the like due to distribution loss.

Hereinafter, a practical preamplifier 9 and Dohachii specifications of the amplifier 1 is assumed, it will be described with reference to FIG. 3 to calculate the added efficiency of common amplifier (Power Added Efficiency). The back-off of the common amplifier is a standard value (7 to 10 dB). Therefore, the operation is performed in the section A, and all the input power to the peak amplifier circuit 5 is reflected and consumed. The preamplifier 9 is a normal class AB amplifier that is not Doherty.
The specifications of the Dohachii amplifier 1 is as follows.
Output: 20W
Gain: 9dB (including distribution loss)
Collector efficiency: 35%
Input: 2.5W
The specifications of the pre-amplifier 9 is as follows.
Output: 2.5W (9dB lower than 20W)
Gain: 12dB
Collector efficiency: 20%
Input: 0.156W
Therefore,
Power consumption of Doherty amplifier: 20 / 0.35 = 57.1W
Preamplifier power consumption: 2.5 / 0.2 = 12.5W
Additional efficiency of common amplifier: (20-0.156) / (57.1 + 12.5) = 27.5%
Thus, even if the collector efficiency of the Doherty amplifier is improved to 35%, the overall efficiency as a common amplifier is reduced to 27.5%.

Alternatively, a method of cascade connection of a single Doherty amplifier is conceivable, but the Doherty amplifier has a phase shifter 3 and a Doherty synthesizer 6 and has a very large frequency characteristic. Absent.

  The present invention has been made from the above background, and an object thereof is to provide an amplifier having a large gain and an added efficiency comparable to the collector efficiency of the Doherty amplifier.

A distributor for distributing the input signal into at least two;
A first preamplifier and a second preamplifier for amplifying each of the distributed signals;
A carrier amplifier circuit for amplifying the output of the first preamplifier;
A peak amplification circuit for amplifying the output of the second preamplifier exceeding a threshold level;
An amplifier having the carrier amplifier circuit and a Doherty combiner for combining the outputs of the peak amplifier circuit.

A distributor that distributes the input signal approximately equally to the two;
A first preamplifier biased to class AB for amplifying one of the distributed signals;
A second preamplifier biased to class AB or class B or class C for amplifying the other of the distributed signals;
A carrier amplifier circuit biased to class AB and linearly amplifying the output of the first preamplifier at least for a level below a threshold;
A peak amplification circuit biased to class B or class C and amplifying the output of the second preamplifier at least for a level equal to or higher than the threshold;
An amplifier having the carrier amplifier circuit and a Doherty combiner for combining the outputs of the peak amplifier circuit.

Preferably, the threshold corresponds to a value about 6 dB less than the compression point of the amplifier,
The first and second preamplifiers have different output distortion amounts,
The peak amplifier circuit and the carrier amplifier circuit each have only one semiconductor device of the same type for power amplification, and have substantially equal saturation output levels,
The Doherty combining unit performs impedance conversion using a transmission line having an electrical length other than λ / 4.

A distributor for distributing the input signal into n parts;
A first preamplifier biased to class AB for amplifying one of the distributed signals;
Second to n preamplifiers biased to class AB or class B or class C for amplifying the other of the distributed signals;
A carrier amplifier circuit biased to class AB and linearly amplifying the output of the first preamplifier at least for a level below a threshold;
2 to n peak amplifier circuits that are biased to class B or class C and amplify the outputs of the second to n preamplifiers at least for a level equal to or higher than the threshold;
An amplifier comprising the carrier amplifier circuit and a Doherty synthesizer for synthesizing outputs of the 2 to n peak amplifier circuits.
Further, the second to n-th preamplifiers are configured in multiple stages, and at least the front end of the amplifiers constituting each stage is biased to class C.

According to the amplifier according to the present invention, when the amplifier is configured in a multistage configuration, the power supply efficiency of the entire amplifier can be brought close to the collector efficiency of the Doherty amplifier by distributing it while the level is small and suppressing the distribution loss.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The function realizing means described below may be any circuit or device as long as it can realize the function, and the function realizing means may be realized by a plurality of circuits. The function realization means may be realized by a single circuit. In addition, not all combinations of functions or configurations of the present embodiment are essential to the present invention.
Further, the present invention does not prevent the present invention from being implemented in combination with the description of the previous patent application by the same applicant as the present application cited in the specification.

FIG. 5 is a configuration diagram of the common amplifier according to the first embodiment. Common amplifier of FIG. 5 is conventional and varies in that separately provided a preamplifier after the distributor 2, the constituent elements same reference numerals have been assigned, in order to facilitate the performance comparison between the conventional, including specifications It is completely the same as FIG.
Reference numeral 1 ′ denotes a Doherty amplifier (final stage part), which corresponds to the remaining part of the conventional Doherty amplifier except for the distributor 2 and the phase shifter 3.
Reference numeral 2 denotes a distributor that distributes the signal input to the input terminal. The distributor 2 is, for example, a Wilkinson distributor formed on a wiring board.
Reference numeral 3 denotes a phase shifter, which generates a delay (phase) corresponding to the transmission line 61 in principle. The phase shifter 3 absorbs a delay time difference (phase difference) between the preamplifier 91 and the carrier amplifier circuit 4 and the preamplifier 92 and the peak amplifier circuit 5 in order to perform the synthesis in the same phase. It may be different from the delay (phase). The phase shifter 3 may be one that can electrically vary the amount of delay (phase shift).
A preamplifier 91 amplifies and outputs one of the distributed input signals. The preamplifier 91 is biased at class AB and satisfies the linearity required as an input of the carrier amplifier circuit 4. The back-off of the preamplifier 91 is designed to be approximately the same as or slightly larger than that of the carrier amplifier circuit 4, for example.
A preamplifier 92 amplifies and outputs the other of the distributed input signals. The preamplifier 92 is biased at class C and satisfies the linearity required as an input of the peak amplifier circuit 5. For this reason, the outputs of the preamplifiers 91 and 92 are not necessarily the same.
Reference numeral 4 denotes a carrier amplifier circuit that amplifies the signal amplified by the preamplifier 91.
Reference numeral 5 denotes a peak amplifier circuit that amplifies the signal amplified by the preamplifier 92. Amplifying elements used in the preamplifiers 91 and 92, the carrier amplifier circuit 4, and the peak amplifier circuit 5 are usually semiconductor devices such as LD-MOS (Lateral Double-diffused MOS), GaAs-FET, HEMT, and HBT. The amplifying elements used in the carrier amplifying circuit 4 and the peak amplifying circuit 5 may be devices having substantially the same specifications.
Reference numeral 61 denotes a transmission line for performing impedance conversion. Although generally constructed as a λ / 4 transformer, it is not constrained to it and has an electrical length (effective line length) of length l = 0 to λ / 2 or more, and its characteristic impedance Z1 may be 2Z7 = 2Z22 / Z0. The design method relating to this is the same as that described in Japanese Patent Application No. 2004-320992. However, in this embodiment, a λ / 4 transformer is used as usual for performance comparison.
Reference numeral 62 denotes a node (combining point) that combines the outputs of the carrier amplifier circuit 4 and the peak amplifier circuit 5 via the transmission line 61.
Reference numeral 7 denotes a λ / 4 transformer for converting the impedance Z7 viewed from the node 62 into an output load Z0. The λ / 4 transformer 7 may be formed on the wiring board as a conductor pattern having a line width corresponding to the characteristic impedance Z2 and a length corresponding to λ / 4. Matching can be achieved in a relatively wide frequency range by using the λ / 4 transformer, but matching means other than the λ / 4 transformer may be used as long as matching is achieved.

Next, the additional efficiency of the common amplifier of FIG. 5 is evaluated. The characteristics of each circuit are the same as in FIG. 3 of the related art. As a common amplifier, if the input level is the same, the same output can be obtained with the same back-off. For comparison, the input / output level as a common amplifier is The same. However, the preamplifier 91 has a class AB and the preamplifier 92 has a class C structure, and the efficiency and gain are the same as the conventional one, but the output level is lower than the conventional one.
The specifications of Dohachii amplifier (output stage unit) 1 'is as follows.
Output: 20W
Gain: 12dB (increased by 3dB because the distributor is removed)
Collector efficiency: 35%
The specifications of the preamplifier 91 is as follows.
Output: 1.25W
Gain: 12dB
Collector efficiency: 20%
Input: 0.078W

The preamplifier 92 does not perform an amplification operation and consumes no power when using a 7-10 dB back-off. The matching between the preamplifier 91 and the carrier amplifier circuit 4 is good, and there is almost no loss. In addition, it should be noted that the wasteful power distributed to the route of the peak amplifier circuit 5 in the section A is reduced from the conventional 1.25 W to 0.078 W.
Therefore,
Power consumption of Doherty amplifier: 20 / 0.35 = 57.1W
Power consumption of preamplifiers 91 and 92: 1.25 / 0.2 = 6.25W
Additional efficiency of common amplifier: (20-0.156) / (57.1 + 6.25) = 31.3%
Thus, the power supply efficiency is improved by 2.8% compared to the conventional FIG.

In the common amplifier described above, the saturation outputs of the carrier amplifier circuit 4 and the peak amplifier circuit 5 are equal, but the present invention is not limited to this and may be different. Further, it is clear that the number of stages of subordinate connections is not limited to two, and if the number of stages is larger than that, the gain can be improved while maintaining the efficiency improvement effect. In that case, all the preamplifiers on the peak side may be class C, but only those closer to the input side may be class C.
Further, the adjustment of the gain and phase of the carrier amplifier circuit 4 and the peak amplifier circuit 5 is important for optimizing the load sharing and the performance of the Doherty amplifier, but such an adjustment circuit (an electronic circuit using a PIN diode or a variable capacitance diode is used). If it is provided in the preamplifier in the preceding stage (for example, the first preamplifier after distribution) as much as possible, the performance of the Doherty amplifier can be improved while suppressing loss in the adjustment circuit.
Further, the bias of each amplifier circuit constituting the common amplifier is not limited to a fixed one, and active bias control may be performed. That is, the present invention can be applied as long as any of the preamplifiers for the peak amplifier circuit 5 is C-class biased and is substantially in an OFF state at an arbitrary level (particularly in the A section).
The expressions A to C used in the above description simply represent the depth of the bias (the amount of idle current), and other operation classes (for example, F) depending on the configuration of the output matching circuit. It does not interfere with the application to the grade.

FIG. 6 is a configuration diagram of a common amplifier according to the second embodiment. The present embodiment is different from the first embodiment in that the Doherty amplifier is configured to synthesize the outputs of the three amplifier circuits. In addition, since the component which attached | subjected the code | symbol same as Example 1 is not different from that of Example 1, description is abbreviate | omitted.
Reference numeral 21 denotes a distributor which distributes the input signal into three.
31 is a phase shifter for synthesizing the outputs from the carrier amplifier circuit 4 and the peak amplifier circuit 5 and the output from the peak amplifier circuit 55 in the same phase.
Reference numeral 55 denotes a second peak amplifying circuit, which has substantially the same configuration as that of the peak amplifying circuit 5, but operates at an input level that is higher than the input level at which the peak amplifying circuit 5 starts to operate ( Bias) is set.
Reference numeral 63 denotes a node (combining point) that combines the output from the carrier amplifier circuit 4 and the peak amplifier circuit 5 and the output from the peak amplifier circuit 55 via the transmission line 64.
Reference numeral 64 denotes a transmission line, which may have a length that is almost directly connected, or may be designed in the same manner as the transmission line 61 for performing impedance conversion.
Reference numerals 91 to 93 denote second to fourth preamplifiers, respectively. By inserting preamplifiers 91, 92, 93 in front of each amplifier circuit 4, 5, 55, respectively, a 3-way Doherty amplifier in which a preamplifier is inserted before distribution of a peak circuit or a drive circuit as shown in FIG. Compared with, the absolute value of the distribution loss is reduced and the added efficiency is improved.

The operation of the common amplifier in FIG. 6 will be described. When the input level is such that the peak amplifier circuit 55 does not operate, the operation from the input terminal to the node 63 operates in the same manner as in FIG. 5, and the combined output of the carrier amplifier circuit 4 and the peak amplifier circuit 5 is obtained at the node 63. Further, the load impedance of the peak amplifier circuit 55 is almost infinite, and the transmission line 64 converts the impedance of the node 63 and transmits it to the node 62.
When the input level is large such that the peak amplifier circuit 55 operates, the impedance of the node 62 as viewed from the transmission line 64 increases, so that the impedance as viewed from the node 63 also increases and is supplied to the output load 8 via the transmission line 64. The generated power is further increased. Alternatively, the operation at the level before and after the peak amplifier circuit 55 starts operating may be similarly analogized by considering the combination of the carrier amplifier circuit 4 and the peak amplifier circuit 5 as the conventional carrier amplifier circuit 4.
In any case, it is only necessary to cause load modulation at the node 63 so as not to reduce at least the combined output of the carrier amplifier circuit 4 and the peak amplifier circuit 5 when the peak amplifier circuit 55 operates. Thereby, the carrier amplifier circuit 4 and the peak amplifier circuits 5 and 55 share the output of the common amplifier.

As described above, by providing the preamplifiers 91 to 93 in front of each amplification unit, the absolute value of the distribution loss when the peak amplification circuits 5 and 55 do not operate can be greatly reduced, and the added efficiency is increased. To do.
In the present embodiment, the Doherty synthesis unit 6 ′ composed of 61 to 64 is not limited to this configuration, and various configurations such as a method of combining with one node are conceivable. Further, the number of synthesis is not limited to three and may be more. Some of the plurality of preamplifiers may be combined into one and shared.

Configuration of conventional Doherty amplifier The figure which shows the theoretical collector efficiency thru | or drain efficiency which concerns on the Doherty amplifier of FIG. Configuration diagram of a two-stage common amplifier Figure Configuration of common amplifier according to an embodiment Configuration of Common Amplifier according to Embodiment 1

Explanation of symbols

1 Doherty amplifier 2 Divider 3 Phase shifter 4 Carrier amplifier circuit 5 Peak amplifier circuit 6 Doherty combiner 61 Transmission line 62 Node 7 λ / 4 transformer 8 Output load 9 Preamplifier

Claims (2)

A distributor that distributes the input signal approximately equally to the two;
A first preamplifier biased to class AB for amplifying one of the distributed signals;
A carrier amplifier circuit biased to class AB and amplifying the output of the first preamplifier;
A second preamplifier, which amplifies the other of the distributed signals, biased to class C so as to be turned off at an input signal level at which only the carrier amplifier circuit operates ;
A peak amplification circuit that is biased to class B or class C and amplifies a level equal to or higher than the threshold value of the output of the second preamplifier
An amplifier having the carrier amplifier circuit and a Doherty combiner for combining the outputs of the peak amplifier circuit. A distributor for distributing the input signal into n parts;
A first preamplifier biased to class AB for amplifying one of the distributed signals;
A carrier amplifier circuit biased to class AB and amplifying the output of the first preamplifier;
Second to nth preamplifiers that are biased to class C so as to be off at an input signal level at which only the carrier amplifier circuit operates, amplifying the other of the distributed signals;
2 to n peak amplifier circuits that are biased to class B or class C and amplify the outputs of the second to n-th preamplifiers having a level equal to or higher than a threshold;
An amplifier comprising the carrier amplifier circuit and a Doherty synthesizer for synthesizing outputs of the 2 to n peak amplifier circuits.

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