JP2005317949A - Contact hole formation method and manufacturing device of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide method and a device for forming contact holes of low resistance with proper productivity, even with respect to an insulating film on a thin active layer Si film of a number of irregularities. <P>SOLUTION: In the method for simultaneously forming the contact holes on a gate electrode on the Si active layer and via an insulating SiO<SB>2</SB>film, oxide films that are left in the irregularities of the Si active layer are removed effectively, by subsequently performing sputter etching by Ar gas with a sputtering device and continuously performing sputtering deposition after performing reactive ion etching by a fluorine gas system and wet etching by a buffered hydrofluoric acid. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method and an apparatus for forming a contact hole in an insulating film on amorphous Si as an active layer, particularly in a method for manufacturing a thin film element on a glass substrate.

  Thin film semiconductor elements using amorphous silicon typified by polysilicon and microcrystal silicon are widely used as large pixel displays, personal computers, mobile phones and the like as pixel drive elements of display devices. Among such thin film semiconductor elements, a thin film transistor made of polysilicon has a high mobility and is known to be useful as a switching element. Most of the thin-film transistor manufacturing methods using polysilicon follow the conventional Si semiconductor process, but the point is that a glass substrate is used and that laser annealing is used to polycrystallize the Si thin film. . For this reason, a problem peculiar to the thin film semiconductor process occurs, and one of them is a contact formation technique. In the contact formation, the contact hole is etched through an insulating film covering the thin film semiconductor serving as the active layer, and the upper layer wiring is buried therein to connect the thin film semiconductor and the upper layer wiring. As described above, since polysilicon is subjected to laser annealing, the surface is not flat and has an uneven structure corresponding to the intensity distribution of the laser. For this reason, the insulating film in the recesses often remains without being removed by etching, which causes an increase in contact resistance. In order to prevent this, conventionally, when the contact hole is formed, the uneven layer is completely etched by digging a part of the upper layer of the semiconductor layer. This will be specifically described with reference to FIG.

  First, as shown in (a), a Si oxide film 102 is formed on a glass substrate 101 to a thickness of about 300 nm, and an active layer Si film 103 is formed on the top of 102 to a thickness of 60 nm. Subsequently, the surface of the active layer Si film 103 is irradiated with an excimer laser and crystallized to form a polysilicon (poly-Si) film. Next, an interlayer insulating Si oxide film 104 is formed to a thickness of 50 nm, and a micro crystal silicon (μc-Si) film 105 and a Cr film 106 are formed in this order as gate wirings. Here, the film thickness of the micro crystal silicon (μc-Si) film 105 is 100 nm, and the film thickness of the Cr film 106 is 200 nm. Next, the micro crystal silicon (μc-Si) film 105 and the Cr film 106 are patterned by photolithography to form a gate electrode. Next, a 100 nm Si oxide film is formed on the top, and a heat treatment at 350 ° C. or higher is performed to lower the resistance of the polysilicon film.

  Subsequently, an Si oxide film is further formed to 300 nm, and a total of 400 nm is formed as the interlayer film 107. Therefore, the interlayer insulating film on the gate electrode is 400 nm,

  The film thickness on the active layer Si film 103 is 450 nm in which the interlayer insulating Si oxide film 104 and the interlayer film 107 are combined.

  Next, as shown in (b), contact openings are made on the Cr film 106 and the active layer Si film 103.

  Using the photoresist 108 as a mask, the Si oxide film is etched by reactive ion etching until the Cr film 106 and the active layer Si film 103 are reached, thereby opening a contact hole. Here, the thickness of the Si oxide film on the active layer Si film 103 is 450 nm, whereas the thickness of the Si oxide film on the Cr film 106 is 400 nm. Open.

Therefore, when the contact hole on the active layer Si film 103 is opened, the contact hole on the Cr film 106 is over-etched. However, if the CHF ₃ / O ₂ mixed gas 109 is used as the etching gas, the Cr film 106 is completely etched. Therefore, excessive digging due to etching over does not occur. A method for removing the Si oxide film using CHF ₃ + O ₂ as an etching gas in this way is described in Japanese Patent Application Laid-Open No. 2001-274411.

  The fluorocarbon-based etching residue 110 deposited on the active layer Si film 103 during etching is removed by wet etching using buffered hydrofluoric acid 111 as shown in FIG. Thus, a method using a hydrofluoric acid-based etchant for removing fluorocarbon-based etching residues on the active layer Si film is described in Japanese Patent Application Laid-Open No. 11-111988.

  Finally, after removing and removing the photoresist, the glass substrate 101 is moved into the sputtering apparatus, AlSi sputter film formation 112 is performed, and an AlSi film is formed as a drain wiring, as shown in FIG. The Cr / Al contact 113 and the Si active layer / Al contact 114 are embedded, and the Cr film 106 and the active layer Si film 103 are connected by the AlSi film.

  Here, the time from the wet etching process with BHF in (c) to the AlSi sputtering process in (d) needs to be one day or less that can prevent the formation of a surface-oxidized silicon. .

  This is because the time during which the Si surface is H-terminated by this etching and the formation of the natural oxide film is suppressed is at most about 24 hours.

JP 2001-274411 A Paragraph 0063 Japanese Patent Laid-Open No. 11-111988, paragraph 0012

  As described above, in the conventional contact hole formation process, two types of etching, ion etching and wet etching, are performed on the insulating film on the active layer Si film. However, the unevenness on the surface of the active layer Si film cannot be completely flattened only by these etchings. In particular, the Si oxide film remaining under the etching residue is extremely difficult to remove.

  Therefore, the contact resistance could not be controlled with good reproducibility. In particular, in the case of a fine contact pattern, this effect is significant, causing a contact failure. As a means for avoiding this, a method of setting the end point of dry etching at the upper part of the active layer Si layer is employed.

  This will be described with reference to FIG. 6 showing an enlarged contact hole portion on the active layer Si film. As shown in (a), the surface of the active layer Si film 103 exhibits an uneven structure with an elevation difference of about 20 nm after being irradiated with an excimer laser. In order to suppress the Si oxide film remaining in the recess, the end point in the dry etching shown in FIG. 5B is set to a depth at which the active layer Si layer 103 is partially over-etched. By etching to this depth, the height difference of the unevenness on the surface of the active layer Si layer 103 is reduced, and the residual Si oxide film 115 in the recess shown in FIG. It can be easily removed by etching.

  Finally, as shown in (d), after removing the photoresist 108, an AlSi sputtered film is formed, whereby the gate Cr / Al contact 113 and the Si active layer / Al contact 114 are connected.

  Here, the active layer Si layer 103 has a thickness of 60 nm, and impurity phosphorus (hereinafter abbreviated as P) is distributed at a depth of about 20 nm from the surface. However, when the depth becomes deeper than this, the P concentration rapidly decreases (FIG. 7). . Therefore, the region allowed to be removed by overetching is limited to a depth of about 20 nm from the surface. The precision of etching depth control in dry etching is 100 nm at most, and such fine control is quite difficult. Considering the variation in the etching rate every day and the change over time of the apparatus itself, it is necessary to optimize the etching time for each etching.

  That is, such process optimization is unavoidable for a decrease in throughput and an increase in manufacturing cost.

  An object of the present invention is to provide a method and an apparatus for forming a low-resistance contact hole with high productivity even for an insulating film on a thin active layer Si film with many irregularities.

  According to the present invention, the non-crystalline Si and the conductive film formed on the insulating film are formed on the insulating film covering the non-crystalline Si having an uneven surface shape formed on the insulating substrate. A method of forming a contact hole for connection, a step of etching the insulating film to a depth at which the unevenness is not lost by reactive ion etching, a step of removing a residue by the reactive ion etching by wet etching, There is provided a contact hole forming method characterized in that the step of sputter etching the amorphous Si surface is performed in this order.

  According to this method, since reactive ion etching is stopped at the surface of amorphous Si, there is no need for overetching, and strict etching depth control is not necessary. Deposits generated by the reactive ion etching generated in this reactive ion etching process can be removed by the subsequent wet etching, and the oxide film in the recess of the amorphous Si surface still remaining after these processes. Can be physically removed by sputter etching. Therefore, it is not necessary to remove the active layer Si film more than necessary in the reactive ion etching, and the etching end point detection control is reliable. Note that wet etching is not necessarily required when there is no deposit or when the amount is small.

  According to the present invention, the non-crystalline Si and the conductive film formed on the insulating film are formed on the insulating film covering the non-crystalline Si having an uneven surface shape formed on the insulating substrate. A method of forming a contact hole for connection, a step of etching the insulating film to a depth at which the unevenness is not lost by reactive ion etching, a step of removing a residue by the reactive ion etching by wet etching, There is provided a contact hole forming method characterized in that a step of sputter-etching the amorphous Si surface and a step of forming a metal film by sputtering are performed in this order.

  According to this method, after the surface of the amorphous Si is exposed by sputter etching, the metal thin film is subsequently formed by sputtering, so that contact formation productivity is improved.

  In the present invention, fluorine-based gas can be used in reactive ion etching.

  If this etching gas is used, the etching selectivity between the metal and Si can be increased, and there is no danger of eroding the metal surface during the etching of Si.

In the present invention, buffered hydrofluoric acid can be used in wet etching. By using buffered hydrofluoric acid, the etching selectivity between Si and SiO ₂ can be increased, and there is no risk of eroding the Si surface during the etching of SiO ₂ .

  In the present invention, after the completion of the sputter etching, the metal film is formed by transporting the substrate to a film formation chamber via a transport path maintained in a vacuum state or a state filled with an inert gas. A contact hole forming method according to claim 3 is provided.

  According to this method, the metal film can be formed in a state where no natural oxide film is formed on the amorphous Si surface, so that the contact resistance can be lowered.

  In the present invention, the amorphous Si and a conductive film formed on the insulating film are connected to an insulating film covering the amorphous Si having an uneven surface shape formed on the insulating substrate. A contact hole forming apparatus for forming a contact hole for forming a contact hole, wherein an etching chamber for performing sputter etching, a film forming chamber for forming a metal film, and a vacuum state or inactive from the etching chamber to the film forming chamber There is provided a contact forming apparatus having a transport mechanism for transporting the glass substrate in a state filled with gas.

  By using this apparatus, a metal film can be formed in a state where a natural oxide film is not formed on the amorphous Si surface, so that the contact resistance can be lowered.

  In the present invention, there is provided an amorphous Si element characterized in that the surface roughness of the amorphous Si surface is 10 nm or less at the contact portion between the wiring and the amorphous Si layer. Here, the surface roughness is the maximum value of the level difference of the surface irregularities.

  In this element, since the height difference of the unevenness on the Si surface is small and no oxide film remains at the interface, the resistance of the contact can be reduced.

  The present invention provides a liquid crystal display device having the amorphous Si element of claim 8 in a liquid crystal driving circuit.

  In the contact hole forming method and apparatus according to the present invention, a glass substrate can be used as the insulating substrate.

  According to the method of the present invention, the unevenness on the amorphous Si having many unevenness is physically flattened with high precision by sputter etching, so that a contact hole with good productivity and low resistance can be formed. Further, according to the manufacturing apparatus of the present invention, since the metal wiring is continuously formed in the contact hole after the unevenness is flattened, a contact can be formed on a clean surface.

  FIG. 1 is a process sectional view showing a manufacturing flow of a thin film transistor device as a first embodiment of the present invention. As shown in FIG. 1A, a Si oxide film 102 is formed on a glass substrate 101 to a thickness of about 300 nm, and an active layer Si film 103 as an active layer is formed thereon to a thickness of 60 nm. Into a polysilicon (poly-Si) film.

  Next, an interlayer insulating Si oxide film 104 is formed to a thickness of 50 nm as an interlayer insulating film, and a micro crystal silicon (μc-Si) film 105 and a Cr film 106 are formed to a thickness of 100 nm and 200 nm in this order as gate wiring materials, respectively. Then, the gate electrode is formed by patterning this into a desired shape. Thereafter, an interlayer Si oxide film is further formed to a thickness of 100 nm, and heat treatment is performed at a temperature of ° C or higher to activate the active layer Si film 103 to reduce the resistance.

  After the above process, an interlayer Si oxide film is further formed to a thickness of 300 nm, and a 400 nm Si oxide film is formed as the interlayer film 107. A contact opening to the interlayer film 107 will be described.

As shown in (b), using the photoresist 108 as a mask, using a CHF ₃ / O ₂ mixed gas as an etching gas, until reaching the surface of the Cr film 106 and the surface of the active layer Si film 103 by reactive ion etching, A contact is opened by etching the Si oxide film.

The condition at this time is
Etching pressure 2Pa,
RF power 1500W,
Etchant gas flow rate 150sccm,
And The etching time is a value obtained by dividing the interlayer film thickness by the average value of the etching rate measured every day under the same conditions.

In this case, since the average etching rate was 60 nm / min and the film thickness was 450 nm, it was set to 450 seconds. When the etching rate varies, the active layer Si layer 103 is not excessively shaved by calculating the etching time with the upper limit value.
After this reactive ion etching, as shown in an enlarged view in FIG. 3A, the surface of the active layer Si film 103 in the contact hole opening has a fluorocarbon (FC) etching residue generated by an etching gas. 110 remains. Therefore, in order to remove the etching residue 110, wet etching using buffered hydrofluoric acid 111 shown in FIG.

  The HF concentration of BHF was about 1%, and the etching time was 120 seconds. In the wet etching with BHF, the etching rate for etching the Si oxide film is extremely higher than the etching rate for the Si film, so that only the remaining Si oxide film can be removed without damaging the active layer Si film 103. . Ammonium fluoride or the like may be added to this BHF as a buffer solution. However, since the Si oxide film in the minute recesses is not completely removed, at this time, the surface of the active layer Si film 103 is covered with the residual Si oxide film 115 and exposed as shown in FIG. There is a part that is not.

  Next, after removing the photoresist 108, the glass substrate 101 is moved by a transfer line while being kept in vacuum in the etching chamber 201 of the AlSi sputtering apparatus shown in FIG. Here, as shown in FIG. 1D, the surface of the active layer Si film 103 is sputter-etched 100 to remove the uneven portions as shown in FIG. In sputter etching, the surface layer is physically scraped off by striking the surface with Ar molecules. Therefore, since the etching is performed at a constant rate almost without depending on the material, both the Si film and the residual Si oxide film are removed at the same time, and the unevenness can be removed. The conditions at this time are as follows.

Chamber pressure 1Pa
RF power 1000W
The etching rate of Si is about 20-30 nm / min. On the other hand, since the height of the convex portion is usually larger than 10 nm and may be up to 15 nm, the Si etching time for removing the residual Si oxide film in the concave portion is appropriately about 30 seconds.
Thereafter, the glass substrate is moved to the film forming sputtering chamber 202 in the same AlSi sputtering apparatus shown in FIG. 2 via a conveyance path held in vacuum, and as shown in FIG. Film 112 is performed.

The condition at this time is
Ar 0.3pa
DC power 20kW
And a film thickness of 500 nm was obtained by sputtering for 60 seconds. By such a process, the gate Cr / Al contact 113 and the Si active layer / Al contact 114 are connected.

  The AlSi sputtering apparatus used in this example will be described. In FIG. 2, the etching chamber 201 has a structure in which the RF electrode 204 is disposed on the substrate side, and an Ar radical 205 generated by Ar gas plasma discharge is physically collided with the substrate to physically form the underlying Si film on the substrate. 103 can be removed by etching with an accuracy of about 10 to 15 nm. On the other hand, the deposition sputtering chamber 202 for performing AlSi sputtering deposition has a structure in which the substrate 203 side is the ground electrode 206 and the DC bias electrode 208 is disposed on the counter electrode side on which the AlSi target 207 is placed. Thus, Ar radicals 205 generated by Ar gas plasma can be generated and sputtered onto an AlSi target, and sputtered Al and Si radicals 209 can be deposited on the substrate.

  By using the method and apparatus described here, in FIG. 1, a good Si active layer / Al contact 114 and gate Cr / Al contact 113 are formed without leaving a Si oxide film on the surface of the underlying Si film 103. Is done. FIG. 8 shows a cross-sectional TEM photograph of the contact portion not subjected to sputter etching and the contact portion subjected to sputter etching for 30 seconds.

  The unevenness on the surface of the lower Si layer 103 was flattened by sputter etching, and the height difference of the unevenness became 10 nm or less.

  The contact resistance was 10 kΩ / or less, and it was confirmed that the contact resistance was sufficiently small for driving as a display device.

  In this embodiment, a glass substrate is used, but a quartz substrate may be used. In the case of a quartz substrate, the price is high, but since it does not contain impurities, it is not necessary to form a thermal oxide film on the substrate, and amorphous silicon can be formed directly. Further, a sapphire substrate may be used instead of the glass substrate. A sapphire substrate is also expensive compared to a glass substrate, but is excellent in thermal conductivity, so it is suitable for use in an environment where temperature increases. A plastic substrate may also be used.

  Further, although polysilicon is used as the amorphous silicon, it is not limited to polysilicon, and microcrystal silicon may be used.

In this embodiment, CHF ₃ and O ₂ are used as an etchant gas in the reactive ion etching, but CCl ₄ may be used instead of CHF ₃ .

  In this embodiment, the Al—Si film is used here as the metal film, but the present invention is not limited to this material, and Cu, Al, Mo, Cr, and polysilicon can also be applied.

  In this embodiment, in the transfer from the etching chamber to the film forming chamber, the transfer path is held in a vacuum, but the transfer path may be filled with an inert gas such as Ar or He.

  In the case where there is no etching residue 110, wet etching with BHF is not necessarily required if the influence is negligibly small.

(Second Embodiment)
Next, as a second embodiment of the present invention, the depth of the contact hole is controlled by shortening the reactive ion etching time and lengthening the BHF wet etching with a high etching selectivity of the Si / Si oxide film. A method for further improving the accuracy of the method will be described. The embodiment is shown in FIG. Although this embodiment is mostly common to the first embodiment, the end point of the reactive ion etching is not the time when the active layer Si film 103 is exposed, but the time when the surface of the Cr film 106 is exposed. Is different. The insulating film on the Cr film 106 is 400 nm, which is 50 nm thinner than the insulating film on the active layer Si film 103. Therefore, when the etching end point is detected in the Cr film 106, an insulating film of 50 nm remains on the active layer Si film 103, and the Si active layer / Al contact 114 is not opened. In this case, the etching end point time can be predicted from the etching time calculated from the etching rate as in the first embodiment. In addition, since the visible light reflectance on the exposed Cr surface is greatly increased compared to the Cr surface covered with the Si oxide film, the etching end point time can also be predicted by observing the visible light reflectance on the Cr surface. Is possible.

  The reflectance can be observed with the naked eye, or a configuration in which a visible laser beam is irradiated on the Cr pattern for observation and the reflected light is received by a light receiver may be used. In detecting the end point, a Cr film dummy film may be provided on the substrate surface with an area sufficiently larger than the contact hole in order to increase accuracy, and the reflectance may be observed at this portion.

  Since BHF has an etching rate of 100 times or more as high as that of the Si oxide film as compared with the Si film, by switching to wet etching when the film thickness of 50 nm remains, the Si over-etching method of the first embodiment This is definitely avoided.

  Since wet etching with BHF is not as anisotropic as reactive ion etching, side etching occurs in long-time etching, which degrades the shape of the contact hole. There is no effect.

  In the first and second embodiments, the silicon oxide film is used as the insulating film or interlayer film covering the substrate, but a silicon nitride film may be used. Also in this case, reactive ion etching and liquid phase etching can be performed using a known method and an etchant, and a contact hole can be formed in the same manner.

(Third embodiment)
Next, as a third embodiment of the present invention, FIG. 9 shows a liquid crystal display device using a pixel driving element created by using the method of the present invention. A TFT matrix using polysilicon is arranged as a pixel driving element in the liquid crystal display portion 904 on the glass substrate 901, and the image signal is run by the horizontal driving circuit 903 and the vertical driving circuit 902 so that an image is displayed. Is displayed. With the contact hole formed by the method of the present invention, the TFT matrix and each TFT of the horizontal and vertical drive circuits are connected to the wiring, and good display characteristics can be obtained. The unevenness of the polysilicon surface at the bottom of the contact hole is 10 nm or less, and unlike the conventional structure where the unevenness is larger than 10 nm, no oxide film remains, so a low contact resistance can be realized.

It is process sectional drawing showing the manufacturing flow of the thin-film transistor formed by the thin-film transistor manufacturing method of this invention. It is the apparatus schematic of the AlSi sputtering apparatus used in the thin-film transistor manufacturing method of this invention. It is sectional drawing which expanded and showed the contact hole formation part of Si active layer part. It is process sectional drawing which shows the manufacturing process of the thin-film transistor formed by the thin-film transistor manufacturing method of this invention. It is process sectional drawing showing the manufacture flow of the thin-film transistor formed with the manufacturing method of the conventional thin-film transistor. It is process sectional drawing which showed contact formation of the Si active layer part in the conventional thin-film transistor manufacturing method. It is a figure which shows the impurity distribution in the active layer Si film | membrane in the thin-film transistor manufacturing method of this invention. It is a figure which shows the cross-sectional TEM image of the thin-film transistor to which this invention is applied. It is a schematic diagram showing the liquid crystal display device to which this invention is applied.

Explanation of symbols

100 Sputter Etching 101 Glass Substrate 102 Si Oxide Film 103 Active Layer Silicon Film 104 Interlayer Insulating Si Oxide Film 105 Micro Crystal Silicon Film 106 Cr Film 107 Interlayer Film 108 Photoresist 109 CHF ₃ / O ₂ Mixed Gas 110 Etch Residue 111 Buffer Dehydrofluoric acid 112 AlSi sputter deposition 113 Gate Cr / Al contact 114 Si active layer / Al contact 115 Residual Si oxide film 201 Etching chamber 202 Deposition sputter chamber 203 Substrate 204 RF electrode 205 Ar radical 206 Earth electrode 207 AlSi target 208 DC Bias electrode 209 Al, Si radical 901 Glass substrate 902 Vertical drive circuit 903 Horizontal drive circuit 904 Liquid crystal display unit

Claims (10)

A contact for connecting the amorphous Si and the conductive film formed on the insulating film to an insulating film covering the amorphous Si having an uneven surface shape formed on the insulating substrate. A method of forming a hole, the step of etching the insulating film to a depth at which the unevenness is not lost by reactive ion etching, the step of removing the residue by the reactive ion etching by wet etching, and the amorphous Si A method of forming a contact hole, comprising performing the step of sputter etching the surface in this order. A contact for connecting the amorphous Si and the conductive film formed on the insulating film to an insulating film covering the amorphous Si having an uneven surface shape formed on the insulating substrate. A method of forming a hole, wherein a step of etching the insulating film to a depth at which the unevenness is not lost by reactive ion etching and a step of sputter-etching the amorphous Si surface are performed in this order. A method for forming a contact hole. A contact for connecting the amorphous Si and the conductive film formed on the insulating film to an insulating film covering the amorphous Si having an uneven surface shape formed on the insulating substrate. A method of forming a hole, the step of etching the insulating film to a depth at which the unevenness is not lost by reactive ion etching, the step of removing the residue by the reactive ion etching by wet etching, and the amorphous Si A method of forming a contact hole, comprising performing a step of sputter-etching the surface and a step of forming a metal film by sputtering in this order. The contact hole forming method according to any one of claims 1 to 3, wherein a fluorine-based gas is used in the reactive ion etching. The contact hole forming method according to claim 1, wherein buffered hydrofluoric acid is used in the wet etching. After completion of the sputter etching, the metal film is formed by transferring the substrate to a film formation chamber via a transfer path maintained in a vacuum state or a state filled with an inert gas. The contact hole forming method according to claim 3. A contact hole for connecting the amorphous Si and a conductive film formed on the insulating film to an insulating film covering the amorphous Si having an uneven surface shape formed on the insulating substrate. An etching chamber for performing sputter etching, a film forming chamber for forming a metal film, and the film forming chamber filled with a vacuum state or an inert gas. A contact hole forming apparatus having a transport mechanism for transporting the glass substrate in a state where the glass substrate is in contact. A non-crystalline Si element characterized in that the surface roughness of the non-crystalline Si surface in contact with the metal wiring in the contact portion is 10 nm or less. A liquid crystal display device comprising the amorphous Si element according to claim 8 in a liquid crystal driving circuit. The contact hole forming method according to claim 1, wherein the insulating substrate is made of glass.

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