KR100603839B1 - method for fabricating the array substrate for liquid crystal display device - Google Patents

Abstract

The present invention relates to an array substrate for a liquid crystal display device. More specifically, the present invention relates to a liquid crystal display device, in order to form an inclined step caused by excessive undercut by wet etching during a thin film transistor fabrication process, which is a switching element of the array substrate. After the electrode is etched, part of the photoresist on the drain electrode is removed, followed by dry etching of the exposed drain electrode, thereby preventing the disconnection of the pixel electrode due to the step, thereby improving the manufacturing yield of the liquid crystal display device.

Description

Method for fabricating the array substrate for liquid crystal display device             

1 is a plan view showing some planes of a general array substrate for a liquid crystal display device;

2A through 2D are cross-sectional views of a conventional array substrate shown in a process sequence by cutting along II-II of FIG. 1;

3A to 3C are partial process cross-sectional views of the array substrate according to the present invention shown in the process sequence by cutting along II-II of FIG.

4A to 4E are process cross-sectional views illustrating an enlarged portion B of FIG. 3C according to a process sequence;

FIG. 5 is a cross-sectional view taken along line II-II of FIG. 1, showing an array substrate for a liquid crystal display device according to the present invention.

<Description of Signs of Major Parts of Drawings>

123: drain electrode 125: drain electrode contact hole

131: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an array substrate for a liquid crystal display device, and more particularly, to preventing open of a pixel electrode by a shoulder of a side of a drain electrode constituting a thin film transistor.

Generally, a liquid crystal display includes a lower substrate on which a switching device and an array line are formed, and an upper substrate on which a common electrode and a color filter are formed. The substrate is bonded to a predetermined gap, and the liquid crystal LC is filled in the gap between the two substrates.

The lower substrate on which the switching element is formed among the liquid crystal display devices manufactured in the above-described configuration is called an array substrate and is composed of a plurality of pixel regions.

The pixel region is defined by the intersection of the data wiring and the gate wiring, and a pixel electrode is formed in the pixel region.

The thin film transistor, which is a switching element, is positioned at the intersection of the gate wiring and the data wiring. The thin film transistor includes a gate electrode, a source electrode, a drain electrode, and an active layer. The gate electrode is connected to the gate wiring, and the source electrode is connected to the data wiring.

The components are formed by repeating a deposition process, a photolithography process, and an etching process several times.

In the etching process, the etching method and the etching solution are different according to the materials constituting each layer, and the conditions such as etching time must be adjusted.

In general, the etching process is largely divided into dry etching and wet etching according to the etching means.

In the wet etching, hydrofluoric acid (HF) or phosphoric acid (PH ₃ ) is mixed with a predetermined chemical, and the etching solution reacts with the layer to be etched to form a compound that is soluble in water. Isolated, for a material of SiO ₂ for example, by reaction with fluorine in hydrofluoric acid (HF) in the etching liquid when the SiO ₂ is melted in the etching liquid. The wet etching may be controlled by the temperature, the etching time, and the composition ratio of the etchant. In the wet etching method, etching is performed by dipping a substrate in an etching solution to simultaneously perform side etching along with planar etching. Therefore, the etching time should be finely adjusted so that excessive under cut does not occur on the side of the pattern.

In the dry etching, the gas injected into the chamber by the plasma discharge is separated into ions, radicals and electrons. At this time, collisions and interactions are caused by an applied electric field, and ions react with the thin film on the glass by electric fields and radicals by diffusion, which are etched simultaneously by physical collisions and chemical reactions. do.

For example, in case of SiO ₂ , which is an insulating material, CF ₄ is mainly used as an etching gas. The energy given to this gas causes the fluorine to react with SiO ₂ to generate a gas containing fluorine, silicon and oxygen, which is removed from the vessel by vacuum.

The dry etching does not occur under etching compared to the wet etching, but the specific dry etching method has no etching selectivity. For example, an ion beam milling method or a plasma method has a disadvantage in that the lower layer is continuously etched when the upper layer is removed by dry etching. Therefore, in the dry etching, the etching time, etc. should be finely controlled.

Among the materials constituting the thin film transistor array substrate, the material patterned by the wet etching is mainly a metal film forming a wiring and a transparent conductive metal forming a pixel electrode, and the dry etching is used for forming a fine pattern. It is mainly used to etch semiconductor films, insulating films and metal films. In detail, the wet etching is applied to the gate wiring, the source, and the drain electrode because the wet etching has an advantage of being applied only to the layer to be etched because the etching selectivity is very large depending on the material.

However, in the wet etching method, side etching of the patterned layer is performed at the same time, so that shoulders are generated by excessive under cut, and the shoulder is disconnected from the layer formed on top of the patterned layer. It causes the (open).

1 is a plan view showing a part of a general array substrate for a liquid crystal display device. As shown, the array substrate for the liquid crystal display device has a gate wiring 13 formed on the substrate 11, and is perpendicular to the gate wiring 13 with an insulating layer (not shown) interposed therebetween. The data wiring 15 is formed. An area defined by the intersection of the gate line 13 and the data line 15 is called a pixel area P, and a transparent pixel electrode 17 is formed in the pixel area.

A capacitor C having the gate wiring 13 as the first electrode is formed on the gate wiring 13. The capacitor may be formed using a part of the gate wiring or may be formed separately from the gate wiring 13.

In the former case, the use of a part of the gate wiring 13 as the capacitor C has the advantage of not needing to modify the manufacturing process or an extra process. However, when the gate wiring 13 is used as the capacitor C, the gate is used. The time constant of the wiring 13 is increased.

This problem can be solved by using aluminum (Al), which has a lower resistance than chromium (Cr) or tantalum (Ta), as a material of the gate wiring.

Meanwhile, a thin film transistor T is formed at an intersection point of the data line 16 and the gate line 13, and the thin film transistor includes a gate electrode 19 and the data line connected to the gate line 13. And a drain electrode 23 spaced apart from each other by a plane.

The gate electrode 19 includes an active layer 27 overlapping the gate electrode 19, the drain electrode 23, and the source electrode 21 to form an island.

The pixel electrode 17 formed on the pixel region P is connected to the drain electrode 23 through the drain electrode contact hole 25 and extends to the upper portion of the gate wiring 13 to form the gate wiring 13. And a capacitor C together with an insulating layer (not shown) thereunder.

The operation characteristics of the liquid crystal display device having the above-described configuration are as follows.

The gate electrode controls a flow of electric charge flowing through the surface of the active layer 27 between the source electrode and the drain electrode by applying a scan signal to the thin film transistor.

That is, when the gate electrode 19 is turned on, a data signal is transmitted through the data line 15 through the surface of the source electrode 21 and the active layer 27 and through the drain electrode 25. Is applied to the electrode 17.

In this case, the liquid crystal (not shown) arranged on the pixel P by the electric field applied from the pixel electrode 17 and the common electrode (not shown) is arranged in a predetermined form. Then, the amount of light incident from the backlight (not shown) is adjusted according to the arrangement of the liquid crystal to represent an image.

In the liquid crystal display device having the operation characteristics as described above, the thin film transistor T used as the switching element is laminated with a fine pattern of several layers to show the operation characteristics of the switching element. In order to obtain the desired operating characteristics, the thin film transistor T must be patterned precisely and accurately.

 2A to 2D are cross-sectional views of the process sequence of FIG. 1 taken along the line II-II.

As shown in FIG. 2A, first, a conductive metal having a low resistance such as aluminum is deposited on the substrate 11, and a conductive metal such as tungsten (W) or chromium (Cr) is continuously deposited and patterned to form a double layer. A gate wiring (not shown) and a gate electrode 19 are formed.

The gate electrode 19 may be formed by using a portion of the gate wiring (see 13 in FIG. 1) or protrudingly extending with a predetermined area from the gate wiring.

The reason why the gate wiring (see 13 in FIG. 1) is formed as a double layer is that aluminum (Al) has a low resistance, which serves to lower the time constant of the gate wiring, but is easily corroded by an etching solution during etching, resulting in poor wiring breakage. May cause.

Therefore, in order to prevent this, a conductive metal material having high corrosion resistance such as chromium (Cr) or tungsten (W) is laminated on the aluminum wiring to protect the lower aluminum wiring and at the same time, a self repair function is also provided. Done.

After forming the gate wiring (see 13 in FIG. 1), an insulating material such as a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN _X ) is deposited on the substrate on which the gate wiring is formed to form a gate insulator 14. GI).

Next, as shown in FIG. 2B, pure amorphous silicon (a-Si) and amorphous silicon (a-Si (n +)) containing impurities are sequentially stacked on the gate insulating layer 15 to form a semiconductor layer ( semiconductor layer).

Next, the semiconductor layer is patterned to form an active layer 27 and an ohmic contact layer 28 on the gate electrode 19.

Next, as illustrated in FIG. 2C, chromium is deposited and patterned on the entire surface of the substrate on which the ohmic contact layer 28 is formed, and the data wiring 15 intersecting the gate wiring (see 13 in FIG. 1) is formed. The source electrode 21 protruding from the data line 15 toward the gate line 13 and the drain electrode 23 spaced apart from each other are formed.

In this case, the source electrode 21 and the drain electrode 23 are patterned simultaneously with the ohmic contact layers 28a and 28b so that the active layer 27 between the source electrode 21 and the drain electrode 23 is exposed. do.

Meanwhile, at the same time as the source and drain electrodes, a capacitor electrode is formed in an island form on a portion of the gate wiring (13 in FIG. 1) where the capacitor (see C of FIG. 1) is formed.

Next, a passivation layer 33 is formed by depositing the above-described insulating material on the entire surface of the substrate on which the source electrode 21 and the drain electrode 23 are formed.

Next, as shown in FIG. 2D, a portion of the protective layer 31 on the drain electrode 23 is etched to form a drain electrode contact hole 25.

Next, a transparent conductive metal such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited and patterned on the entire surface of the substrate on which the drain electrode contact hole 25 is formed. The pixel electrode 17 in contact with the drain electrode 23 is formed through 25.

In the manufacturing process of the conventional array substrate described above, the metal forming the data wiring (15 of FIG. 1) and the source electrode 21 is etched by a wet etching method, and the wet etching method uses side etching as described above. It has anisotropic etching characteristics performed simultaneously.

Accordingly, excessive under cuts are generated on the side surfaces of the data line 15, the source electrode 21, and the drain electrode 23, and are eroded by the undercuts at a sharp inclination to the inside, and a shoulder at the upper end thereof. Is formed. However, since the shoulder affects the upper layer, the thickness of the pixel electrode 17 located on the upper portion of the drain electrode 23 is about 500 m 3, and the pixel electrode is the shoulder A of the drain electrode 23 described above. Occasionally, an open circuit is caused by a sudden step difference.

Since the open defect of the pixel electrode 17 does not drive the liquid crystal even when a signal is applied, the liquid crystal display device may cause defects, resulting in a problem of lowering the yield of the product.

In order to solve the problems as described above, an object of the present invention is to propose a method of manufacturing an array substrate for a liquid crystal display device that can prevent the disconnection of the pixel electrode by solving the problem occurring in the stepped portion of the drain electrode. It is done.

An array substrate manufacturing method for a liquid crystal display device for achieving the object of the present invention as described above comprises the steps of preparing a substrate; Forming a gate wiring and a gate electrode on the substrate; Depositing an insulating material on the substrate on which the gate wiring is formed to form a first insulating layer; Depositing a semiconductor material on the first insulating layer to form an active layer in an island shape on the gate electrode; Depositing a metal layer on a substrate on which the active layer is formed; Depositing and exposing a photoresist on said metal layer; Removing the unexposed photoresist; Etching the metal layer on which the exposed and patterned photoresist is not protected; Exposing a metal layer by removing a portion of the photoresist overly undersided of the metal layer protected by the photoresist; Etching the exposed portion of the metal layer to form a gentle inclination of a side that forms an excessive undercut to form a data line, a source electrode, and a drain electrode; Forming a contact hole on the drain electrode by forming and patterning a second insulating layer on an entire surface of the substrate on which the data line, the source electrode and the drain electrode are formed; Forming and patterning a transparent conductive metal on the second insulating layer to form a pixel electrode in contact with the drain electrode through the contact hole.

The first insulating layer is characterized in that the silicon oxide (SiO ₂ ) or silicon nitride (SiN _X ).

The side portion of the patterned photoresist is characterized in that it is removed by a dry etching method.

The etching gas used in the dry etching method is characterized in that the mixed gas of oxygen (O ₂ ) + SF ₆ .

The metal layer which is not protected by the photoresist may be removed by a wet etching method.

The etching solution used for the wet etching is characterized in that it comprises nitric acid + chlorine + hydrochloric acid + distilled water (HNO ₃ + Cl ₂ + HCl + DI).

After the photoresist is removed, the side portion of the exposed metal layer may be inclined by a dry etching method.

The etching gas used for the dry etching is characterized in that the mixed gas containing chlorine + helium (Cl ₂ + He).

The pixel electrode is characterized in that the transparent conductive metal.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, comprising: preparing a first substrate and a second substrate; Forming a gate wiring and a gate electrode on the first substrate;

Depositing an insulating material on the substrate on which the gate wiring is formed to form a first insulating layer; Depositing a semiconductor material on the first insulating layer to form an active layer in an island shape on the gate electrode; Depositing a metal layer on a substrate on which the active layer is formed; Depositing and exposing a photoresist on said metal layer; Removing the unexposed photoresist; Etching the metal layer on which the exposed and patterned photoresist is not protected; Exposing a metal layer by removing a portion of the photoresist overly undersided of the metal layer protected by the photoresist; Etching the exposed portion of the metal layer to form a gentle inclination of a side that forms an excessive undercut to form a data line, a source electrode, and a drain electrode; Forming a contact hole on the drain electrode by forming and patterning a second insulating layer on an entire surface of the substrate on which the data line, the source electrode and the drain electrode are formed; Forming and patterning a transparent conductive metal on the second insulating layer to form a pixel electrode in contact with the drain electrode through the contact hole; Forming a common electrode on the second substrate; Bonding the first substrate and the second substrate to a predetermined gap; and injecting a liquid crystal between the first substrate and the second substrate.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

An embodiment of the present invention proposes a method of preventing open defects of a pixel electrode due to a stepped portion of a drain electrode by etching the source / drain metal layer using two etching steps when patterning the drain electrode. This is described in detail below.

3A to 3C are process diagrams according to the present embodiment, which are briefly described as the processes of FIGS. 2A to 2B described above, and will be described with reference to the plan view of FIG. 1 as necessary.

First, a conductive metal having a low resistance such as aluminum is deposited on the substrate 111, and a conductive metal such as tungsten (W) or chromium (Cr) is continuously deposited and patterned to form a double layer gate wiring (13 in FIG. 1). And a gate electrode 119 are formed.

The gate electrode 119 is formed by using a portion of the gate wiring or protruding with a predetermined area in one direction from the gate wiring.

A gate insulator (GI) is formed by forming a gate wiring (13 in FIG. 1) and then depositing an insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN _X ) on the substrate on which the gate wiring is formed. ).

Next, pure amorphous silicon (a-Si) and amorphous silicon (a-Si (n +)) containing impurities are sequentially stacked on the gate insulating layer 115 to form a semiconductor layer.

The semiconductor layer is patterned to form an island-type active layer 127 and an ohmic contact layer 128 on the gate electrode 119.

In this case, the active layer 127 and the ohmic contact layer 128 may be formed larger than the area of the gate electrode.

Next, as illustrated in FIG. 3C, conductive metals such as chromium (Cr), tungsten (W), and molybdenum (Mo) are deposited on the entire surface of the substrate on which the active layer 127 and the ohmic contact layer 128 are formed. To form a source / drain metal layer.

Next, a photoresist 129 is formed on the source / drain metal layer in a pattern of a mask through a photolithography process including applying a photoresist on the source / drain metal layer.

Next, the source / drain metal layer which is not protected by the photoresist is etched, wherein the source / drain metal layer is etched by a wet etching method.

The wet etching method is advantageous in terms of good selectivity, large surface area etching uniformity, productivity, and low cost, and can be obtained at the same time. Therefore, the wet etching method is widely used in an array substrate forming process including a thin film transistor.

The wet etching is exposed to an etchant for a predetermined time in a bath to rapidly remove the thin film by chemical reaction and rapidly remove it by chemical distillation (DI water) to secure etching uniformity. After the first Quick Dipping Rinse process and the second rinse process to completely remove the trace chemicals with the distilled water (spin dry), spin dry to dewater by rotating the distilled water on the substrate at high speed Proceed in order.

For example, in the case of using a chromium (Cr) layer as the source / drain metal layer, the etching solution for etching the chromium layer is nitric acid (HNO ₃₎ + chlorine (Cl ₂ ) + hydrochloric acid (HCl) + A mixed solution containing distilled water (DI) is mixed and used at a predetermined ratio.

By the above-described method, the data line (15 in FIG. 1) intersecting with the gate line (13 in FIG. 1) and the insulating layer interposed therebetween, and the source electrode 121 protruding from the data line in the gate line direction. And the drain electrode 123 spaced apart from each other by a predetermined interval in plan view.

4A to 4E are enlarged process cross-sectional views of the portion B of FIG. 3C to illustrate the process of forming the drain electrode.

As shown in FIG. 4A, the side surface of the drain electrode 123 after the etching process by wet etching is excessively undercut into the photoresist 129 by the side etching of the etching solution. It can be seen that. This undercut creates a pointed shoulder on the side of the drain electrode 123.

Therefore, as shown in FIG. 4B, the shoulder portion C is removed by removing the photoresist 129 of the side portion of the photoresist on the drain electrode 123 in order to remove it. ).

The photoresist stripping may also use wet stripping and dry stripping. In the process of FIG. 4B, the photoresist 129 may be dried using dry stripping. The side part of) was removed.

In this embodiment, a mixed etching gas of O ₂ + SF ₆ was used to etch the side portion of the photoresist.

A process of removing the photoresist using the gas will be described below. When the substrate is placed in a plasma reaction chamber, a mixed etching gas of O ₂ + SF ₆ is added, and the energy is increased, oxygen is excited to a high energy level under the influence of the plasma field, and the photoresist component is oxidized to undergo a preashing process. SF ₆ serves to further promote etching.

The oxidized photoresist is converted to a compound gas and discharged in vacuo.

The reason why the side portion of the photoresist 129 can be selectively etched is that the photoresist of the side portion is thinner during the exposure process of the photoresist.

The portion to which the etching method is applied is applied not only to the side portion of the drain electrode but also to the photoresist formed on the side surface of the source electrode or the like patterned in a predetermined form.

Next, as shown in Figure 4c, in order to remove the shoulder portion of the side of the source / drain metal layer patterned by the wet etching including the drain electrode 123, the shoulder portion is removed using a dry etching method and the metal Make sure the sides of the membrane have a gentle slope. In this embodiment, a mixed gas of Cl ₂ + He mixed at a predetermined ratio was used as an etching gas to remove the shoulder portion.

Next, as shown in FIG. 4D, an ohmic contact layer exposed between the source electrode (see 121 of FIG. 3C) and the drain electrode (see 123 of FIG. 3C) by dry etching for removing the shoulder portion (FIG. 3C). (See 128) is simultaneously etched, which results in the gate insulating layer 115 being further etched to a predetermined thickness α while the ohmic contact layer is etched.

Next, as shown in FIG. 4E, through the process of removing the photoresist, a drain electrode 123 having a step D having a gentle inclination may be obtained.

FIG. 5 illustrates the formation of a protective layer 122 by depositing an insulating material on the substrate on which the source electrode 121 and the drain electrode 123 are formed through the aforementioned process, and patterning the drain electrode contact on the drain electrode. The hole 125 is formed.

Next, a transparent conductive metal such as indium tin oxide (ITO) and indium zinc oxide is deposited on the substrate on which the protective layer is formed to form a transparent conductive metal layer.

The transparent conductive metal layer is patterned to form the pixel electrode 131 in contact with the drain electrode 123 through the drain electrode contact hole 125.

Accordingly, the present invention has the effect of improving the yield of the product by removing the shoulder portion in the drain electrode to form a stepped portion having a gentle inclination, thereby preventing the disconnection of the pixel electrode generated by the shoulder of the drain electrode. .

Claims (10)

Preparing a substrate; Forming a gate wiring and a gate electrode on the substrate; Depositing an insulating material on the substrate on which the gate wiring is formed to form a first insulating layer; Depositing a semiconductor material on the first insulating layer to form an active layer in an island shape on the gate electrode; Depositing a metal layer on a substrate on which the active layer is formed; Depositing and exposing a photoresist on said metal layer; Removing the unexposed photoresist; Etching the exposed metal layer between the exposed and patterned photoresist; Exposing a metal layer by removing a portion of the photoresist overly undersided of the metal layer protected by the photoresist; Etching the exposed portion of the metal layer to form a gentle inclination of a side that forms an excessive undercut to form a data line, a source electrode, and a drain electrode; Forming a contact hole on the drain electrode by forming and patterning a second insulating layer on an entire surface of the substrate on which the data line, the source electrode and the drain electrode are formed; Forming and patterning a transparent conductive metal on the second insulating layer to form a pixel electrode in contact with the drain electrode through the contact hole; Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 1, And the first insulating layer is silicon oxide (SiO ₂ ) or silicon nitride (SiN _X ). The method of claim 1, And side surfaces of the patterned photoresist are removed by a dry etching method. The method of claim 3, wherein The etching gas used in the dry etching method is an array substrate manufacturing method of a mixed gas of oxygen (O ₂ ) + SF ₆ . The method of claim 1, And a metal layer not protected by the photoresist is removed by a wet etching method. The method of claim 5, The etching solution used in the wet etching is a mixed substrate containing nitric acid + chlorine + hydrochloric acid + distilled water (HNO ₃ + Cl ₂ + HCl + DI). The method of claim 1, After the photoresist is removed, the side surface portion of the exposed metal layer is formed to be inclined by a dry etching method. The method of claim 7, wherein The etching gas used for the dry etching is a mixed substrate containing chlorine + helium (Cl ₂ + He) gas array manufacturing method. The method of claim 1, The pixel electrode is a transparent conductive metal array substrate manufacturing method.  The method of claim 1, And the array substrate is used in a liquid crystal display device.

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