JP2005311579A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the frequency band characteristics of power gain and power efficiency by performing second or third harmonic processing for the basic wave over a wide phase angle range. <P>SOLUTION: A series resonance section (La, Ca) and a parallel resonance section (Lc, Lb, Cb) forming resonance circuits, respectively, for object harmonic frequencies while sustaining the matching conditions for the basic wave are provided in a harmonic processing circuit (20). When a capacitive or inductive reactance is added in the frequency regions before and behind the resonance frequency, reflection coefficient Γ can adjust its phase angle Γ_ANG over a wide range under a state where Γ_MAG is 1, resulting in wideband power gain and efficiency. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device that performs high-frequency power amplification, and in particular, the present invention relates to a circuit configuration that performs output matching and harmonic processing for efficiently transmitting a high-frequency power amplification signal to a next-stage circuit.

  Generally, in order to operate the amplifying element with high efficiency, the output load is short-circuited for even-order harmonics and open for odd-order harmonics with respect to the harmonics generated at the output of the amplifying element. By doing so, there is known a class F amplifier that eliminates power generation due to harmonics and increases the power component of the fundamental wave to operate the amplifier with high efficiency.

  In addition, matching processing for matching the output impedance with the input impedance of the next-stage circuit so as not to cause reflection with respect to the fundamental wave is realized by the impedance conversion circuit.

  In other words, a short circuit is realized with respect to even-order harmonics and an open state with respect to odd-order harmonics is realized, and the harmonic components are totally reflected and transmitted to the next-stage circuit by reflection including a signal (fundamental wave) of a desired frequency. As a result, the amplified fundamental wave is transmitted to the next stage circuit by efficiently using the power.

  Usually, in a high frequency amplifier circuit, in order to prevent transmission of harmonics to the next stage circuit and to transmit only the fundamental wave to the next stage circuit, a fundamental wave matching circuit and an absorption circuit for harmonics ( Reflection circuit).

  Patent Document 1 (Japanese Patent Application Laid-Open No. 7-263939) discloses three types of output matching circuits as conventional techniques. In the first configuration, a quarter wavelength line for the fundamental wave is connected between the output of the amplification transistor and the fundamental wave matching circuit, and an inductor is connected between the input of the fundamental wave matching circuit and the ground line (ground). A configuration is shown in which a parallel resonant circuit composed of a parallel circuit of capacitors is arranged. This parallel resonant circuit resonates in parallel with the fundamental wave and realizes an open state with respect to the fundamental wave. In a harmonic that is twice or more the frequency of the fundamental wave, the impedance is capacitive in the parallel resonance circuit, and a high-frequency component having a frequency that is twice or more that of the fundamental wave is bypassed to the ground line via the capacitor. Therefore, since the 1/4 wavelength line is in a short-circuited state with respect to the harmonic component, it functions as a 1/2 wavelength line for the second harmonic (second harmonic), and the third harmonic (third harmonic). (Wave) functions as a 3/4 wavelength line. Therefore, this 1/4 wavelength line realizes a short circuit state with respect to the output of the amplifying element for the second harmonic wave, and realizes an open state for the third harmonic wave. The quarter wavelength line is also coupled to a fundamental wave matching circuit, and functions as an impedance conversion element that matches the output impedance of the amplification transistor with respect to the fundamental wave to the impedance of the output load node.

  In the configuration of the second output matching circuit disclosed in Patent Document 1, a parallel resonant circuit of an inductor and a capacitor is connected in series between the output of the amplification transistor and the fundamental matching circuit, and the input of the fundamental matching circuit is provided. A series resonant circuit of an inductor and a capacitor is connected between the capacitor and the ground. The resonant frequency of the parallel resonant circuit is set to the frequency of the third harmonic, and the resonant frequency of the series resonant circuit is set to the frequency of the second harmonic. Therefore, this parallel resonant circuit is realized in an open state for the third harmonic wave and in a short-circuit state for the second harmonic wave. In the parallel resonant circuit, the impedance is inductive in the frequency region lower than the third harmonic, and the reactance component is almost ignored, and in this frequency region, the output node of the amplification transistor is almost in the reactance 0 and is in series resonance. Coupled to the input of the circuit and the fundamental matching circuit.

  Further, in the configuration of the third output matching circuit disclosed in Patent Document 1, a 1/12 wavelength line and a 1/6 wavelength line for the fundamental wave are provided between the output of the amplification transistor and the input of the fundamental wave matching circuit. Connect as an impedance line in series. An LC series resonant circuit that resonates at a third harmonic is connected between the connection point of these impedance lines and the ground, and an LC that resonates at a second harmonic frequency between the input of the fundamental matching circuit and the ground. Connect a series resonant circuit. The 1/12 wavelength line becomes a 1/4 wavelength line for the 3rd harmonic wave, and therefore provides an open condition for the output node of the amplification transistor for the 3rd harmonic wave. On the other hand, since these impedance lines as a whole function as a half-wave line for the second harmonic, a short circuit state is realized for the second harmonic. With respect to the fundamental wave, it functions as an ordinary quarter wavelength line, and functions as an impedance conversion element for matching between the output impedance of the amplification transistor and the fundamental wave matching circuit.

  In FIG. 4.17 of Non-Patent Document 1 ("RF Power Amplifier Wireless Communications" by Steve C., published by "Artech House"), amplification is performed. A configuration is shown in which a quarter-wave line of the fundamental wave is connected between the element output node and the power source to theoretically realize a short-circuit state for even-order high frequencies. In the configuration, an LC series resonance circuit of an inductor and a capacitor is connected between the output of the amplifying element and the ground as a harmonic trap circuit, and an output matching circuit is further provided in the subsequent stage. Is suitable for the current source of the amplifying element, with the reactance component being zero at the second harmonic and the impedance at the second harmonic as seen from the amplifying element output as viewed from the harmonic trap circuit is 0Ω. Giving second harmonic short circuit impedance shows a configuration for performing the second harmonic processing.

In the configuration disclosed in Patent Document 2 (Japanese Patent Laid-Open No. 8-148949), an LC series resonance circuit and an LC parallel resonance circuit are connected between the output of the amplifying element and the ground. The LC series resonance circuit resonates with the second harmonic, and the LC parallel resonance circuit operates with the LC series resonance circuit to resonate with the fundamental wave and the third harmonic. The impedance of this series resonant circuit is determined by considering the series inductive component of the internal impedance of the amplifying element, that is, when the amplifying element is composed of a field effect transistor (FET), considering the internal drain inductance. Sets the resonant frequency of the resonant circuit. The impedance value of the LC parallel resonance circuit is set to a value that resonates at the fundamental wave and the third harmonic in consideration of the reactance component of the series resonance circuit, the internal drain-source capacitor of the amplification FET, and the drain inductance. The output node of this amplifying element is also connected to the fundamental matching circuit. In Patent Document 2, the double-wave short-circuit condition is realized by an LC series resonance circuit. For the fundamental wave, the series resonance circuit is capacitive and the parallel resonance circuit is inductive, and the series resonance circuit and the parallel resonance circuit constitute a parallel resonance circuit that resonates with respect to the fundamental wave. For the third harmonic, the series resonant circuit is inductive and the parallel resonant circuit is capacitive, and a parallel resonant circuit that resonates at the third harmonic (third harmonic) is formed. Further, an impedance provided for the third harmonic (third harmonic) is set to be large by an inductor provided in series with the output matching circuit, and these harmonic processing circuits do not affect the fundamental matching circuit. To realize.

Patent Document 3 (Japanese Patent Laid-Open No. 2002-118428) shows a configuration in which a circuit having at least one attenuation pole in the pass characteristic is used as an output-side matching circuit provided in an output section of an amplifier circuit. This patent document 3 eliminates the loss in the low-pass filter by eliminating the low-pass filter on the output side, and achieves a highly efficient amplifier.
Japanese Patent Laid-Open No. 7-2631979 JP-A-8-148949 JP 2002-118428 A Steve C, "RF Power Amplifiers for Wireless Communications", published by Artech House

  In the configurations shown in Patent Documents 1 and 2 described above, a circuit for removing harmonic components of the second harmonic and the third harmonic is provided separately from the fundamental matching circuit. Therefore, an extra fundamental matching circuit is required, and the area occupied by the circuit increases.

  Further, in the configurations shown in these Patent Documents 1 and 2, no consideration is given to a configuration that widens the frequency band characteristics of the gain and efficiency.

  In the configuration shown in Patent Document 3, an L-type low-pass filter (LPF) is used as the basic configuration as an output matching circuit for the fundamental wave, and the inductance is changed by constant K-type LPF processing without changing the reactance component. Attenuation poles for the 2nd harmonic component and 3rd harmonic component affect the matching characteristics of the fundamental wave by converting to a parallel resonant circuit composed of a capacitor and an inductor, or converting a capacitor to a series resonant circuit To form without. However, this Patent Document 3 merely aims at forming an attenuation pole corresponding to a harmonic in the pass characteristic of the output matching circuit, and does not take into consideration the gain and efficiency band characteristics of the output signal. Absent.

  In the configuration shown in Non-Patent Document 1, it is said that it is difficult to satisfy the short-circuit condition for the second harmonic due to the influence of the reactance component of the pin terminal of the package, and load pull measurement is performed as a practical countermeasure. Thus, it is proposed to determine the final matching circuit parameters.

  Further, in this Non-Patent Document 1, it is shown in FIG. 4.20 that the frequency characteristics of power gain and efficiency are different, and there is no discussion about a configuration for widening both the efficiency and power gain bands.

  As also shown in the aforementioned Non-Patent Document 1, the second harmonic impedance given to the output of the actual amplifying element (transistor) is 0Ω ± j · X (Ω), which is different from 0Ω of an ideal short circuit. Become. If this state is represented by a reflection coefficient Γ, a phase angle of Γ = 1∠θ exists. Actually, a parasitic reactance component such as a series inductive component exists between the actual transistor region of the amplifying element and the second harmonic processing circuit. Therefore, it is more realistic that the actual second harmonic processing circuit can control the reactance component (phase angle) as Γ = 1∠θ. In particular, the phase control is performed by matching the fundamental wave. It is desirable to do so without affecting the system. Further, it is desirable from the viewpoint of application that this phase angle control can be controlled over a wide range so that it can be used for the third harmonic processing. That is, it is desirable that the second harmonic processing and the third harmonic processing can be realized with substantially the same configuration.

  In any of the above-described prior arts, the ideal short circuit state (Γ = 1∠180 °) is applied to the second harmonic, and the ideal open state (Γ = 1∠0 °) is applied to the third harmonic. ), And does not consider any configuration for controlling the phase angle θ of Γ = 1∠θ over a wide range.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of controlling a reactance component at the time of harmonic processing applied to an output of an amplifying element over a wide range with the same circuit configuration.

  A semiconductor device according to a first aspect of the present invention is connected between a transistor element that generates a signal corresponding to an input signal at an internal output terminal, and a load output node to which the internal output node and a load are coupled, A matching process for a fundamental wave component having a desired frequency and a resonance process for a harmonic component having a frequency that is an integral multiple of the fundamental wave are formed and a reactance component is added to the resonance state to commonly use an attenuation process for the harmonic wave component. An output processing circuit is provided.

  A semiconductor device according to a second aspect of the present invention connects a transistor having a conductive output region, a first conductor disposed opposite to the output region, and the first conductor and the output region. A plurality of wirings, a first transmission line connected to the first conductor and disposed in a U-shape, and a plurality of second lines disposed so as to be surrounded by the first transmission line and separated from each other , A second transmission line connected to the first conductor and arranged in a meandering shape, a first capacitor connected between the second transmission line and the ground line, and the first conductor And a second capacitor having one electrode connected to the first transmission line, one end connected to the other electrode of the second capacitor and the other end connected to the first transmission line, and a U-shape. The third transmission line arranged in the area and the inner area of the third transmission line are separated from each other A plurality of third conductors, a fourth transmission line having one end connected to the common coupling end of the first and third transmission lines, and a serpentine shape, and the fourth transmission line A plurality of fourth conductors arranged in a region surrounded by the meandering shape, and a third capacitor connected between the fourth transmission line and the ground line.

  A semiconductor device according to a third aspect of the present invention connects a transistor having a conductive output region, a first conductor disposed opposite to the output region, and the first conductor and the output region. A plurality of wirings, a first transmission line connected to the first conductor and disposed in a U-shape, and a plurality of second lines disposed so as to be surrounded by the first transmission line and separated from each other A second transmission line having one end connected to the first conductor and arranged in a meandering shape, and a first capacitor connected between the other end of the second transmission line and the ground line A second capacitor coupled between one end and the other end of the U-shape of the first transmission line, and a third connected between the other end of the first transmission line and the ground line. With a capacitor.

  A semiconductor device according to a fourth aspect of the present invention connects a transistor having a conductive output region, a first conductor disposed opposite to the output region, and the first conductor and the output region. A plurality of wirings, a first transmission line having one end connected to the first conductor and arranged in a U-shape, and a plurality of wirings surrounded by the first transmission line and separated from each other A second conductor, a second transmission line having one end connected to the first conductor and arranged in a meandering shape, and a first conductor connected between the other end of the second transmission line and the ground line A capacitor, a second capacitor having one electrode connected to one end of the first transmission line, one end connected to the other electrode of the second capacitor, and the other end connected to the first transmission line; Further, a third transmission line arranged in a U-shape facing the first transmission line A plurality of third conductors arranged separately from each other in the inner region of the third transmission line, and arranged in a region between the first and third transmission lines and of the first and third transmission lines A third capacitor connected between the common coupling end and the ground line is provided.

  A semiconductor device according to a fifth aspect of the present invention includes a transistor having a conductive output region, a first conductor disposed opposite the output region, and a plurality of conductors connecting the first conductor and the output region. Wiring, a first transmission line having one end connected to the first conductor and disposed in a U-shape, and a plurality of second lines disposed separately from each other so as to be surrounded by the first transmission line A second transmission line having one end connected to the first conductor and arranged in a meandering shape, and a first capacitor connected between the other end of the second transmission line and the ground line A second capacitor coupled between one end and the other end of the U-shape of the first transmission line, and one end connected to the other end of the first transmission line and arranged in a meandering shape A third transmission line and a plurality of third conductors arranged corresponding to the meandering shape of the third transmission line; And a third capacitor connected between the other end and the ground line of the third transmission line.

  A semiconductor device according to a sixth aspect of the present invention includes a transistor having a conductive output region, a first capacitor disposed opposite to the output region and having one electrode connected to a ground line, and an output A plurality of first wirings connecting the region and the other electrode of the first capacitor, a second conductor disposed opposite the output region with respect to the first capacitor, a second conductor and the output region A plurality of second wirings to be connected; a third conductor disposed away from the second conductor; a second capacitor having one electrode connected to the third conductor; and the other of the second capacitors A plurality of third wirings that connect the side electrode and the second conductor, a plurality of fourth wirings that connect the second conductor and the third conductor, and the third conductor are arranged to face each other. And a third and a fourth, each having one electrode connected to the ground line A capacitor, a plurality of fifth wirings connecting the other electrode of the third capacitor to the third conductor, and a plurality of sixth wirings connecting the other electrode of the fourth capacitor to the third conductor. Prepare.

  In the semiconductor device according to the first aspect of the present invention, the fundamental wave matching and the harmonic attenuation process are performed by a common filter circuit. In the harmonic attenuation process, a reactance component is added to the resonance state. Therefore, the phase of the reflection coefficient can be adjusted without substantially changing the magnitude of the reflection coefficient, and the phase angle of the reflection coefficient in the total reflection state can be controlled over a wide range in high frequency processing. Harmonic attenuation processing can be performed in a state different from the ideal open state, and the bandwidth of efficiency and power gain can be flattened over a wide range.

  According to the second to sixth aspects of the present invention, each transmission line or wiring can be used as an inductor when mounted on a board, and the parameters of a circuit for performing harmonic processing and fundamental wave matching processing can be easily set according to an actual application. Can be adjusted to a desired value.

[Embodiment 1]
FIG. 1 schematically shows an overall configuration of the semiconductor device according to the first embodiment of the present invention. In FIG. 1, a semiconductor device is connected to an amplifying element 1 that amplifies a high-frequency signal from an input unit (not shown) and outputs the amplified signal to an output terminal (node) 5, and an output signal of the amplifying element 1 to a load circuit in the next stage. The output processing circuit 2 for transmitting to the load output terminal 3 is included.

  The amplifying element 1 is composed of, for example, an LDMOSFET (laterally diffused insulated gate field effect transistor). Hereinafter, the amplifying element 1 is referred to as a device FET1.

  The output processing circuit 2 matches the impedance of the output terminal of the device FET1 and the impedance of the load output terminal 3 with respect to the fundamental wave, reflects a harmonic component to prevent transmission to the output load terminal 3, and Improve efficiency. A specific configuration of the output processing circuit 2 will be described later in detail, but a resonance matching circuit 10 that forms a parallel resonance circuit with a reactance component of the output region of the device FET1 to prevent transmission of harmonic components, It is connected in series between the device output terminal 5 and the load output terminal 3 to achieve impedance matching for the fundamental wave, and to achieve a reflection condition for the harmonic wave and to make the phase of the reflected wave wide. A harmonic processing circuit 20 that can be controlled across is included.

  The resonance matching circuit 10 cancels out the influence of the reactance component of the device FET1, and the harmonic processing circuit 20 controls the phase of the reflected wave to flatten the efficiency and gain over a wide band.

  The harmonic processing circuit 20 achieves both matching with the fundamental wave and impedance adjustment with respect to the harmonic with the same filter configuration. The harmonic processing circuit 20 performs processing of the second harmonic component and the third harmonic component that occupy a large proportion during power amplification. Although processing of higher harmonic components may be performed, a configuration for performing processing of the second harmonic (second harmonic) and third harmonic (third harmonic) will be described below.

  FIG. 2 is a diagram showing an example of the configuration of the harmonic processing circuit 20 shown in FIG. As shown in FIG. 2, the harmonic processing circuit 20 performs frequency conversion and impedance conversion using a constant K-type low-pass filter (LPF) 30 as a basic form. The constant K-type LPF 30 is a second-order constant K-type LPF, and includes an inductor L1 connected in series between the input node 20a and the output node 20c, an output node 20c, and reference nodes (ground: ground nodes) 20d and 20b. Including a capacitor C1 connected between the two. The coefficient K indicates the impedance conversion ratio of the normalization filter which is the basis of the second-order constant K-type LPF 30 (K = target impedance / normalization filter impedance). In the second-order constant K-type LPF, the product of the inductance L1 and the capacitance C1 is a constant value regardless of the value of the impedance conversion ratio K.

  The harmonic processing circuit 20 is formed using a secondary constant K-type LPF 30 composed of the inductor L1 and the capacitor C1 as a basic configuration. That is, the capacitor C1 is transformed into a series body of the inductor La and the capacitor Ca. The resonance frequency of the series resonance circuit formed by the inductor La and the capacitor Ca is made higher than the frequency of the fundamental wave. In this case, the series resonant circuit composed of the inductor La and the capacitor Ca has a capacitive impedance with respect to the fundamental wave, and functions as a constant K-type LPF capacitor.

  On the other hand, inductor L1 of constant K type LPF 30 is connected between nodes 20a and 20c in parallel with capacitors Cb and Lb connected in series between nodes 20a and 20c, and in parallel with capacitors Cb and inductor Lb. It is transformed into an inductor Lc. The reactance component formed by the inductor Lb and the capacitor Cb is capacitive in a frequency region below the series resonance frequency when the series resonance circuit is formed. Further, the reactance component formed by the capacitive reactance of the capacitor Cb and the inductor Lb and the inductor Lc connected in parallel to the capacitive reactance is inductive in a frequency region below the parallel resonance frequency. Inductive reactance functions as an inductor of the constant K-type LPF 30 with respect to the fundamental wave.

  Hereinafter, the locus of impedance between the nodes 20a and 20b of the harmonic processing circuit 20 shown in FIG. 2 will be examined.

  Now, as shown in FIG. 3A, it is assumed that the inductor Lb and the capacitor Cb are in a series resonance state, and the inductor La and the capacitor Ca are also in a series resonance state. That is, in the simplest case, La = Lb and Cb = Ca = Cb0, and the resonance frequency is f0. In this state, the impedance of the circuit composed of the capacitor Cb and the inductor Lb is 0, and the impedance of the circuit formed by the inductor La and the capacitor Ca is also 0. Therefore, as shown in FIG. 3B, when the impedance Z between the nodes 20a and 20b at the frequency f0 is plotted on the Smith chart, Z = 0 ± j0 (Ω), and the reflection coefficient Γ is Γ = 1∠180 °, indicating a complete short circuit state.

  Next, as shown in FIG. 4A, the capacitance value of the capacitor Cb is made smaller than the capacitance value Cb0, and the series resonance frequency of the inductor Lb and the capacitor Cb is shifted to a frequency f1 higher than the frequency f0. In this case, the frequency f0 is a region lower than the series resonance frequency f1, and the reactance component formed by the inductor Lb and the capacitor Cb at the frequency f0 is capacitive. Assuming that this capacitive reactance component is -jXc, as shown in FIG. 4A, the reactance component -jXc is connected in parallel with the inductor Lc. At this time, the resonance frequency of the parallel resonance circuit formed by the inductor Lc and the reactance component -jXc is set to a position lower than the resonance frequency f0. In this state, in the parallel resonance circuit formed by the inductor Lc and the reactance component −jXc, the reactance component is capacitive in the region of the series resonance frequency f0, and the amount of the inductor Lc can be ignored. Therefore, the impedance Z between the nodes 20a and 20b is 0-jXc (Ω) at the frequency f0. Here, the reactance component -jXc is represented by 1 / j (ω · Cb). Further, the capacitance value of the capacitor Cb is indicated by the same symbol. The same applies to the following description.

  When the impedance Z at the resonance frequency f0 of the circuit shown in FIG. 4A is plotted on a Smith chart, the phase is lower in the region below the constant reactance line with impedance 0 as shown in FIG. 4B. Change. That is, in terms of the reflection coefficient Γ, Γ = 1∠ (180 ° + θ, θ is positive).

  Next, from the state shown in FIG. 4A, the capacitance value of the capacitor Cb is shifted to a smaller capacitance value Cb2, and the series resonance frequency of the inductor Lb and the capacitor Cb is shifted to a position higher than the frequency f0. . In this case, the magnitude (absolute value) of the reactance component -jXc is increased. In this case, as shown in FIG. 5A, the resonance frequency of the parallel resonance circuit formed by the inductor Lc and the reactance component -jXc is set to f0. In this state, since the impedance of the parallel resonant circuit is infinite at the frequency f0, when the impedance Z between the nodes 20a and 20b is plotted on the Smith chart, as shown in FIG. The right end position, that is, the position of Z = ∞ ± j0. That is, a completely open state is realized with respect to the frequency f0 (Γ = 1∠0).

  The capacitance value of the capacitor Cb is further reduced and set to the capacitance value Cb3. In this state, the series resonance frequency f3 of the inductor Lb and the capacitor Cb is at a position higher than the frequency f0. Further, consider a state where the parallel resonance frequency f4 due to the inductor Lc and the reactance -jXc is higher than the frequency f0 and lower than the frequency f3 (f0 <f4 <f3). In this case, as shown in FIG. 6A, the parallel combined reactance component of the inductor Lc and the reactance component -jXc is inductive at the frequency f0. When this reactance component is + jX1, as shown in FIG. 6B, the plot point of the impedance Z between the node 20a and the node 20b on the Smith chart is Γ = (1∠θ), that is, Z = 0 + jX1 ( Ω). That is, the impedance Z is plotted in a region above the constant reactance line of reactance 0.

  Therefore, at the resonance frequency f0 of the series resonance circuit of the inductor La and the capacitor Ca, the impedance Z between the nodes 20a and 20b can control the imaginary term to be capacitive or inductive while maintaining the real term at 0Ω. It is also possible to realize a high impedance state with impedance Z = ∞. That is, the impedance Z is controlled in such a manner that the series reactance component formed by the inductor Lb and the capacitor Cb is connected in parallel with the series reactance component in a state where the resonance frequency of the series resonance circuit of the inductor La and the capacitor Ca is set to the frequency f0. This is possible by controlling the combined reactance component with the inductor Lc. Therefore, when the resonance frequency f0 is set to the second harmonic or the third harmonic, the impedance Z between the nodes 20a and 20b is short-circuited and the states before and after the second harmonic (second harmonic). Moreover, about the 3rd harmonic (3rd harmonic), it can set to an open | release and the state before and behind that.

  Further, by setting the frequency of the fundamental wave to a value lower than the resonance frequency f0, a circuit portion constituted by a series resonance circuit of an inductor Lb and a capacitor Cb and an inductor Lc connected in parallel with the series resonance circuit. 7A can be set to a constant inductive reactance component jXl, and the reactance component composed of the inductor La and the capacitor Ca is also shown in FIG. 7A. The constant capacitive reactance component jXc shown can be set. Therefore, with respect to this fundamental wave, impedance conversion is performed using the second-order constant K-type LPF 30 shown in FIG. 2 so as to satisfy the matching condition, and as shown in FIG. The impedance Z at the fundamental frequency fb can be plotted at the origin.

  That is, the reactance component is converted with respect to the secondary constant K-type LPF 30, and the converted reactance components are equal to the reactance components jXl and jXc shown in FIG. By setting the reactances of Lc and capacitors Ca and Cb, it is possible to match the fundamental wave and efficiently transmit the fundamental wave to the next stage circuit without causing reflection.

  In FIG. 7A, the matching condition for the fundamental wave is such that the reactance components jXl and jXc become zero in the fundamental frequency region in the impedance Z provided by the nodes 20a and 20b.

  In the above description, the resonance frequency f0 of the series resonance circuit of the inductor La and the capacitor Ca shown in FIG. 2 is set to the second harmonic or the third harmonic. However, provided that this resonance frequency f0 is present in a region higher than the fundamental frequency, if the impedance Z between the nodes 20a and 20b is in a state where a desired harmonic impedance is easily realized, This series resonance frequency f0 may be set to a frequency different from the second harmonic or the third harmonic.

  Further, the resonance matching circuit 10 shown in FIG. 1 functions in the direction of canceling the capacitive reactance component given by the drain-source capacitance Cds of the device FET1. Thus, the circuit parameters can be set in the harmonic processing circuit 20 without being affected by the drain capacitance Cds that varies depending on the voltage amplitude of the drain of the device FET1.

  Next, the impedance is specifically obtained for the equivalent circuit of the output processing circuit 2 of the semiconductor device according to the present invention. First, in order to see the function of the resonance matching circuit 10, an operation in the case of configuring a harmonic processing circuit without using this resonance matching circuit will be described.

  FIG. 8 is a diagram schematically showing the configuration of the output matching circuit (L match circuit) using the constant K-type LPF of the harmonic processing circuit 20 when the resonance matching circuit is not used. In FIG. 8, the device FET1 has a drain-source resistance Rds and a drain-source capacitance Cds connected in parallel to each other with respect to the output node. As described above, the device FET1 is assumed to be an LDMOFET. In the constant K type low-pass filter 40, the inductor L1 is divided into two inductors L11 and L12. A capacitor C1 is connected between the output node and the ground. The impedance when the device FET1 is viewed from between the split inductors L11 and L12 is expressed by Za. That is, it is considered that an L match circuit composed of an inductor L11 and a drain-source capacitance Cds and an L match circuit composed of an inductor L12 and a capacitor C1 are connected. In the case of this two-stage configuration, at the time of impedance conversion, the output load impedance Zds can be set to a value equal to or higher than the internal impedance Za, and accordingly, this output load impedance Zds is equal to or higher than the drain-source resistance Rds. It can have an impedance value, and the output voltage (power) can be increased.

  Actually, since the capacitor C1 is often realized by a surface mount capacitor or a MOS capacitor chip, the design freedom of the capacitor C1 is limited by the product, and the design freedom of the capacitance value is low. Therefore, the inductance of the inductor L1 is determined while keeping in mind the selection of the capacitance value of the capacitor C1. In the impedance Za when the output of the device FET1 is viewed from the dividing point of the inductor L1, a parallel body of the resistance component Rds and the capacitor Cds is connected in parallel to the series body of the inductor L11. Is expressed by the following equation.

  When output matching can be obtained at the angular frequency ω, the reactance component is 0, and the impedance Za and the reactance Xl11 are respectively expressed by the following equations.

  Accordingly, the reactance Xl11 is uniquely determined by the drain-source resistance Rds and the capacitance Cds of the device FET1.

  Next, in the impedance Zds when the output node of the device FET1 is viewed from the output node, the capacitor C1 is connected in parallel, and the inductor L12 and the impedance Za are connected in series. Therefore, impedance Zds viewed from this output node is expressed by the following equation.

  Since the matching condition is satisfied and the reactance component is 0 at the desired angular frequency ω, the load impedance Zds viewed from the output side terminal is expressed by the following equation.

  In this case, at the desired angular frequency ω, the impedance Za also has a reactance component of 0 and has only a resistance component. The condition that the final target output load impedance Zds is equal to or higher than the intermediate impedance Za is calculated from the impedance Zds of the above equation. In this case, when the reactance Xl12 is arranged, the following equation is obtained.

  Further, the condition for the reactance component A to be 0 is obtained by solving the quadratic equation of the reactance Xl12 in the above equation A.

  Further, the quality factor Q of this circuit is expressed by the following equation from the values of impedances Za and Zds at which the reactance component does not exist at the desired angular frequency ω.

  As can be seen from the above equation of quality factor Q, impedance Za is included. This impedance Za is affected by the drain-source capacitance Cds of the device FET1. The drain-source capacitance Cds fluctuates with the amplitude of the drain voltage in the device FET1 during nonlinear operation. When the drain amplitude is high (the drain voltage is high), the drain depletion layer becomes narrow, and this drain-source capacitance The capacity Cds is reduced.

  Therefore, when the output matching circuit is formed simply using the configuration of the constant K-type LPF 40, it is difficult to control the phase characteristics by offsetting the influence of the drain-source capacitance Cds. Therefore, in the present invention, the resonance matching circuit 10 is provided to cancel the influence of the drain-source capacitance of the device FET1, and the harmonic processing circuit 20 is not affected by the drain-source capacitance Cds. Perform harmonic processing. As a result, phase control can be performed stably, and a broadband power gain and efficiency can be realized.

  Further, by setting the quality factor Q to an appropriate value, a desired power gain characteristic can be obtained without reducing the efficiency, and the frequency characteristics of the power gain and efficiency can be substantially matched. .

  The output impedance Zl viewed from the device FET1 can be obtained by the following equation.

  Next, using the resonance matching circuit 10 according to the first embodiment of the present invention, the harmonic processing circuit 20 impairs output matching with respect to the fundamental wave without being affected by the drain-source capacitance Cds of the device FET1. A configuration for performing harmonic processing without any problem will be described.

  FIG. 9 shows an example of the configuration of output processing circuit 2 according to the first embodiment of the present invention. In FIG. 9, the device FET1 has a resistance Rds and a capacitance Cds with respect to its internal output node (device output node) 5.

  The resonant matching circuit 10 includes an inductor Le connected in series between the device output node 5 and the internal node 7, and an inductor Ld and a capacitor connected in series between the device output node 5 and the reference voltage line (ground) 45. Contains Cd.

  The harmonic processing circuit 20 has a configuration based on the constant K-type LPF described above, a capacitor Cb and an inductor Lb connected in series between the internal node 7 and the output node 3, and these capacitors Cb. And inductor Lc connected in parallel with inductor Lb between nodes 3 and 7, and inductor La and capacitor Ca connected in series between output node 3 and ground 45. An output load resistor Rk is connected between the output node 3 and the ground 45.

  Next, the parameter size of each component of the output processing circuit 2 will be examined. In the following description, reference numerals of components and capacitance values or inductance values are denoted by the same symbols.

  First, the impedance Zm when the resonance control circuit 10 is viewed from the internal node 7 (terminal surface Tm) is expressed by the following equation.

  First, in order to detect the change range of the impedance Zm, the extreme value of the impedance Zm when the resonance condition or the matching condition is satisfied in the impedance Zm, that is, when the reactance component is 0, is obtained. The impedance Zm when the reactance component becomes 0 at the angular frequency ω is expressed by the following equation.

  The impedance Zm is adjusted by changing the reactance of the series resonant circuit of the inductor Ld and the capacitor Cd when the reactance component is zero. In order to obtain the extreme value of the impedance Zm, the impedance Zm is differentiated with respect to the reactance Xl, and a value at which the numerator of the differential coefficient dZm / dXl becomes 0 is obtained. The molecular component Zm (num) of the differential coefficient dZm / dXl is expressed by the following equation.

  The impedance Zm takes an extreme value from the above equation when Xl = 0 and Xl = Xds. In the range of 0 ≦ Xl ≦ Xds, the molecular component Zm (num) is positive, and in other regions, the molecular component Zm (num) is negative. Therefore, the impedance Zm takes a minimum value when Xl = 0, When Xl = Xds, the impedance Zm takes a maximum value. The minimum value and the maximum value of the impedance Zm become 0 and Rds, respectively, by substituting Xl = 0 and Xds, respectively.

  Since the reactance component Xl ≧ 0, the impedance Zm at the angular frequency ω at which the reactance Xl is 0 takes a value equal to or less than the drain-source resistance Rds. The quality factor Q of the resonance matching circuit 10 satisfies the relationship expressed by the following equation with respect to the impedance Zm where the reactance component does not exist at the angular frequency ω and the drain-source resistance Rds of the device FET1.

  In the above equation, since the quality factor Q takes a non-negative value, it is necessary to satisfy the following equation.

Xl ≧ Xds
Since the impedance Zm takes the maximum value Rds at the angular frequency ω, the possible value of the impedance Zm at which the reactance component becomes 0 at the angular frequency ω is expressed by the following equation.

0 <Zm ≦ Rds
The reactance Xle is derived from the condition that the reactance component of the previous impedance Zm is 0 at the frequency ω. When these reactances Xl and Xle are each expressed by a quality factor Q, the following equation is obtained.

  At the angular frequency ω at which the reactance component of the impedance Zm is 0, the series resonant circuit formed by the inductor Ld and the capacitor Cd is inductive, and the reactance Xl takes a positive value. Is required to satisfy the following equation.

0 <Q ≦ Rds / Xds
The range that the element parameter of the resonance matching circuit 10 can take and the range that the quality factor Q can take are determined by the above-described calculation formula. That is, if the drain-source resistance Rds and the drain-source capacitance Cds of the output of the amplification transistor 1 can be determined, the reactance values of the inductors Ld and Le of the resonance matching circuit 10 and the capacitor Cd can be determined. The influence of the drain capacitance Cds can be offset. Actually, the element parameters of the resonance matching circuit 10 are optimized by load pull measurement. In this case, the resonance matching circuit 10 configured with the obtained optimum element parameters realizes impedance conversion that cancels (reduces) the influence of the reactance component of the amplification transistor 1. Therefore, in the harmonic processing circuit 20, it is possible to determine the element parameters for matching and harmonic processing without considering the drain-source capacitance Cds having a large voltage fluctuation, and stable matching and harmonic processing can be performed. Can be realized.

  Next, calculation of parameters of each component of the harmonic processing circuit 20 will be described.

  FIG. 10 is a diagram showing a simplified configuration of the harmonic processing circuit 20 shown in FIG. In FIG. 10, the harmonic processing circuit 20 is simplified to a constant K type LPF 50. The impedance conversion of the matching circuit in the first embodiment uses a constant K-type LPF. Therefore, the circuit portions of inductors Lb and Lc and capacitor Cb shown in FIG. 9 are replaced with inductor L as shown in FIG. 10, and inductor La and capacitor Ca are replaced with capacitor C. It is assumed that the impedance Zm when the resonance matching circuit 10 is viewed from the terminal surface Tm at the desired angular frequency ω during the impedance conversion operation satisfies the above-described condition, that is, the condition that the reactance component is zero. Hereinafter, the desired angular frequency is used as a frequency that satisfies the condition that the reactance component of the impedance Zm satisfies zero.

  The reactance components of the inductor L and the capacitor C of the constant K-type LPF 50 at the angular frequency ω are defined by the following equations as before.

j ・ ω ・ L = j ・ Xll
1 / (j · ω · C) = − j · Xc
Here, the inductance and the capacitance values of the inductor L and the capacitor C are respectively denoted by the same reference numerals.

  The impedance Zds when the constant K-type LPF 50 is viewed from the terminal surface Tk at the desired angular frequency ω is expressed by the following equation.

  When the reactance component of the impedance Zds is zero at the desired angular frequency ω, the impedance Zds is expressed by the following equation.

  The quality factor Q of the constant K-type LPF 50 is expressed by the following equation between impedances Zds and Zm where the reactance component does not exist at the desired angular frequency ω.

  The impedance Zds at which the reactance component becomes zero at the desired angular frequency ω is given a condition that it takes a value of 2 · Zm or more. That is, Q ≧ 1 is given as a condition. By increasing the impedance conversion ratio as much as possible, the output voltage (power) is increased and the bandwidth characteristic of the power gain is widened.

  Under this condition, the following equation is obtained from the above equation.

  When this inequality is rearranged for the reactance component Xll, the following equation (I) is obtained.

  On the other hand, the condition that the reactance component of the impedance Zds becomes zero at the desired angular frequency ω is expressed by the following equation from the condition that the imaginary term of the impedance Zds is zero.

  The reactance Xll of the formula (II) that satisfies the condition of the above formula (I) is determined. That is, by setting the reactance Xc of the capacitor C, the reactance Xll of the inductor L is determined.

  By deriving the reactance components Xll and Xc of the inductor L and the capacitor C of the constant K-type LPF 50, the constants of the respective elements of the original harmonic processing circuit 20 shown in FIG. 9 can be derived as described below. it can.

Derivation of constants for inductor La and capacitor Ca :
When a series resonance circuit composed of an inductor La and a capacitor Ca is resonated with the second harmonic, the impedance Z of the series resonance circuit satisfies the resonance condition at an angular frequency 2 · ω that is twice the desired angular frequency ω. . That is, the following relationship is satisfied.

  Similarly, when the series resonance circuit composed of the inductor La and the capacitor Ca is resonated with the third harmonic, the reactance components Xla and Xca satisfy the following relationship, respectively.

  By making the reactance component of the series resonant circuit composed of the inductor La and the capacitor Ca equal to the reactance component of the capacitor C of the constant K-type LPF 50 at the desired angular frequency ω, the matching condition for the fundamental wave is satisfied. Short circuit or open conditions for the second harmonic or the third harmonic can be realized. That is, when the second harmonic is reflected by the inductor La and the capacitor Ca (a short circuit condition is established), the relationship of the following equation (V) is obtained using the above equation (III).

-J.Xc = j.Xla-j.Xca = -j.3.Xca / 4
Therefore,
Xca = 4 · Xc / 3 (V)
On the other hand, when the series resonance circuit composed of the inductor La and the capacitor Ca resonates with respect to the third harmonic, the relationship of the following equation (VI) is satisfied using the above equation (IV).

-J.Xc = j.Xla-j.Xca = -j.8.Xca / 9
Therefore,
Xca = 9 · Xc / 8 (VI)
From equations (III) and (V), the reactance Xla satisfies the following relationship for the second harmonic resonance condition.

Xla = Xc / 3
On the other hand, from the equations (IV) and (VI), the reactance Xla satisfies the following equation for the third harmonic resonance condition.

Xla = Xc / 8
Therefore, by determining the reactance Xc of the capacitor C in the constant K-type LPF 50, the reactances Xla and Xca in which the inductor La and the capacitor Ca resonate at the second harmonic or the third harmonic can be derived.

  In the above equation, the reactance component of the capacitor C satisfies the following relationship.

1 / (j · ω · C) = − j · Xc
With this series of processing, the series resonance state shown in FIGS. 3 to 6 can be realized.

Derivation of reactance of inductors Lb and Lc and capacitor Cb :
In the second harmonic processing, the reactance component formed by the inductor Lb and the capacitor Cb shown in FIG. 9 is resonated before and after the second harmonic. The reactance of the inductor Lc connected in parallel to the reactance component of the inductor Lb and the capacitor Cb changes in conjunction with the resonance before and after the second harmonic (see FIGS. 3 and 4). At the desired angular frequency ω, the reactance of the circuit formed by the inductors Lb and Lc and the capacitor Cb is the same as the reactance Xll of the inductor L of the constant K-type LPF 50.

  In the third harmonic process, the reactance component formed by the inductor Lb and the capacitor Cb is a capacitive component. The reactance of the inductor Lc connected in parallel to the capacitive reactance component is inductive, and the parallel resonant circuit including the capacitive reactance and the inductor Lc resonates before and after the third harmonic (see FIG. 5). The reactance of the inductor Lc changes at frequencies before and after the parallel resonance. At the desired angular frequency ω, the reactance of the parallel circuit formed by the inductors Lb and Lc and the capacitor Cb is equal to the reactance Xll of the inductor L. Become. That is, the circuit formed by the capacitor Cb and the inductors Lb and Lc satisfies the relationship represented by the following formula (VII).

  The reactance Xll is determined according to the value of the impedance Zm in which the reactance Xc of the capacitor C and the reactance component are zero in the constant K-type LPF 50 shown in FIG. When the above relational expression (VII) is arranged for the reactance Xlc, the following expression (VIII) is obtained.

By determining the reactances Xll, Xlb, and Xcb from the equation (VIII), the reactance Xlc of the inductor Lc can be determined. In this equation, impedance Zm is included, and reactance of capacitance Cds is included in impedance Zm. However, the impedance Zm cancels the influence of the device capacity Cds and transmits power to the internal node 7. In the harmonic processing circuit 20, each parameter value is set without considering the influence of the device capacity. Even if it is determined, harmonic processing can be performed accurately. ,
In this relational expression (VIII), reactances Xlb and Xcb are variables that can be arbitrarily determined. However, by setting Xlb = Xla and Xcb = Xca as the initial values, the tendency of the impedance Zk when the resonance matching circuit 10 is seen from the output terminal surface Te of the device FET1 can be understood as shown in FIGS. It is easy to observe the frequency characteristics of the impedance when the constant value of each element is determined.

  FIG. 11 is a diagram for calculating the impedance Zk of the resonance matching circuit 10 viewed from the output node 5 of the device FET and the impedance Zrd of the drain-source capacitance Cds viewed from the drain-source resistance Rds of the device FET1. FIG. 3 is a diagram illustrating terminal surface development of the output processing circuit 2.

  Now, as shown in FIG. 11, the output node 3 to which the load Rk is connected is the terminal surface Tk, and the portion between the inductors La and Lb is the terminal surface T1. Further, the internal node 7 of the capacitor Cb and the inductor Le is defined as a terminal surface Tm. The portion between the inductor Ld and the inductor Le is the terminal surface T2, the device output node 5 is the terminal surface Te, and the portion between the drain-source resistance Rds and the drain-source capacitance Cds is the terminal surface Td. . The impedance Z1 when viewed from the terminal surface T1 in the load Rk direction is expressed by the following equation.

  In the above equation, the definition of each reactance component is the same as that in the above equation, and is not particularly noted.

  Next, the impedance Z2 viewed from the terminal surface T2 in the direction of the output load Rk is expressed by the following equation.

  Next, the impedance Zk viewed from the terminal surface Te in the direction of the output load Rk is expressed by the following equation.

  Impedance Zk (reflection coefficient Γk) and separation between terminals are calculated by setting each element parameter. Each frequency characteristic is obtained, displayed in a graph, and a parameter satisfying the required frequency band characteristic is determined. In this case, the impedance condition of the second harmonic or the third harmonic at the device end surface Te is obtained in advance by harmonic load pull measurement, the impedance is calculated based on the obtained value, and the magnitude of the reflection coefficient is calculated. Γ_MAG (= | Γ |) and reflection coefficient phase Γ_ANG (= ∠θ) are obtained, and the matching state with respect to the fundamental wave and the reflection condition with respect to the harmonic wave are observed.

  Hereinafter, the reflection coefficient corresponding to the impedance Zk when viewing the direction of the load resistance Rk from the device FET output terminal surface Te is denoted by Γk.

  FIG. 12 is a diagram showing the frequency dependence of the magnitude Γ_MAG of the reflection coefficient Γk with respect to the impedance Zk when the value of the capacitor Cb is changed.

  In FIG. 12, the reflection coefficient Γk is normalized using the real term (resistance component) of the impedance Zk at the fundamental frequency (175 MHz) as a normalized impedance. The capacitance of the capacitor Cb is changed in the range of 150 pF to 400 pF. As shown in FIG. 12, the magnitude of the reflection coefficient Γk is the same in the fundamental wave (desired frequency) regardless of the capacitance value of the capacitor Cb. This is because the value of the inductor Lc is controlled with respect to the change in the capacitance value of the capacitor Cb so that the impedance Zk with respect to the fundamental wave becomes a constant value. In the second harmonic (350 MHz), the magnitude of the reflection coefficient Γk is almost 1 regardless of the capacitance value of the capacitor Cb, indicating that total reflection occurs in the second harmonic.

  FIG. 13 is a diagram illustrating the frequency dependence of the phase angle Γk_ANG of the reflection coefficient Γk and the capacitance value of the capacitor Cb with respect to the impedance Zk. In FIG. 13, the fundamental wave is 175 MHz, and the capacitance value of the capacitor Cb is the same as that for the graph shown in FIG. Further, the reflection coefficient Γk is normalized by using the real term of the impedance Zk in the fundamental wave as a normalized impedance.

  As shown in FIG. 13, a state where the impedance Zk in the second harmonic is an ideal short circuit (Γk = 1∠180 °) (capacitor Cb = 379 pF) and a state where the constant of the capacitor Cb is changed within an appropriate range. Show. Regarding the reflection coefficient Γk for the second harmonic (350 MHz), the capacitance value of the capacitor Cb is 379 pF and a phase angle of 180 ° (= −180 °), which indicates an ideal short-circuit state. From this capacitance value, the capacitance of the capacitor Cb When the value is decreased, the phase angle changes from the negative region to the positive region, and when Cb = 200 pF, the phase angle is 0 °, that is, an open state. When the capacitance value of the capacitor Cb is further reduced, the phase angle enters a positive region. Therefore, the reflection coefficient Γk for the second harmonic can be adjusted in the phase angle over a very wide range by changing the capacitance value of the capacitor Cb and the reactance of the inductor Lc controlled according to the capacitance value. That is, the range of the phase θ can be changed at the reflection coefficient Γk = 1∠θ, and the desired state is realized.

  FIG. 14 is a diagram showing the frequency dependence of the signal attenuation (unit dB) between the terminal surfaces Te and Tk shown in FIG. Also in FIG. 14, the fundamental wave is 175 MHz, and the capacitance value of the capacitor Cb is changed. As for the attenuation, the reactance component formed by the inductor La and the capacitor Ca shown in FIG. 11 resonates at the second harmonic, and this series resonance circuit (formed by La and Ca) is short-circuited. A large amount of attenuation is secured. The attenuation between terminals is calculated based on the output circuit mismatch loss expressed by the following equation.

  Here, in the above equation, S11 is an S parameter obtained by viewing the matching circuit from the device output, and Γs represents a reflection coefficient of the device output. The reflection coefficient Γs and the S parameter S11 indicate signal transmission in the opposite direction. Therefore, if the output of the device FET is defined by, for example, the resistor Rds and the capacitor Cds, the state in which the S parameter S11 viewed from the device output is a complex conjugate with respect to the reflection coefficient Γ indicated thereby. As a reference, mismatch loss can be calculated according to changes in S-parameters.

  As can be seen from the above graph, the output processing circuit 2 according to the first embodiment effectively functions as a filter circuit that does not transmit the second harmonic component generated by the device FET1 to the next stage circuit such as an output load. .

  Note that FIGS. 12 to 14 show the characteristics of the second harmonic. However, for the third harmonic, the inductor La and the capacitor Ca constitute a series resonant circuit for the third harmonic, and the circuit constituted by the inductors Lb and Lc and the capacitor Cb is the third harmonic. A parallel resonant circuit is constructed. Even in this state, by changing the value of the capacitor Cb and setting the inductance of the inductor Lc to a value that can match the fundamental wave, the same characteristic can be obtained for the third harmonic, According to the capacitance value of the capacitor Cb, the phase angle of the reflection coefficient Γk in the total reflection state can be changed over a wide range.

  15 to 18 are diagrams showing a relationship between output power Pout, drain efficiency, and power gain for each frequency of the output processing circuit according to the embodiment of the present invention. 15 to 17, the horizontal axis represents output power Pout (unit dBm), the left vertical axis represents drain efficiency ηd (unit%), and the right vertical axis represents power gain (unit dB). Show. The measurement frequency ranges from 460 MHz to 500 MHz, and the step is 10 MHz. Under this measurement condition, the input power Pin is sequentially changed for each frequency, and the output power Pout is measured. The drain efficiency ηd detects the drain power by detecting the current and voltage at the drain terminal by harmonic load-pull measurement when the amplifying element is constituted by a MOSFET. The drain efficiency ηd is obtained from the ratio of the drain power and the DC power available to the power source to which the drain is connected. The power gain is obtained from the ratio between the input power Pin and the output power Pout (when the unit is dBm, the input power Pin is subtracted from the output power Pout).

  FIG. 15 shows the characteristics at the time of the third harmonic processing when the load Rk1 is connected when the inductors La and Lb are not provided in the configuration of the output processing circuit 2 shown in FIG. The characteristic at the time of the 3rd harmonic process in case an output load is resistance Rk1 is shown. FIG. 17 shows the second harmonic processing when the output load is Rk2 smaller than Rk1 when the second harmonic trap circuit and the constant K-type LPF shown in the conventional method (see Non-Patent Document 1) are used. Show properties. FIG. 18 shows the characteristics during the second harmonic processing when the output load resistance is Rk2.

  In the measurement in FIGS. 15 and 16, the third harmonic processing is performed when the fundamental wave is 480 MHz. 15 and 16 both show substantially the same characteristics in the case of the same output load Rk1. Therefore, in the third harmonic processing, in the series resonance circuit, the reactance component becomes capacitive in a region higher than the series resonance frequency, and the influence of these inductors La and Lb is reduced on the third harmonic processing. Therefore, substantially the same characteristics are realized. As for drain efficiency, substantially the same characteristics are obtained with respect to the angular frequency, and the variation in frequency between the power gains is also small. Therefore, both the flatness of the power gain and the flatness of the frequency band of the drain efficiency can be realized, and the band characteristics of the power gain and the drain efficiency can be matched over a wide range.

  Also, referring to FIGS. 17 and 18 showing the characteristics at the time of the second harmonic processing, almost the same characteristics can be obtained with respect to the power gain, and the drain efficiency is compared with the configuration shown in FIG. The drain efficiency of the output processing circuit gives the same characteristics regardless of the frequency. In FIGS. 17 and 18, therefore, appropriate second harmonic processing is realized even when compared with the configuration of the series LC harmonic trap circuit + constant K-type LPF based on the conventional method of second harmonic processing, and the efficiency is improved. The frequency band characteristics are further improved.

  The circuit characteristics shown in FIGS. 15 to 18 are based on the 60 W power matching condition, and the efficiency and the gain curve intersect at 60 W = 48 dBm.

  Therefore, by using the resonance matching circuit 10 and the harmonic processing circuit 20 according to the present invention, the second harmonic processing or the third harmonic processing can be controlled without breaking the fundamental matching without changing the equivalent circuit configuration. Can do. Therefore, by making the second harmonic processing or the third harmonic processing compatible with fundamental wave matching, the power gain and efficiency curve can be flattened over a wide frequency range. Hereinafter, a specific circuit configuration will be described.

  FIG. 19 schematically shows an arrangement on the substrate of a semiconductor device including output processing circuit 2 according to the present invention. In FIG. 19, the device FET1 is composed of an LDMOSFET chip having excellent high frequency response characteristics and suitable for surface mounting, has a wide gate width Wgt, and performs a large power amplification operation with its large current driving force. Opposing the drain region of the device FET1, a conductor (printed wiring pattern) 60 having a width substantially the same as that of the device FET1 and formed in a tapered pattern is provided. The conductor 60 and the drain region (output region) of the device FET 1 are bonded by a wiring (wire) 62. The resonance matching circuit 10 is connected between the conductor 60 and the ground, and the harmonic processing circuit 20 is provided between the conductor 60 and a load such as a matching circuit. The resonance matching circuit 10 includes an inductor Ld and a capacitor Cd connected in series between the conductor 60 and the ground. The inductor Le in the equivalent circuit is not provided in the configuration shown in FIG. The inductor Le is actually a parasitic inductance between the resonance matching circuit 10 and the output processing circuit 20, and depends on the physical shape of the wiring (transmission line) between the conductor 60 and the inductors Lc and Lb of the output processing circuit 20. Since it is determined, it is not shown in FIG.

  The inductors La to Ld may be realized by using any of a winding coil or a surface mount component mounted on the substrate, a microstrip line on the substrate, or a bonding wire.

  The capacitor Ca-Cd is configured by a chip capacitor or a MOS chip capacitor mounted on a substrate.

  In the semiconductor device shown in FIG. 19, when the drain capacitance Cds of the device FET1 is small and its influence can be ignored, it is not particularly required to provide the resonance matching circuit 10. Further, the inductors La and Lb can also be selectively deleted as is apparent from the characteristic curve shown in FIG. Hereinafter, the circuit arrangement on the board will be specifically described.

  The resonance matching circuit 10 is provided to cancel the influence of the drain-source capacitance Cds of the device FET. Therefore, the resonance matching circuit is not particularly required as long as the influence of the capacitance Cds is so small that it can be ignored.

[Example 1]
FIG. 20 is a diagram showing an arrangement example according to the first embodiment of the on-board arrangement of the semiconductor device according to the present invention. In FIG. 20, in the semiconductor device, a device FET (LDMOSFET chip) 1 is disposed on a conductive plate 65. The conductive plate 65 is fixed to a ground voltage, for example, and functions as a ground. An insulating substrate 68 is disposed on the conductive plate 65. The insulating substrate 68 is made of, for example, a glass epoxy substrate, and various wiring patterns and components are arranged on the surface of the insulating substrate 68 to realize one power amplification module.

  The chip back surface of the device FET1 is connected to the conductive plate 65 by, for example, solder, and the substrate region of the LDMOSFET is fixed to the ground voltage level.

  A conductor 60 having one end tapered is disposed on the insulating substrate 68 so as to face the device FET1. The conductor 60 has two protrusions 60a and 60b in the taper portion thereof. The conductor 60 has a straight end at the end facing the device FET1 and is connected to the drain region of the device FET1 by a wire 62 over a wide range. The An inductor Le in the equivalent circuit is formed by the inductance component of the conductor 60 and the wire 62. A portion including the device FET1, the bonding wire 62, and the conductor 60 is hereinafter referred to as an amplifying element 1A. It is considered that the parasitic inductance of the output portion of the amplifying element, that is, the inductance component of the inductor Le is negligible compared to reactances of other inductors La-Ld and capacitors Ca-Cd.

  Opposite the conductor 60, a conductor 70 is provided for electrically connecting the output of the device FET1 to the load of the next stage circuit (such as the next stage matching circuit) of the output processing circuit. Between the conductors 60 and 70, the conductor 74 is disposed in an island shape, and the conductors 71, 72, and 73 are disposed in alignment with the lower end of the insulating substrate 68 in the figure. The conductor 72 is connected to the conductor plate 65 formed on the back surface of the insulating substrate 68 through the through hole 90.

  The conductive line 80 that forms the inductor Lc is connected between the protruding portion 60a of the conductor 60 and the conductor 70, and the protruding portion 60b of the conductor 60 and the conductor 74 are connected by the conductive line 81 that forms the inductor Lb. A conductive line 82 that forms the inductor Ld is connected between the protruding portion 60 c of the conductor 60 and the conductor 71. In addition, a conductive line 83 forming an inductor La is connected between the conductors 70 and 73.

  In FIG. 20, the conductive lines forming the inductors La-Ld are shown to be realized by microstrip lines. However, these inductors La-Ld may be constituted by winding coils, or alternatively, may be constituted by surface mount chip coils (laminated type or winding type).

  A chip capacitor 84 forming a capacitor Cb is connected between the conductors 70 and 74, a chip capacitor 85 forming a capacitor Ca is connected between the conductors 73 and 72, and a capacitor Cd is connected between the conductors 71 and 72. A chip capacitor 86 is connected. Each of these capacitors Ca-Cd is a surface-mount type chip capacitor, and electrodes are formed on the back surface, and each is connected to a corresponding conductor. These capacitors Ca-Cd may also be composed of MOS type chip capacitors.

  In the configuration of the semiconductor device shown in FIG. 20, the components of the resonance matching circuit 10 and the harmonic processing circuit 20 shown in FIG. 19 are connected. By forming the conductor 60 of the output portion of the amplifying element 1A in a tapered shape, the conductive lines forming the inductors Lb-Ld can be connected efficiently. Since the device FET1 has a sufficiently wide gate width Wgt due to its large current driving force, the width of the conductor 60 is also sufficiently wide. By forming the end portion in a tapered shape, each component can be arranged with a small occupation area. Thus, the corresponding conductor and the chip electrode can be electrically connected.

[Example 2]
FIG. 21 shows a specific arrangement of the semiconductor device according to the second embodiment of the present invention. In the configuration of the semiconductor device shown in FIG. 21, inductors La and Lb are omitted. Therefore, the protrusion 60 b of the conductor 60 is connected to the conductor 70 via the chip capacitor 84. Further, the conductors 72 and 73 shown in FIG. 20 are converted into one conductor pattern 92, and the conductor 92 and the conductor 71 are connected to the chip capacitor 86 forming the capacitor Cd. The conductor 92 is also connected to the conductor 70 via the chip capacitor 85. This chip capacitor 85 forms a capacitor Ca. The conductor 92 is connected to the conductive plate 65 formed under the insulating substrate 68 through the through hole 94. The other configuration of the semiconductor device shown in FIG. 21 is the same as the configuration shown in FIG. 20, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 22 shows an electrical equivalent circuit of the semiconductor device shown in FIG. As shown in FIG. 22, in the output processing circuit 20, a capacitor Cb is connected in series between the conductor 60 and the output node 3, and a capacitive capacitor Ca is connected between the output node 3 and the ground. Therefore, the characteristics of the circuit configuration shown in FIGS. 21 and 22 are represented by the power gain and efficiency characteristics of FIG.

  The capacitor Cb and the inductor Lc form a parallel resonance circuit for the third harmonic. The capacitor Cb and the inductor Lc are operated inductively in a desired frequency region, and a matching condition for the desired frequency is established by the inductive reactance component and the capacitive reactance component of the capacitor Ca. The parallel resonant frequency of the parallel resonant circuit formed by the capacitor Cb and the inductor Lc is set in the vicinity of a frequency that is three times the desired frequency. The parallel oscillation circuit formed of the inductor Lc and the capacitor Cb achieves an open state with respect to the third harmonic by setting the phase angle of the reflection coefficient to a value different from 180 ° with respect to the third harmonic. The power amplification can be performed by flattening the band characteristics of power gain and efficiency. When the harmonic processing circuit 20 is applied to an application for performing the third harmonic processing, the inductors La and Lb can be eliminated, and the circuit occupation area can be reduced. The resonance matching circuit 10 matches the fundamental wave with respect to the drain capacitance of the device FET1, and gives the impedance of the reactance component 0 to the output of the device FET1 for the third harmonic.

[Example 3]
FIG. 23 schematically shows an on-board arrangement of the semiconductor device according to the third embodiment of the invention. The semiconductor device shown in FIG. 23 differs from the semiconductor device shown in FIG. 20 in the following points. That is, inductor La is removed, conductors 72 and 73 shown in FIG. 20 are integrated into conductor pattern 92, and chip capacitor 85 is connected between conductor patterns 92 and 70. The conductor pattern 92 is connected to the conductive plate below the insulating substrate 68 through the through hole 94. The other configuration of the semiconductor device shown in FIG. 23 is the same as the configuration of the semiconductor device shown in FIG. 20, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  24 is a diagram showing an electrical equivalent circuit of the semiconductor device shown in FIG. As shown in FIG. 24, in the harmonic processing circuit 20, a capacitor Ca is connected between the output node 3 and the ground. In the arrangement shown in FIG. 23, as is apparent from the electrical equivalent circuit of FIG. 24, no series resonant circuit is formed between the output node 3 and the ground. For the second harmonic, the reactance of the capacitor Ca becomes 0, and the capacitor Cb and the inductor Lb constitute a series resonance circuit for the second harmonic.

  For the third harmonic, the inductors Lb and Lc and the capacitor Cb constitute a parallel resonant circuit. That is, each circuit constant is set so that the third harmonic processing is performed in the harmonic processing circuit 20. That is, each parameter constant is set so as to satisfy the value of the previous impedance Zk. The inductor La in the harmonic processing circuit 20 becomes unnecessary, and the number of components of the circuit that performs the second or third harmonic processing can be reduced.

  FIG. 25 is a diagram showing the relationship between the power gain and drain efficiency for each frequency of the semiconductor device shown in FIG. 24 and the output power Pout. In FIG. 25, the horizontal axis represents output power Pout (unit dBm), the left vertical axis represents drain efficiency ηd (unit%), and the right vertical axis represents power gain (unit dB). The frequency is changed from 460 MHz to 500 MHz in 10 MHz steps. As shown in FIG. 25, the drain efficiency is the same at each frequency, and the gain has substantially the same characteristics. When the output power Pout giving power matching is 48 dBm, the variation of the gain with respect to the frequency is small, and even when the inductor La is not provided, the characteristics of the output power gain and the drain efficiency shown in FIGS. 15 and 16 are almost the same. Similar characteristics are obtained.

  Therefore, if it is possible to adjust the constant of each component to the load impedance Zk viewed from the device output of the second harmonic or the third harmonic, as shown in FIG. 24, the harmonic processing circuit 20 In this case, the inductor La can be eliminated. In the electrical equivalent circuit shown in FIG. 24, since a series resonant circuit does not exist between the output terminal 3 and the ground, a complete short-circuit state is not realized. However, in the present invention, in order to realize a state shifted by phase θ from this complete short-circuit state, the constant value of each component is set to a value that satisfies the target output impedance Zk even if the complete short-circuit state is not realized. If possible, processing of the second harmonic and the third harmonic can be performed.

[Example 4]
FIG. 26 schematically shows an on-board arrangement of the semiconductor device according to the fourth embodiment of the invention. The semiconductor device shown in FIG. 26 differs from the semiconductor device shown in FIG. 20 in the following points. That is, the chip capacitor 84 is connected between the protrusion 60 b of the conductor 60 and the conductor 70. The inductor Lb is not provided. The other configuration shown in FIG. 26 is the same as the configuration of the semiconductor device shown in FIG. 20, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 27 shows an electrical equivalent circuit of the semiconductor device shown in FIG. As shown in FIG. 27, in the semiconductor device shown in FIG. 26, in harmonic processing circuit 20, inductor Lc and capacitor Cb are connected in parallel between conductor 60 and output node 3. An inductor La and a capacitor Ca are connected in series between the output terminal 3 and the ground. Therefore, in this case, since the series resonance circuit and the parallel resonance circuit are provided in the harmonic processing circuit 20, even when the inductor Lb is not provided, the second harmonic processing or the third harmonic processing is the target output. This can be realized by setting the reactance of each component to a constant value that satisfies the impedance Zk.

  For the second harmonic, the capacitor Cb functions as a bypass capacitor, and the inductor La and the capacitor Ca act as a series resonance circuit. For the fundamental wave, the combined reactance of the inductor Lc and the capacitor Cb is inductive, and the combined reactance of the capacitor Ca and the inductor La is capacitive, so that the matching condition for the fundamental wave is satisfied.

  For the third harmonic, the capacitor Ca and the inductor La become a series resonance circuit, and the reactance of the circuit constituted by the capacitor Cb and the inductor Lc is set before and after the parallel resonance condition. The fundamental wave is the same as in the case of the second harmonic.

  FIG. 28 is a diagram showing the relationship between output power, drain efficiency, and gain for each frequency of the electrical equivalent circuit shown in FIG. Also in FIG. 28, the frequency is changed from 460 MHz to 500 MHz at step 10 MHz. The output power Pout is observed by changing the input power Pin for each frequency. FIG. 28 shows the characteristics when the third harmonic processing is performed when the fundamental wave is 480 MHz. The characteristics shown in FIG. 28 are almost the same as those in the third harmonic processing shown in FIG. 16, and even when the inductor Lb is not provided, the constants of the respective constituent elements are set to appropriate values. The drain efficiency ηd and the gain can be obtained with substantially the same characteristics as when the inductor Lb is provided.

[Example 5]
FIG. 29 schematically shows the on-board layout of the semiconductor device according to the fifth embodiment of the present invention. In FIG. 29, a T-type conductor (printed wiring pattern) 100 is disposed to face the output region (drain terminal portion) of the device FET1. The width direction of the conductor pattern 100 is substantially the same as the width of the output region (drain region) of the device FET1. The conductor 100 is connected to the output portion region (drain region) of the device FET 1 by a plurality of wires 62.

  A U-shaped transmission line (microstrip line) 101 is provided at the bottom of the T-shape of the conductor 100. A plurality of floating conductors 102 that are in an electrically floating state are arranged in the U-shaped region of the transmission line 101. One floating conductor 102 is connected to the U-shaped transmission line 101 at both ends by, for example, solder 115. The transmission line 101 constitutes an inductor Lc, and the length of the transmission line 101 is adjusted by a short circuit with the floating conductor 102, and the reactance of the inductor Lc is adjusted accordingly.

  A transmission line (microstrip line) 103 is arranged in a U-shape similarly to the U-shaped transmission line 101. These transmission lines 101 and 103 are coupled in common and coupled to a load such as a matching circuit at the next stage. Also in the U-shaped transmission line 103, a plurality of floating conductors 104 formed in an island shape are arranged separately from each other. In the arrangement shown in FIG. 29, the floating conductor 104 is kept electrically separated from the transmission line 103. The leg portion of the T-shaped conductor pattern 100 is also connected to the transmission line 103 via a chip capacitor 112 that forms a capacitor Cb.

  Further, the conductor pattern 100 is provided with a meandering transmission line (microstrip line) 105 extending continuously at the lower part of the top of the T-shape. The meandering transmission line 105 constitutes an inductor Ld, and the inductance is set by the meandering wiring length. The meandering transmission line 105 is connected to a conductor (wiring pattern) 107 via a chip capacitor 110 forming a capacitor Cd. The conductor 107 is connected to a conductive plate formed under the insulating substrate 68 through the through hole 108.

  A transmission line 106 is arranged in a meandering shape from the common coupling portion of the transmission lines 103 and 101. A floating conductor 109 is provided in a meandering region of the meandering transmission line 106. Using one of the floating conductors 109, one U-shaped region of the transmission line 106 is short-circuited by the solder 116, and its inductance value (reactance) is adjusted. The transmission line 106 is coupled to a conductor (wiring pattern) 107 via a chip capacitor 111 at the end thereof. The chip capacitor 111 constitutes a capacitor Ca.

  That is, in the arrangement shown in FIG. 29, inductors La-Ld are formed using transmission lines 101, 103, 105, 106 such as strip lines. Each of the chip capacitors Ca-Cd is composed of a surface mount type chip capacitor.

  Therefore, in the arrangement shown in FIG. 29, by forming the inductor with a strip line (microstrip line), the height of the board can be reduced compared to a configuration using a winding coil or the like, The inductance value can be finely adjusted.

  The electrical equivalent circuit of the semiconductor device shown in FIG. 29 is the same as the electrical equivalent circuit shown in FIG.

[Example 6]
FIG. 30 schematically shows the on-board layout of the semiconductor device according to the sixth embodiment of the present invention. The semiconductor device shown in FIG. 30 differs from the semiconductor device shown in FIG. 29 in the following points. That is, the U-shaped microstrip line forming the inductor Lb is not provided. Therefore, a U-shaped microstrip line (transmission line) 101 is connected to the T-shaped leg portion of the conductor 100. Both ends of the U-shape of the transmission line 101 are connected via a chip capacitor 112. The chip capacitor 112 forms a capacitor Cb. The output end of the transmission line 101 is connected to the conductor pattern 120 via the chip capacitor 111. The conductor pattern 120 is connected to a conductive plate 65 provided under the insulating substrate 68 through a through hole 125. Since the transmission line forming the inductor Lc is connected to the ground via the capacitor Ca, similarly, the strip line 106 arranged in a meandering shape shown in FIG. 29 is not provided, and the inductor La is not provided.

  The other configuration of the semiconductor device shown in FIG. 30 is the same as that of the semiconductor device shown in FIG. 29, and the corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  Therefore, in the semiconductor device shown in FIG. 30, inductors La and Lb are not provided in the output processing circuit. Therefore, the electrical equivalent circuit is the same as the electrical equivalent circuit shown in FIG. 22, and the harmonic processing circuit 20 executes processing for the third harmonic. The constant value of each inductor and capacitor is adjusted so as to satisfy the value at the third harmonic of the target impedance Zk. Thereby, the attenuation process for the third harmonic component can be performed.

  In the semiconductor device shown in FIG. 30, the inductor is not provided, and the inductor is formed of a microstrip line, so that the height of the circuit can be reduced and the area occupied by the circuit can be reduced. Inductance can be adjusted accurately and finely.

[Example 7]
FIG. 31 schematically shows an arrangement of the semiconductor device according to the seventh embodiment of the present invention on the board. The semiconductor device shown in FIG. 31 differs from the semiconductor device shown in FIG. 29 in the following points. That is, the conductor pattern 122 is disposed between the U-shaped transmission lines 101 and 103. The conductor pattern 122 is connected to the conductive plate through a through hole. The common coupling ends of the U-shaped transmission lines 101 and 103 and the conductor pattern 122 are connected by a surface mount type chip capacitor 111. This surface-mounted chip capacitor 111 forms a capacitor Ca. Only the surface-mounted capacitor 111 is connected to the common coupling end of the U-shaped transmission lines 101 and 103, and the meandering transmission line (microstrip line) shown in FIG. 29 is not provided. Therefore, the inductor La is not used in this semiconductor device. The other configuration of the semiconductor device shown in FIG. 31 is the same as the arrangement of the semiconductor device shown in FIG. 29, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The electrical equivalent circuit of the semiconductor device shown in FIG. 31 is the same as the electrical equivalent circuit shown in FIG. 24, and only a capacitor Ca is provided between the output node 3 of the harmonic processing circuit 20 and the ground. is there.

  In this case, similarly, a series resonance circuit is not formed between the output node of the harmonic processing circuit and the ground, and the harmonic processing is performed at a position shifted in phase from the resonance point. In order to obtain power gain characteristics over a wide phase angle, no series resonance circuit is formed, and there is no particular problem even if the phase is shifted from the resonance point. If the constant of each component is set so that each constant value satisfies the value of the impedance Zk at the frequency targeted for the second harmonic or the third harmonic, substantially the same characteristics can be obtained.

  FIG. 32 is a diagram showing gain and drain efficiency ηd for each frequency of the semiconductor device shown in FIG. In FIG. 32, the horizontal axis represents output power Pout (unit dBm), the right vertical axis represents power gain (unit dB), and the left vertical axis represents drain efficiency ηd (unit%). FIG. 32 shows the characteristics during the second harmonic processing. The frequency is in the frequency range from 460 to 500 MHz, and power matching is taken at the output power Pout of 48 dBm.

  As shown in FIG. 32, when the inductor La is configured using a microstrip line, even when the inductor La is not provided, the characteristics when the second harmonic processing is performed are performed using the inductor La. The characteristic similar to the characteristic shown in FIG. Therefore, by setting the constant values of the circuit inductor and the capacitor so as to satisfy the impedance condition in the target frequency region, the number of components is reduced, and the harmonic processing is performed on the second harmonic or the third harmonic. And a wide frequency band characteristic can be imparted to both power gain and drain efficiency.

[Example 8]
FIG. 33 schematically shows an on-board arrangement of a semiconductor device according to the eighth embodiment of the present invention. The semiconductor device shown in FIG. 33 differs from the semiconductor device shown in FIG. 29 in the following points. That is, the U-shaped transmission line (microstrip line) forming the inductor Lb is not provided. Both ends of the U-shape of the transmission line 101 forming the inductor Lc are connected via the chip capacitor 112. The chip capacitor 112 forms a capacitor Cb, and the capacitor Cb and the inductor Lc are connected in parallel. The other configuration of the semiconductor device shown in FIG. 33 is the same as the configuration of the semiconductor device shown in FIG. 29, and corresponding portions bear the same reference numerals and will not be described in detail.

  Therefore, the electrical equivalent circuit of the semiconductor device shown in FIG. 33 is given by the electrical equivalent circuit shown in FIG. In the harmonic processing circuit, even if the inductor Lb is omitted, if the constants of the inductors and the capacitors can be adjusted so that the impedance Zk achieves the target value for the harmonic to be processed, Similarly, the phase of the reflection coefficient can be changed over a wide range by adding an inductive reactance component to a state in which a series resonance state is substantially realized with respect to the output terminal.

  The frequency characteristics shown in FIG. 34 are substantially the same as the characteristics shown in FIG. 18, and even if the inductor Lb is omitted, the same characteristics can be realized, and the number of circuit components can be reduced. The element parameters can be set accurately.

[Example 9]
FIG. 35 schematically shows an on-board arrangement of the semiconductor device according to the ninth embodiment of the invention. In the configuration shown in FIG. 35, device FET1 and MOS type chip capacitor 200 are arranged on conductive plate 65 so as to face each other. This MOS chip capacitor 200 corresponds to the capacitor Cd. The output portion (drain region) of the device FET1 and one electrode of the MOS chip capacitor 200 are electrically connected to each other at a plurality of locations by wires 202. The other electrode of the MOS chip capacitor 200 is connected to the conductive plate 65. By adjusting the number, line width (diameter) and length of the plurality of wires 202, an inductor Ld having a necessary reactance is formed.

  A conductive (wiring pattern) 204 is provided on the insulating substrate 68 adjacent to the end of the conductive plate 65. The conductive material 204 is also connected to the output portion (drain region) of the device FET by a plurality of wires 203. The number of wires 203 and their line width, length, and wire diameter are also adjusted to realize an inductor Le having a necessary reactance value.

  A conductor (wiring pattern) 206 is formed on the insulating substrate 68 so as to face the conductor 204. A portion passing through the insulating substrate 68 is provided adjacent to the conductor 206, and the conductive plates 207 and 208 are exposed. MOS type chip capacitors 210 and 212 are arranged on conductive plates 207 and 208, respectively. MOS type chip capacitors 210 and 212 have their lower electrodes electrically connected to conductive plates 207 and 208, respectively. In the MOS type chip capacitor 210, the upper electrode is electrically connected to the conductive pattern 206 via the wire 215, and the MOS type chip capacitor 212 is electrically connected to the conductor (wiring pattern) 206 via the wire 217. Connected.

  A MOS chip capacitor 218 is also disposed on the conductor 206, and the upper electrode of the MOS chip capacitor 218 is electrically connected to the conductor (wiring pattern) 204 by a wire 219. This MOS type chip capacitor 218 corresponds to the capacitor Cb. By adjusting the number, the wire diameter, and the length of the wire 205 between the conductors 204 and 206, the reactance of the inductor Lc is adjusted. Similarly, the reactance of the inductor Lb is adjusted by adjusting the number, wire diameter, and length of the wires 219 connected to the upper electrode of the MOS chip capacitor 218.

  Further, the reactances of these inductors La are adjusted by adjusting the wire diameters, numbers, and lengths of the wires 215 and 217. MOS type chip capacitors 210 and 212 form capacitor Ca (MOS type chip capacitors 210 and 212 are connected in parallel by wires 215 and 217 between conductor 206 (output node) and ground.

  FIG. 36 shows a schematic cross-sectional structure of device FET, MOS chip capacitor 200 and conductor pattern 204 of the semiconductor device shown in FIG. As shown in FIG. 36, the device FET1 and the MOS chip capacitor 200 are arranged on the conductive plate 65. The back surface of the device FET1 and the lower electrode of the MOS chip capacitor 200 are electrically connected to the conductive plate 65 by solder or the like (not shown). On the other hand, an insulating substrate 68 is disposed on the conductive plate 65, and a wiring pattern (conductor) 204 is provided on the surface of the insulating substrate 68.

  The output portion of the device FET1 is electrically connected to the upper electrode of the MOS chip capacitor 200 by a wire 202, and is electrically connected to a conductor 204 by a wire 203. By adjusting the number of these wires 202 and 203 and the height and distance at the time of mounting thereof, a reactance component necessary for the inductors Ld and Le can be provided. Similarly, by adjusting the number, height, and distance (length) of the other wires 205, 219, 215, and 217 as well, necessary inductances can be given to the inductors La, Lb, and Lc, respectively. .

  On the other hand, in order to minimize the inductance of the inductor, the number of wires is increased, and the length is made as short as possible by taking the height and distance into account. Thereby, each of the inductors La and Lb can be set to a state in which the electrical influence can be almost ignored by the corresponding wires 215, 217 and 219, and a state in which the inductors La and Lb are not present can be realized. it can.

  As shown in FIG. 35, by controlling the number of wires, the height of the wires, and the distance between the wire bonds in the MOS type chip capacitor, the wires 203, 202, 205, 215, 217 and 219 are made to have their wire inductances. Can function as an active inductance function, or can operate as a connection medium without an inductance function in which the inductance value is actively reduced sufficiently. Therefore, there is no aspect in which the second harmonic processing or the third harmonic processing is realized as the harmonic processing circuit having the inductors La and Lb or the inductors La and Lb without changing the arrangement positions of the components on the board. The second harmonic processing or the third harmonic processing can be realized as a mode in which the third harmonic processing is applied as the harmonic processing circuit and the harmonic processing circuit without the inductor La or Lb.

  The semiconductor device according to the present invention can be applied to an output matching circuit of a power amplifier. For example, the semiconductor device according to the present invention is applied to a module of a 60 W class power amplifier so that the frequency band of power efficiency and gain is widened. Can be realized.

  In the above description, an LDMOSFET having excellent high frequency characteristics is used as the device FET. The present invention can also be applied to a power amplifier in which a MESFET (metal-semiconductor field effect transistor) is used as an amplifying element instead of the LDMOSFET. Similarly, the drain electrode includes a source electrode, a gate electrode, and a chip. The same applies to VDMOSs ("Vertically diffused" MOSFETs) present on the opposite side with respect to. When this VDMOSFET is mounted on a board, a device FET is arranged on the insulating substrate 68, and the same arrangement is realized by connecting the drain electrode as an upper electrode and the source and gate electrodes as lower electrodes by printed wiring. can do.

  The power amplifying element may be a bipolar transistor. The semiconductor device is mounted on an insulating substrate such as a glass epoxy substrate to constitute a power amplification module. However, the semiconductor device may be integrated on a semiconductor chip or a semi-insulator chip.

  As described above, attenuation processing for the second harmonic component and the third harmonic component, which are strong components during power amplification operation, can be realized with the same circuit configuration, and a highly versatile output matching circuit is realized. Can do.

1 schematically shows an entire configuration of a semiconductor device according to the present invention. FIG. FIG. 2 is a diagram schematically showing a configuration of a harmonic processing circuit shown in FIG. 1. (A) And (B) is a figure which shows the state of a harmonic process. (A) And (B) is a figure which shows the state of the harmonic processing operation | movement according to this invention. (A) And (B) is a figure which shows the state of the harmonic processing operation | movement according to this invention. (A) And (B) is a figure which shows the state of the harmonic processing operation | movement according to this invention. (A) And (B) is a figure which shows the state of the harmonic processing operation | movement according to this invention. It is a figure which shows the starting structure of a harmonic processing circuit. It is a figure which shows the specific structure of the output processing circuit shown in FIG. FIG. 10 is a diagram showing an equivalent circuit of the output processing circuit shown in FIG. 9. It is a figure which shows distribution of the impedance of the output processing circuit according to this invention. It is a figure which shows the magnitude frequency dependence of the reflection coefficient of the harmonic processing circuit according to this invention. It is a figure which shows the frequency dependence of the phase angle of the reflection coefficient of the harmonic processing operation according to this invention. It is a figure which shows the frequency dependence of the attenuation amount between input-output terminals of the harmonic processing operation | movement according to this invention. It is a figure which shows the relationship between the output electric power of the output processing circuit according to this invention, a gain, and drain efficiency. It is a figure which shows the relationship between the output electric power of a harmonic processing operation | movement according to this invention, a gain, and drain efficiency. It is a figure which shows the relationship between the output electric power in a conventional harmonic processing structure, a gain, and drain efficiency. It is a figure which shows the relationship between the output electric power of the output processing circuit according to this invention, a gain, and drain efficiency. It is a figure which shows the specific arrangement | positioning of the output processing circuit according to this invention. It is a figure which shows typically arrangement | positioning on the board | substrate of the semiconductor device according to Example 1 of this invention. It is a figure which shows typically arrangement | positioning on the board | substrate of the semiconductor device according to Example 2 of this invention. FIG. 22 is a diagram showing an electrical equivalent circuit of the semiconductor device shown in FIG. 21. It is a figure which shows schematically arrangement | positioning on the board | substrate of the semiconductor device according to Example 3 of this invention. FIG. 24 is a diagram showing an electrical equivalent circuit of the semiconductor device shown in FIG. 23. FIG. 24 is a diagram illustrating a relationship between output power, gain, and drain efficiency of the output processing circuit illustrated in FIG. 23. It is a figure which shows schematically arrangement | positioning on the board | substrate of the semiconductor device according to Example 4 of this invention. FIG. 27 is a diagram showing an electrical equivalent circuit of the semiconductor device shown in FIG. 26. FIG. 27 is a diagram showing a relationship between output power, gain, and drain efficiency of the semiconductor device shown in FIG. 26. It is a figure which shows schematically arrangement | positioning on the board | substrate of the semiconductor device according to Example 5 of this invention. It is a figure which shows typically the board | substrate arrangement | positioning of the semiconductor device according to Example 6 of this invention. It is a figure which shows schematically arrangement | positioning on the board | substrate of the semiconductor device according to Example 7 of this invention. FIG. 32 is a diagram showing a relationship between output power, gain, and efficiency of the semiconductor device shown in FIG. 31. It is a figure which shows schematically arrangement | positioning on the board | substrate of the semiconductor device according to Example 8 of this invention. FIG. 34 is a diagram showing a relationship between output power, gain, and efficiency of the semiconductor device shown in FIG. 33. It is a figure which shows roughly arrangement | positioning on the board | substrate of the semiconductor device according to Example 9 of this invention. FIG. 36 schematically shows a cross-sectional structure of a substantial part of the semiconductor device shown in FIG. 35.

Explanation of symbols

  1 device FET, 10 resonance matching circuit, 20 harmonic processing circuit, 2 output processing circuit, 65 conductive plate, 62 wire, 60 conductor (wiring pattern), 68 insulating substrate, 70, 71, 72, 73 conductor, 80 , 81, 82, 83 Conductive line (microstrip line), 84, 85, 86 Chip capacitor, 92 Conductor pattern, 100 Conductive pattern, 101, 103, 105, 106 Conductive line, 102, 104, 109 Floating conductor, 107 Conductor (Wiring pattern), 110, 111, 112 chip capacitor, 203, 205, 215, 217, 219 wire, 200, 210, 212 MOS type chip capacitor, 204 conductor (wiring pattern).

Claims (16)

A transistor element that generates a signal corresponding to an input signal at an internal output node, and a matching process for the fundamental wave having a desired frequency and the fundamental wave connected between the internal output terminal and a load output terminal to which a load is coupled A semiconductor device comprising: an output processing circuit that forms a resonance state with respect to a harmonic having a frequency that is an integral multiple of the resonance frequency and adds a reactance component to the resonance state to perform attenuation processing with respect to the harmonic.   The semiconductor device according to claim 1, wherein the transistor element and the output processing circuit are disposed on a common insulating substrate.   The semiconductor device according to claim 1, wherein the harmonic is one of a second harmonic component and a third harmonic component of the fundamental wave. The output processing circuit includes:
A first inductor and a first capacitor connected in series between the internal output node and the load output node, and the internal output node and the load in parallel with the first inductor and the first capacitor A harmonic processing circuit including a second inductor connected between the output node and a third inductor and a second capacitor connected in series between the load output node and a ground line; The semiconductor device according to claim 1. The output processing circuit includes:
A first capacitor connected between the internal output node and the load output node; and a first inductor connected between the internal output node and the load output node in parallel with the first capacitor. 2. The semiconductor device according to claim 1, further comprising: a harmonic processing circuit including a second capacitor connected between the load output node and a ground line.   The semiconductor device according to claim 5, wherein the harmonic processing circuit further includes a second inductor connected in series with the first capacitor and in parallel with the first inductor.   The semiconductor device according to claim 5, wherein the harmonic processing circuit further includes a second inductor connected in series with the second capacitor to form a series resonance circuit with the second capacitor. The transistor element has a resistance component as an output impedance at the internal output node and a reactance component having a significant magnitude with respect to the resistance component,
The semiconductor device according to claim 4, wherein the output processing circuit further includes a resonance capacitor and a resonance inductor connected in series between the internal output node and a ground line.   The semiconductor device according to claim 8, wherein the output processing circuit further includes an inductor connected in series to the harmonic processing circuit between the internal output node and the harmonic processing circuit.   The harmonic processing circuit realizes the harmonic attenuation processing in a state in which a phase of a reflection coefficient is shifted from an ideal resonance state for the harmonic while maintaining matching with the fundamental wave. Semiconductor device. The transistor element has an output region;
The internal output node includes a conductor that is disposed to face the output area and has substantially the same width as the output area, and a plurality of wirings that connect the conductor and the output area. The semiconductor device described. A transistor having a conductive output region,
A first conductor disposed opposite the output region;
A plurality of wirings connecting the first conductor and the output region;
A first transmission line connected to the first conductor and arranged in a U-shape;
A plurality of second conductors surrounded by the first transmission line and separated from each other;
A second transmission line connected to the first conductor and arranged in a meandering shape;
A first capacitor connected between the second transmission line and a ground line;
A second capacitor having one electrode connected to the first conductor and the first transmission line;
A third transmission line having one end connected to the other electrode of the second capacitor and the other end connected to the first transmission line and arranged in a U-shape;
A plurality of third conductors arranged separately from each other in the inner region of the third transmission line;
A fourth transmission line having one end connected to a common coupling end of the first and third transmission lines and arranged in a meandering shape;
A plurality of fourth conductors arranged separately from each other in a region surrounded by the meandering shape of the fourth transmission line;
A semiconductor device comprising: a third capacitor connected between the fourth transmission line and a ground line. A transistor having a conductive output region,
A first conductor disposed opposite the output region;
A plurality of wirings connecting the first conductor and the output region;
A first transmission line connected to the first conductor and arranged in a U-shape;
A plurality of second conductors surrounded by the first transmission line and separated from each other;
A second transmission line connected to the first conductor and arranged in a serpentine shape;
A first capacitor connected between the second transmission line and a ground line;
A second capacitor coupled between one end and the other end of the U-shape of the first transmission line; and a second capacitor connected between the other end of the first transmission line and a ground line. A semiconductor device comprising three capacitors. A transistor having a conductive output region,
A first conductor disposed opposite the output region;
A plurality of wirings connecting the first conductor and the output region;
A first transmission line having one end connected to the first conductor and arranged in a U-shape;
A plurality of second conductors surrounded by the first transmission line and separated from each other;
A second transmission line connected to the first conductor and arranged in a meandering shape;
A first capacitor connected between the second transmission line and a ground line;
A second capacitor having one electrode connected to one end of the first transmission line;
One end is connected to the other electrode of the second capacitor and the other end is connected to the first transmission line. Transmission lines,
A plurality of third conductors disposed so as to be surrounded by the third transmission path and separated from each other; and a first conductor and a third conductor disposed in a region between the first and third transmission lines. A semiconductor device comprising a third capacitor connected between the common coupling end of the transmission line and the ground line. A transistor having a conductive output region,
A first conductor disposed opposite the output region;
A plurality of wirings connecting the first conductor and the output region;
A first transmission line having one end connected to the first conductor and arranged in a U-shape;
A plurality of second conductors surrounded by the first transmission line and separated from each other;
A second transmission line connected to the first conductor and arranged in a serpentine shape;
A first capacitor connected between the second transmission line and a ground line;
A second capacitor coupled between one end and the other end of the U-shape of the first transmission line;
A third transmission line having one end connected to the other end of the first transmission line and arranged in a meandering shape;
A plurality of third conductors arranged corresponding to the meandering shape of the third transmission line; and a third capacitor connected between the other end of the third transmission line and a ground line. Semiconductor device. A transistor having a conductive output region,
A first capacitor disposed opposite the output region and having one electrode connected to a ground line;
A plurality of first wires connecting the output region and the other electrode of the first capacitor;
A second conductor disposed opposite the output region with respect to the first capacitor;
A plurality of second wirings connecting the second conductor and the output region;
A third conductor disposed away from the second conductor;
A second capacitor having one electrode connected to the third conductor;
A plurality of third wires connecting the other electrode of the second capacitor and the second conductor;
A plurality of fourth wirings connecting the second conductor and the third conductor;
A third and a fourth capacitor, arranged opposite to each other with respect to the third conductor, each having one electrode connected to a ground line;
A plurality of fifth wires connecting the other electrode of the third capacitor to the third conductor;
A semiconductor device comprising a plurality of sixth wirings connecting the other electrode of the fourth capacitor to the third conductor.

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