JP2005302943A5 - - Google Patents
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- Publication number
- JP2005302943A5 JP2005302943A5 JP2004115497A JP2004115497A JP2005302943A5 JP 2005302943 A5 JP2005302943 A5 JP 2005302943A5 JP 2004115497 A JP2004115497 A JP 2004115497A JP 2004115497 A JP2004115497 A JP 2004115497A JP 2005302943 A5 JP2005302943 A5 JP 2005302943A5
- Authority
- JP
- Japan
- Prior art keywords
- metal foil
- main surface
- wiring board
- laminate
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Claims (5)
第一主表面及び第二主表面が誘電体層にて形成されるように、2以上の誘電体層と2以上の導体層とが交互に積層された積層体と、
前記第一主表面及び前記第二主表面上に形成される複数の金属端子パッドと、
前記積層体を補強して平坦度を確保する補強枠と、
を有し、前記半導体チップ及び前記補強枠は前記第一主表面に配置され、
前記金属端子パッドの少なくとも一部のものが、前記積層体内に位置する内部導体層にビアを介して導通するとともに、
前記金属端子パッドと前記半導体チップとが半田接続部を介してフリップチップ接続され、
前記誘電体層のヤング率が0.01GPa以上0.3GPa以下であることを特徴とする配線基板。 A wiring board that does not have a core board and connects a semiconductor chip,
A laminate in which two or more dielectric layers and two or more conductor layers are alternately laminated so that the first main surface and the second main surface are formed of a dielectric layer;
A plurality of metal terminal pads formed on the first main surface and the second main surface;
A reinforcing frame that reinforces the laminate and ensures flatness;
The semiconductor chip and the reinforcing frame are disposed on the first main surface,
At least a part of the metal terminal pad is electrically connected to an internal conductor layer located in the multilayer body through a via,
The metal terminal pad and the semiconductor chip are flip-chip connected via a solder connection portion,
A wiring substrate, wherein the dielectric layer has a Young's modulus of 0.01 GPa to 0.3 GPa.
支持基盤を用意する工程と、 A process of preparing a support base;
互いに密着し、かつ、分離可能な金属箔を含む金属箔密着体を用意する工程と、 A step of preparing a metal foil adhesion body including metal foils that are in close contact with each other and separable;
前記支持基盤の上部に前記金属箔密着体を配置する工程と、 Placing the metal foil adhesion body on top of the support base;
前記金属箔密着体を介して前記支持基盤の上部に配置され、ヤング率が0.01GPa以上0.3GPa以下である前記誘電体層と、前記誘電体層に設けられたビア導体と、前記誘電体層上に配置されると共に前記ビア導体を介して前記金属箔密着体と接続する前記導体層と、を含む積層体を形成する工程と、 The dielectric layer disposed on the support base via the metal foil adhesion body and having a Young's modulus of 0.01 GPa or more and 0.3 GPa or less, a via conductor provided in the dielectric layer, and the dielectric Forming a laminate including the conductor layer disposed on the body layer and connected to the metal foil adhesion body via the via conductor;
前記金属箔密着体に含まれる金属箔を界面にて剥離して、前記積層体における前記金属箔密着体上の領域を前記金属箔が付着した状態で前記支持基盤から分離する工程と、 Separating the metal foil contained in the metal foil adhesion body at the interface, and separating the region on the metal foil adhesion body in the laminate from the support base in a state where the metal foil is attached;
前記積層体に補強枠を接着する工程と、 Adhering a reinforcing frame to the laminate;
を備える、配線基板の製造方法。 A method for manufacturing a wiring board, comprising:
前記積層体の周囲部を除去して前記金属箔密着体の端部を露出させる工程を備える、配線基板の製造方法。 A method for manufacturing a wiring board, comprising: removing a peripheral portion of the laminate to expose an end portion of the metal foil adhesion body.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004115497A JP4336605B2 (en) | 2004-04-09 | 2004-04-09 | Wiring board manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004115497A JP4336605B2 (en) | 2004-04-09 | 2004-04-09 | Wiring board manufacturing method |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005302943A JP2005302943A (en) | 2005-10-27 |
JP2005302943A5 true JP2005302943A5 (en) | 2008-11-06 |
JP4336605B2 JP4336605B2 (en) | 2009-09-30 |
Family
ID=35334095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004115497A Expired - Fee Related JP4336605B2 (en) | 2004-04-09 | 2004-04-09 | Wiring board manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4336605B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5192870B2 (en) * | 2008-03-26 | 2013-05-08 | 古河電気工業株式会社 | Metal core multilayer printed wiring board |
TW201947722A (en) * | 2018-05-07 | 2019-12-16 | 恆勁科技股份有限公司 | Flip-chip package substrate |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3635219B2 (en) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | Multilayer substrate for semiconductor device and manufacturing method thereof |
JP3969886B2 (en) * | 1999-03-19 | 2007-09-05 | 株式会社カネカ | Method and system for calculating dimensional change rate of multilayer bonding sheet |
JP3213291B2 (en) * | 1999-06-29 | 2001-10-02 | ソニーケミカル株式会社 | Multilayer substrate and semiconductor device |
JP3838232B2 (en) * | 2000-06-30 | 2006-10-25 | 日本電気株式会社 | Semiconductor package substrate manufacturing method and semiconductor device manufacturing method |
JP3983146B2 (en) * | 2002-09-17 | 2007-09-26 | Necエレクトロニクス株式会社 | Manufacturing method of multilayer wiring board |
-
2004
- 2004-04-09 JP JP2004115497A patent/JP4336605B2/en not_active Expired - Fee Related
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