JP2005302943A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board that has no core substrate and can be reduced in warping. <P>SOLUTION: The wiring board 1, which connects semiconductor chips to each other, has a laminate BU formed by alternatively laminating two or more dielectric layers and two or more conductor layers upon another so that the first and second main surfaces MP1 and MP2 of the laminate BU may be formed of dielectric layers, a plurality of metallic terminal pads PD1 and PD2 formed on the first and second main surfaces MP1 and MP2, and a reinforcing frame ST which secures flatness by reinforcing the laminate BU. The semiconductor chips and reinforcing frame ST are arranged on the first main surface and at least part of the metallic terminal pads PD1 and PD2 are electrically connected to internal conductor layers positioned in the laminate BU through via holes. At the same time, the metallic terminal pads PD1 and PD2 and semiconductor chips are flip-chip connected to each other through soldered connections and the Young's modulus of the dielectric layers is adjusted to 0.01GPa-0.3 GPa. Since the Young's modulus of the dielectric layers is low, the thermal stress caused by the difference between the coefficients of thermal expansion of the dielectric layers and conductor layers can be absorbed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wiring board.

  In recent years, due to the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration has rapidly progressed in electronic components such as IC chips and LSIs. There is a demand for higher-density wiring and multi-terminals than ever before.

  As such a package substrate, a build-up multilayer wiring substrate is currently used. The build-up multilayer wiring board uses the rigid property of an insulating core substrate (glass epoxy substrate such as FR-4) in which a reinforcing fiber is impregnated with a resin, and a dielectric layer and a conductor are formed on both main surfaces thereof. A build-up layer (hereinafter also referred to as a laminate) in which layers are alternately arranged is formed. In such a build-up multilayer wiring board, high-density wiring is realized in the laminate, while the core board plays a reinforcing role. Therefore, the core substrate is configured to be very thick compared to the multilayer body, and wiring (for example, referred to as a through-hole conductor) for establishing electrical connection between the multilayer bodies disposed on the respective main surfaces is provided in the core substrate. It is formed penetrating in the thickness direction. However, at the present time when the signal frequency to be used has become a high frequency band exceeding 1 GHz, there is a problem that the wiring penetrating such a thick core substrate contributes as a large inductance.

Therefore, in order to solve such a problem, there has been proposed a wiring board mainly composed of a laminate that does not have a core board and can be formed with high density wiring, as shown in Patent Document 1 below. In such a wiring board, since the core board is omitted, the entire wiring length is short, which is suitable for high-frequency applications. In order to manufacture such a wiring board, as described in paragraphs 0012 to 0029 and FIGS. 1 to 4 of Patent Document 1 below, a laminate is formed on the metal plate, and then the metal plate is etched. By doing so, only a thin film laminate is obtained. And this laminated body is used as a wiring board.
JP 2002-26171 A

  In the thin film laminate separated from the metal plate, a reinforcing frame (hereinafter also referred to as a stiffener) for securing the rigid property of the wiring board is installed on the IC connection side. Copper alloy or SUS304 is used as the material of the reinforcing frame, and epoxy resin is used as the dielectric layer. When connecting the reinforcing frame to the laminate, an adhesive is used, and vacuum curing is performed at about 150 ° C. in order to solidify the adhesive. The thermal expansion coefficient of the copper alloy used for the reinforcing frame is about 17.7 ppm / ° C. The dielectric layer is mainly composed of an epoxy resin, and its thermal expansion coefficient is about 55 ppm / ° C. In the conventional wiring board, there is a problem that the wiring board is warped due to the difference in the coefficient of thermal expansion. That is, when the vacuum curing is completed and the cooling is performed, the reinforcing frame is contracted only slightly, but the wiring board including the dielectric layer is greatly contracted, so that it has an arcuate shape as shown in FIG.

  On the other hand, there is also a warp caused by a difference in wiring density of the conductor layer. The conductor layer has a different wiring density depending on the layer. For example, a conductor layer constituting a metal terminal pad to be connected to a semiconductor chip has a low wiring density, and a conductor layer constituting a metal terminal pad on the mother board connection side has a high wiring density. This is because the metal terminal pads on the semiconductor chip connection side are generally made small. When a copper alloy is used as the conductor layer, the coefficient of thermal expansion is about 17.7 ppm / ° C., and the dielectric layer mainly composed of epoxy resin is about 55 ppm / ° C. Therefore, a difference in thermal expansion coefficient occurs between the surface on the semiconductor chip connection side where the wiring density is low and the surface on the motherboard connection side where the wiring density is high, causing warpage. Since a high temperature of about 170 ° C. is applied in the build-up process, stress is applied to the cooled wiring board after the build-up process is completed, and warping occurs. Since the metal terminal pad for connecting the semiconductor chip is disposed in the central portion of the wiring board, it is deformed so that the central portion is recessed as shown in FIG.

  The present invention has been made in the background as described above, and includes a laminated body in which conductor layers and dielectric layers are alternately laminated, a reinforcing frame that reinforces the laminated body to ensure flatness, It is an object to provide a wiring board that can be reduced.

Means for Solving the Problems and Effects of the Invention

  In order to solve the above problems, the wiring board of the present invention is a wiring board that does not have a core board and connects conductor chips, and the first main surface and the second main surface are formed of a dielectric layer. As described above, a laminate in which two or more dielectric layers and two or more conductor layers are alternately laminated, a plurality of metal terminal pads formed on the first main surface and the second main surface, and a laminate An internal conductor layer in which the semiconductor chip and the reinforcing frame are disposed on the first main surface, and at least a part of the metal terminal pads are located in the multilayer body. The metal terminal pad and the semiconductor chip are flip-chip connected via the solder connection portion, and the Young's modulus of the dielectric layer is 0.01 GPa or more and 0.3 GPa or less. And

  In the present invention, a wiring board with less warpage is provided by using a polymer material having a low Young's modulus for the dielectric layer. Specifically, the Young's modulus of the dielectric layer is set to 0.01 GPa or more and 0.3 GPa or less. Even if a stress is applied to the laminate due to the difference in thermal expansion coefficient between the reinforcing frame and the dielectric layer, the dielectric layer itself is deformed, so that the stress can be relaxed and the warpage of the laminate can be reduced. If the Young's modulus is 0.3 GPa or more, the dielectric layer is not easily deformed, and the stress may not be sufficiently relaxed. Further, if the Young's modulus is 0.01 GPa or less, it is too soft to be suitably used for a wiring board. Examples of the material having a Young's modulus of 0.01 GPa or more and 0.3 GPa or less include ABF-LE CodeT3 (trade name: manufactured by Ajinomoto Fine Techno Co., Ltd.).

  When the Young's modulus of the dielectric layer is set within the above range, and a material having a small thermal expansion coefficient is used for the conductor layer, warpage can be further reduced. Specifically, the Young's modulus of the dielectric layer is preferably 0.01 GPa or more and 0.3 GPa or less, and the thermal expansion coefficients of all the conductor layers are 15 ppm / ° C. or more and 25 ppm / ° C. or less. Further, the warp can be further reduced by reducing the difference in the wiring density of the conductor layer. Specifically, the wiring density of the conductor layer closest to the main surface on the semiconductor chip connection side is set to 50% to 90% and the wiring density of the conductor layer closest to the main surface on the motherboard connection side is set to 50% to 90%. % Or less. In this way, the difference in wiring density between the conductor layers is 40% or less, and the warpage can be reduced.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
Fig.1 (a) is a schematic sectional drawing which shows one Embodiment of this invention. Dielectric layers and conductor layers are alternately stacked to form a stacked body BU. On the first main surface MP1, a protruding metal terminal (solder bump) FB made of a well-known solder for connecting to the semiconductor chip is formed. Further, a reinforcing frame (stiffener) ST for reinforcing the wiring substrate 100 and ensuring flatness is bonded to the first main surface MP1. Since the wiring board of the present invention does not have a core board, it is easy to bend unless a reinforcing frame is used, and it becomes difficult to connect the solder bump FB and the semiconductor chip.

  Next, it will be described in more detail with reference to FIG. FIG.1 (b) is principal part sectional drawing of the wiring board of this invention. The laminate 100 is formed by alternately laminating conductor layers M1 to M4 and dielectric layers B1 to B4. A solder resist SR is formed on the surface of the dielectric layer B4. The conductor layers M1 to M4 are mainly composed of copper. A plurality of metal terminal pads PD1 are formed on the first main surface MP1. The metal terminal pad PD1 constitutes a solder land that is a pad for flip-chip connection of a semiconductor chip or the like. The metal terminal pad PD2 on the second main surface MP2 side is used as a back surface land for connecting the wiring board itself to the mother board by a pin grid array (PGA) or a ball grid array (BGA). On the other hand, the conductor layers M1 and M2 are interconnected by a via V1. Similarly, the conductor layers M2 and M3 are interconnected by a via V2, and the conductor layers M3 and M4 are interconnected by a via V3. In this manner, an electrical conduction path from the solder bump FB to the metal terminal pad PD2 is formed.

  Compared with the semiconductor chip and the metal terminal pad PD1 for connection, the metal terminal pad PD2 for motherboard connection is made larger. Therefore, the wiring density of the conductor layer M1 is low, and the wiring density of the conductor layer M4 is high. As described above, this difference in wiring density causes a warp.

  As shown in FIG. 2 (a), the metal terminal pads PD1 are arranged in a lattice shape at a substantially central portion of the wiring board 1, and the chip mounting portions 40 are formed together with the solder bumps FB formed thereon. In addition, as shown in FIG. 2B, the metal terminal pads PD2 are also arranged in a grid pattern.

  The laminated body BU described above can be manufactured, for example, by stacking and forming a metal substrate using a known build-up method, and removing the metal plate by etching. FIG. 3 is a conceptual cross-sectional view showing the occurrence of warping when a reinforcing frame is bonded. As shown to Fig.3 (a), the reinforcement frame ST for ensuring flatness is adhere | attached on the 1st main surface MP1 side of laminated body BU. Adhesion of the reinforcing frame ST is performed using an adhesive, but curing (for example, about 150 ° C.) is performed to solidify the adhesive. When this process is completed and the cooling is performed, as shown in FIG. 3B, shrinkage stress of the reinforcing frame and the laminate is generated. Since each coefficient of thermal expansion is different, the shrinkage stress of the reinforcing frame ST is small, and the shrinkage stress of the laminated body BU is large. Therefore, when the cooling is completed, as shown in FIG. However, if a dielectric material B1 to B4 has a low Young's modulus and a polymer material of 0.01 GPa or more and 0.3 GPa or less is used, the laminate BU itself is deformed as shown in FIG. Can be reduced and warpage can be reduced.

  FIG. 4 is a schematic cross-sectional view showing the occurrence of warpage due to the wiring density between conductor layers. FIG. 4A shows a cross-sectional view of the process of laminating the laminated body BU on the metal plate. During the build-up process, for example, a high temperature state of about 170 ° C. is reached. When the laminate is cooled to room temperature, as shown in FIG. 4B, a contraction stress on the first main surface MP1 side and a contraction stress on the second main surface MP2 side are generated. The shrinkage stress on the MP1 side is large, and the shrinkage stress on the MP2 side is small. The conductor layer M1 that forms the metal terminal pad PD1 and the conductor layer M2 that forms the metal terminal pad PD2 have different wiring densities because of their different wiring densities. Since the metal terminal pads M1 are arranged in the central portion of the wiring board, contraction stress is particularly likely to occur in the central portion. When the metal plate is etched, as shown in FIG. 4C, the central portion of the laminate is deformed into a concave shape. However, if a polymer material of 0.01 GPa or more and 0.3 GPa or less is used for the dielectric layers B1 to B4, such warpage is reduced, and a substantially flat laminated body BU is obtained. In addition, it is desirable that the thermal expansion coefficient of the conductor layer is 15 ppm / ° C. or more and 25 ppm or less. Further, the wiring density of the conductor layer M1 closest to the first main surface is set to 50% or more and 90% or less, and the wiring density of the conductor layer M4 closest to the second main surface is set to 50% or more and 90% or less. More preferably, the difference in wiring density between the conductor layers M1 and M4 is 40% or less.

  As shown in FIG. 4, after the laminated body BU is laminated on the metal plate, the method of removing the metal plate by etching requires the metal plate to maintain its strength as a support base. It needs to be about. In this case, a relatively long time of about 30 minutes is required to remove the metal plate by etching. Such a problem can be solved by the following manufacturing method. 5 and 6 show a method for manufacturing a wiring board according to the present invention. This manufacturing method is characterized in that it uses a metal foil contact body in which metal foils M1 and M1 'are in close contact. In step 1, the laminated body BU is formed on the base dielectric sheet 21 formed on the support substrate 20. Here, a polymer material having a Young's modulus of 0.01 GPa or more and 0.3 GPa or less is used for the dielectric layer. Further, a metal foil adhesion body is disposed so as to be included in the main surface of the base dielectric sheet 21, and a first dielectric layer B2 is disposed so as to wrap the metal foil adhesion body. And dielectric material layer B2-B4 and conductor layer M2-M4 are laminated | stacked on the metal foil adhesion body using the well-known buildup process. Next, the peripheral part (broken line part in the figure) of the laminated body BU is removed, and the end surface 101 of the laminated body is exposed (step 2). Then, the laminated body BU is separated from the support base 20 and the base dielectric sheet by peeling off the metal foil adhesion body (step 3). Next, the metal foil M1 attached to the laminated body BU side is patterned and etched to form the metal terminal pad PD1 on the semiconductor chip connection side (step 4). That is, the metal foil M1 is used as a conductor layer for constituting the metal terminal pad PD1. Thereafter, the dielectric layer B1 is laminated on the metal terminal pad PD1 side and selectively etched so that the metal pad PD1 is opened. When the reinforcing frame is bonded to the semiconductor chip connection side (the side with PD1) of the stacked body BU formed in this way, the wiring substrate 1 shown in FIGS. 1A and 1B is formed. According to the above method, since it is not necessary to etch the metal plate, the process time can be shortened. Further, since a material having a relatively low Young's modulus is used for the dielectric layers B1 to B4, warpage can be reduced.

  In order to confirm the effect of the present invention, the following experiment was conducted. First, a thin film stack BU having the structure of FIG. 1B was obtained using the above-described manufacturing method. In Examples belonging to the present invention, ABF-LE CodeT3 (trade name: manufactured by Ajinomoto Fine Techno Co., Ltd.) having a Young's modulus of 0.025 GPa and a thermal expansion coefficient of 132 ppm / ° C. was used as the dielectric layers B1 to B4. On the other hand, a sample as a comparative example outside the present invention includes ABF-GX Code 3 (trade name) mainly composed of an epoxy resin having a Young's modulus of 2.4 GPa and a thermal expansion coefficient of 55 ppm / ° C. in the dielectric layers B1 to B4. : Ajinomoto Fine Techno Co., Ltd.) was used. Thereafter, the reinforcing frame ST was bonded at 150 ° C. to the first main surfaces of the examples and comparative examples. In each sample, a copper alloy having a thermal expansion coefficient of 17.7 ppm / ° C. was used as a material for the conductor layers M1 to M4 and the reinforcing frame ST.

  After creating the sample, the amount of warpage was measured. The result is shown in FIG. The example (ABF-LE CodeT3) belonging to the present invention had an average warpage of 49 μm, and the comparative example (ABF-GX Code3) outside the present invention had an average warpage of 128 μm. From this result, it was confirmed that the warpage can be reduced in the example.

BRIEF DESCRIPTION OF THE DRAWINGS (a) sectional drawing and (b) principal part sectional drawing which show one Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS (a) Front view and (b) Back view which show one Embodiment of this invention. Sectional drawing which shows curvature generation | occurrence | production when the reinforcement frame was adhere | attached. Sectional drawing which shows generation | occurrence | production of the curvature resulting from the wiring density between conductor layers. Process drawing which shows an example of the manufacturing method of a wiring board. Process drawing following FIG. The graph which shows the relationship between a dielectric material layer and curvature.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board 20 Support base 21 Base dielectric layer BU Laminate MP1 1st main surface MP2 2nd main surface M1 1st conductor layer (metal foil)
B1 First dielectric layer PD1 Metal terminal pad ST Reinforcement frame FB Solder bump

Claims (3)

A wiring board that does not have a core board and connects a semiconductor chip,
A laminate in which two or more dielectric layers and two or more conductor layers are alternately laminated so that the first main surface and the second main surface are formed of a dielectric layer;
A plurality of metal terminal pads formed on the first main surface and the second main surface;
A reinforcing frame that reinforces the laminate and ensures flatness;
The semiconductor chip and the reinforcing frame are disposed on the first main surface,
At least a part of the metal terminal pad is electrically connected to an internal conductor layer located in the multilayer body through a via,
The metal terminal pad and the semiconductor chip are flip-chip connected via a solder connection portion,
A wiring substrate, wherein the dielectric layer has a Young's modulus of 0.01 GPa to 0.3 GPa. The wiring board according to claim 1, wherein the thermal expansion coefficient of all the conductor layers is 15 ppm / ° C. or more and 25 ppm / ° C. or less. The wiring density of the conductor layer closest to the first main surface is 50% to 90%, and the wiring density of the conductor layer closest to the second main surface is 50% to 90%. Or the wiring board of Claim 2.

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