JP2005286831A - Apparatus and method for measuring error - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an error measuring apparatus and an error measuring method capable of measuring the condition of an error generated when serial transmission is performed, by assigning minimum terminals to two integrated circuits, when the serial transmission is performed with a transmission line arranged between these two integrated circuits. <P>SOLUTION: A transmitting circuit portion 207 transmits predetermined data to a receiving circuit portion 209 via the transmission line of a measuring object. The error detection portion 218 of the receiving portion 209 compares received data with a receiving-side reference signal 236 generated by a receiving-side reference signal generation portion 217, and inputs an error signal 237 into an error counter circuit 219 each time a transmission error is detected. The counter circuit 219 counts inputted error signals 237 based on a transmission error clock signal 224 when it is in a count-up mode, stops counting when it is in a shift mode, and outputs a counted quantity of generation of transmission errors by the shape of a serial shift-out signal 226, along with an input start of a shift clock 227. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an error measuring apparatus and an error measuring method for measuring the state of a transmission error with respect to a transmission line arranged between a plurality of integrated circuits, and in particular, converts a parallel signal into a serial signal and transmits the transmission line. The present invention relates to an error measuring apparatus and an error measuring method for measuring a serial transmission circuit.

  The processing speed inside LSI (Large Scale Integrated Circuits) is rapidly increasing. On the other hand, the processing of the input / output circuit for connecting a plurality of LSIs is not so fast. For this reason, if parallel signals in an LSI are transmitted as they are to other LSIs to increase the speed of the LSI by increasing the number of transmission lines, both LSIs lack input / output terminals. Such a situation may occur.

  Therefore, instead of transmitting the parallel signal as it is, the parallel signal is converted into a serial signal, and if necessary, the serial signal is also made into a plurality of systems, so that relatively few input / output terminals are used as a whole. It has been proposed to enable faster transmission. Here, regarding the transmission of the serial signal, the level of the signal to be transmitted is related to the error rate as the error occurrence rate. Therefore, when transmitting a serial signal, it is proposed as a first proposal to first adjust the data transmission level (see, for example, Patent Document 1).

  In this first proposal, the transmission level is adjusted when a serial signal is transmitted, and the influence of impedance is reduced even when the transmission line is long. In the first proposal, when the bit error rate of the serial signal cannot be improved by this adjustment, the clock frequency when data is transferred serially is adjusted.

  There is also a proposal of a circuit for measuring an error rate for setting an appropriate bit rate when transmitting a parallel signal (see, for example, Patent Document 2). In the example of the second proposal, a 51.84 Mb / s (megabit / second) signal is subjected to serial-parallel conversion or parallel-serial conversion on the input side or output side of the modem (modem) because of its feasibility. Information is transmitted at a lower frequency. Further, the error rate is measured so that the signal transmission level and transmission frequency can be changed according to the condition of the transmission path.

By the way, when data is transmitted using a serial transmission circuit, there is a problem that restrictions on data transmission / reception timing are severe. Therefore, in order to save time and effort for circuit design by intervening in such timing control, a circuit portion and circuit arrangement for serial transmission are referred to as a serial transmission macro circuit or a macro block (hereinafter referred to as a serial transmission macro block). .), And these are often used as known parts. Then, a method of confirming whether or not a circuit device using a serial transmission macroblock has an error rate lower than or equal to that allowed for serial transmission is confirmed by measuring an error rate or an error occurrence state as in the second proposal. Is generally adopted.
Japanese Unexamined Patent Publication No. 2002-223204 (paragraph 0006, FIG. 1) JP-A-5-336078 (paragraph 0004)

  When signals are transmitted between LSIs or generally between integrated circuits, the transmission frequency for that is usually fixed to a predetermined frequency used in both integrated circuits. Therefore, when the transmission frequency is fixed to a predetermined frequency, it is necessary to determine whether or not signal transmission within an error rate allowed between the integrated circuits actually used is possible. In other words, when considering the case where a plurality of integrated circuits are actually mounted on a printed circuit board, the length of the transmission line connecting the integrated circuits due to the necessity of bypassing other components is the serial transmission macroblock specification. May be extended to the indicated tolerance limit. In such a case, whether or not the serial transmission macroblock is within an allowable error rate can only be confirmed by actually measuring the error rate with an error measurement device. Further, in order to judge whether the characteristics of the integrated circuit are good or bad, it is necessary to measure an actual circuit device with an error measuring device.

  If the error rate is measured with an actual circuit device in which integrated circuits are connected by a transmission line due to such necessity, it is necessary to provide a dedicated terminal for the measurement in the integrated circuit for each part where the error is measured. Generally considered difficult. The reason why the transmission lines between the integrated circuits are serial transmission is to reduce the total number of terminals for the transmission lines connecting these integrated circuits as much as possible. Therefore, it is difficult to provide a large number of dedicated terminals for measuring error states or error rates at a plurality of locations in an integrated circuit such as a large-scale integrated circuit.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to enable measurement of error conditions during serial transmission by assigning a minimum number of terminals to these integrated circuits when serial transmission is performed on a transmission line disposed between the two integrated circuits. The present invention relates to an error measurement apparatus and an error measurement method.

  According to the first aspect of the present invention, (a) parallel data output means for outputting arbitrary parallel data, and test data for outputting parallel data having the same bit configuration as the parallel data at the time of a test for measuring an error as test data Select output means, parallel serial conversion means for converting parallel data to serial data, and parallel data output by test data output means during testing, otherwise select parallel data output by parallel data output means and select parallel data A first integrated circuit comprising: parallel data selection means to be supplied to the serial conversion means; and serial data sending means for sending the serial data converted by the parallel-serial conversion means to a predetermined transmission line; Convert serial data transmitted through the transmission path to parallel data An error generated in the serial data by comparing the parallel data converted by the serial parallel conversion means at the time of the test with the same parallel data as the test data output by the test data output means Error detection means for detecting the error, error storage means for storing the error detected by the error detection means over a predetermined period, and error serial for outputting the storage contents of the error storage means in synchronization with a predetermined read signal And an error measuring device including a second integrated circuit including an output unit.

  That is, in the first aspect of the present invention, the error measuring device is composed of a first integrated circuit such as an LSI and a second integrated circuit in which a predetermined transmission path to be an error measurement target is arranged. . The first integrated circuit is provided with parallel-serial conversion means for converting parallel data into serial data, but the parallel data output from the parallel data output means is converted into parallel-serial conversion means during normal times when error measurement is not performed. To be supplied. Further, during a test for measuring an error, test data having the same bit configuration as the parallel data output from the test data output means is supplied to the parallel-serial conversion means. The serial data after the conversion by the parallel-serial conversion means is sent to the predetermined transmission path. On the other hand, the second integrated circuit is provided with serial / parallel conversion means for converting serial data transmitted through the predetermined transmission path into parallel data. The error detecting means detects the error generated in the serial data by comparing the converted parallel data with the same parallel data as the test data output from the test data output means, and the error storage means detects the error. The error is stored for a predetermined period. The error serial output means outputs the stored contents serially in synchronization with a predetermined read signal. Thereby, an error when serial transmission is performed on a transmission line arranged between two integrated circuits can be detected inside the integrated circuit. Further, since the detected error is output serially from the integrated circuit, the error condition can be measured in a state where the increase in the number of terminals of the second integrated circuit is minimized.

  According to a second aspect of the present invention, in the error measuring apparatus according to the first aspect, the error storage means is means for storing a count value as the number of errors.

  That is, in the second aspect of the invention, the error storage means stores the count value as the number of errors detected in the predetermined period, so that the count value can be output from the second integrated circuit.

  According to a third aspect of the present invention, in the error measuring device according to the second aspect, the error serial output means converts the count value stored in the error storage means into a predetermined read signal that is output after the end of the predetermined period. It is a means for outputting serially in synchronization.

  That is, in the third aspect of the invention, the error serial output means serially outputs the count value in synchronization with a predetermined read signal, and the predetermined read signal is a predetermined value at which the error storage means counts errors. Output begins after the period ends. Thereby, since the count value is output at the timing when the output of the predetermined read signal is started, the count value can be more reliably detected externally.

  In the invention of claim 4, (a) parallel data output means for outputting arbitrary parallel data, and test data for outputting parallel data having the same bit configuration as the parallel data at the time of a test for measuring an error as test data Select output means, parallel serial conversion means for converting parallel data to serial data, and parallel data output by test data output means during testing, otherwise select parallel data output by parallel data output means and select parallel data A plurality of first integrated circuits comprising: parallel data selection means for supplying to the serial conversion means; and serial data sending means for sending the serial data converted by the parallel-serial conversion means to a predetermined transmission line; Provided corresponding to each of the plurality of first integrated circuits. The first integrated circuit corresponding to its own circuit converts the serial data transmitted through the predetermined transmission path for transmitting the serial data into parallel data, and is converted by the serial parallel conversion means during the test. Error detection for detecting an error occurring in the serial data by comparing the subsequent parallel data with the same parallel data as the test data output from the test data output means provided in the first integrated circuit corresponding to the circuit itself A plurality of second integrated circuits comprising means, (c) an error storage means for storing errors detected by the error detection means provided in the plurality of second integrated circuits over a predetermined period, and the error Error serial output means for serially outputting the stored contents of the storage means in synchronization with a predetermined read signal; And a third integrated circuit was example is provided in the error measuring device.

  That is, in the invention described in claim 4, a plurality of first integrated circuits and a plurality of second integrated circuits corresponding to each of the plurality of first integrated circuits are provided, and error measurement is performed on a plurality of transmission lines arranged between them. I do. The third integrated circuit includes error storage means for storing an error detected by the error detection means provided in each of the plurality of second integrated circuits over a predetermined period. The stored error is stored in the third integrated circuit. It is designed to output serially. That is, errors detected for a plurality of transmission paths can be stored together in one error storage means and can be serially output.

  In the invention according to claim 5, (a) parallel data output means for outputting arbitrary parallel data and test data for outputting parallel data having the same bit configuration as the parallel data at the time of a test for measuring an error as test data Select output means, parallel serial conversion means for converting parallel data to serial data, and parallel data output by test data output means during testing, otherwise select parallel data output by parallel data output means and select parallel data A plurality of first integrated circuits comprising: parallel data selection means for supplying to the serial conversion means; and serial data sending means for sending the serial data converted by the parallel-serial conversion means to a predetermined transmission line; Provided corresponding to each of the plurality of first integrated circuits. The first integrated circuit corresponding to its own circuit converts the serial data transmitted through the predetermined transmission path for transmitting the serial data into parallel data, and is converted by the serial parallel conversion means during the test. Error detection for detecting an error occurring in the serial data by comparing the subsequent parallel data with the same parallel data as the test data output from the test data output means provided in the first integrated circuit corresponding to the circuit itself A plurality of second integrated circuits comprising: means; and error storage means for storing a count value as the number of errors detected by the error detection means over a predetermined period; The error storage means is serially connected, and the output is started after a predetermined period. It is provided to the error measurement device and an error serial output means for outputting sequentially shifting the stored count value to these errors storage means in sync.

  That is, the invention according to claim 5 is provided with a plurality of first integrated circuits and a plurality of second integrated circuits corresponding to each of the plurality of first integrated circuits, and measuring errors in a plurality of transmission lines arranged therebetween. I do. The error serial output means is connected to the error storage means serial provided in each of the plurality of second integrated circuits, and sequentially shifts and outputs the count values stored in each of them. That is, the error count values for a plurality of transmission paths can be collectively output in a state in which the error count values detected on the respective transmission paths are known.

  According to a sixth aspect of the present invention, in the error measuring device according to any one of the first to fifth aspects, the first integrated circuit and the second integrated circuit are arranged on the same substrate, and on this substrate, A first transmitting means for transmitting the test time to the parallel data selecting means and the error detecting means; and a second transmitting a predetermined period for storing the error to the error storing means. And a third processing means for transmitting a predetermined read signal to the error serial output means. The test processing circuit is further arranged.

  That is, in the invention described in claim 6, the first integrated circuit, the second integrated circuit, and the test processing circuit for controlling the error measurement are arranged on the same substrate. In this test processing circuit, the test time is transmitted to the parallel data selection means and the error detection means, the error storage means is transmitted to the predetermined period for storing the error, and the predetermined read signal is output to the error serial. To the means.

  In the invention of claim 7, (a) a test-time serial data receiving step of receiving serial data sent from a specific integrated circuit through a transmission line from the start to the end of a test for measuring an error; (B) A serial / parallel conversion step for sequentially converting the serial data received in the serial data reception step at the time of testing into bit-parallel data to be measured for errors, and (c) after conversion in the serial / parallel conversion step. Error data determination step for sequentially comparing the parallel data with test parallel data prepared in advance to determine the presence or absence of an error, and (d) a counting step for counting the number of errors determined in the error presence determination step, (E) The count counted in the counting step when the above test is completed. Synchronization data representing the cement value to a predetermined read clock is provided an error serial output step of outputting the serially one bit error measuring method.

  That is, the seventh aspect of the invention expresses the same principle as the method of the first aspect of the invention as a method.

  As described above, according to the error measurement device of the present invention, an error when serial transmission is performed on a transmission line arranged between two integrated circuits can be detected inside the integrated circuit. Further, since the detected error is output serially from the integrated circuit, the error condition can be measured in a state where the increase in the number of terminals of the second integrated circuit is minimized.

  Hereinafter, the present invention will be described in detail with reference to examples.

  FIG. 1 shows a configuration of an error measuring apparatus according to an embodiment of the present invention. The error measurement device 201 transmits a transmission side LSI 202 as a data transmission side device, a reception side LSI 203 as a data reception side device, and data sent from the transmission side LSI 202 to the reception side LSI 203. A transmission path 204 is provided. Further, an error rate measuring unit 205 for measuring the error rate of data transmitted through the transmission path 204 is arranged in such a manner that the transmission side LSI 202 and the reception side LSI 203 are connected.

  The transmission-side LSI 202 is provided with a transmission-side logic circuit 206 for performing various arithmetic processing and a transmission circuit unit 207 for performing data transmission processing. The reception-side LSI 203 is provided with a reception-side logic circuit 208 for performing various arithmetic processing, a reception circuit unit 209 for performing data reception processing, and a PLL (Phase Lock Loop) circuit 211 that is a high-speed frequency oscillator. ing. The transmission circuit unit 207, the reception circuit unit 209, and the transmission path 204 are a serial transmission circuit 210 that transmits normal data from the transmission side logic circuit 206 to the reception side logic circuit 208. The transmission circuit unit 207 and the reception circuit unit 209 can further measure the error rate of the transmission path 204. The error rate measuring unit 205 includes an information processing device 212 that performs various types of information processing for measuring the error rate using the transmission circuit unit 207 and the reception circuit unit 209, and a shift that generates a clock signal having a predetermined frequency. A clock generator 213 is provided.

  In the transmission-side LSI 202, an n-bit parallel data input signal 221 to be transmitted is input from the transmission-side logic circuit 206 to the transmission circuit unit 207. Then, the signal is converted into the serial signal 222 by the transmission circuit unit 207 and input to the reception circuit unit 209 of the reception-side LSI 203 via the transmission path 204. In the reception-side LSI 203, the input serial signal 222 is converted by the reception circuit unit 209 to be restored to the original n-bit parallel data output signal 223, and input to the reception-side logic circuit 208. The PLL circuit 211 outputs a high-speed clock signal, and this clock signal is used when the receiving circuit unit 209 receives the serial signal 222. The PLL circuit 211 further outputs a transmission error clock signal 224 obtained by dividing the clock signal by n as a clock signal used when detecting a transmission error. The transmission error clock signal 224 is supplied to the reception circuit unit 209.

  A counter control signal 225 that rises during an error rate measurement period is input from the information processing device 212 of the error rate measuring unit 205 to the reception circuit unit 209 of the reception-side LSI 203. On the contrary, the shift-out signal 226 including the measurement result as information is input from the reception circuit unit 209 to the information processing device 212. Further, the shift clock signal 227 generated by the shift clock generator 213 of the error rate measuring unit 205 is also input to the reception circuit unit 209 of the reception-side LSI 203. Further, a test mode signal 228 for causing the transmission circuit unit 207 to output data serving as a reference for measuring the error rate as the serial signal 222 is input from the information processing device 212 to the transmission circuit unit 207. ing. Further, a generation start signal 229 for starting generation of the shift clock signal 227 is input from the information processing device 212 to the shift clock generator 213.

  The transmission-side LSI 202 and the reception-side LSI 203 and the transmission path 204 disposed between them are disposed on a printed circuit board (not shown). A connector (not shown) is provided on the printed board, and is connected to a connector (not shown) provided in the error rate measuring device 205. Each pin of these connectors corresponds to a test mode signal 228, a counter control signal 225, a shift clock signal 227, and a shift out signal 226, respectively. That is, the error rate measuring unit 205 is connected to the printed circuit board only when measuring the error rate, and functions as a part of the error measuring device 201.

  FIG. 2 shows a circuit configuration of the serial transmission circuit. The transmission circuit unit 207 of the serial transmission circuit 210 includes a parallel-serial conversion transmission circuit 214 that performs n-to-1 parallel-serial conversion, and a transmission-side reference signal 235 that is an n-bit parallel signal for measuring an error rate. The transmission side reference signal generation unit 215 is configured to generate. The reception circuit unit 209 of the serial transmission circuit 210 includes a serial / parallel conversion reception circuit 216 that performs 1-to-n serial / parallel conversion, and a reception-side reference signal that generates a reception-side reference signal 236 having the same pattern as the transmission-side reference signal 235. A generation unit 217 and an error detection unit 218 that detects a transmission error are provided. Further, an error counter circuit 219 that counts transmission errors and a synchronization that outputs the above-described counter control signal 225 to the transmission error clock signal 224 and outputs to the error counter circuit 219 as a synchronization switching signal 238 that instructs counting of transmission errors. A circuit 220 is provided.

  The parallel-serial conversion transmission circuit 214 switches between the parallel data input signal 221 output from the transmission-side logic circuit 206 in FIG. 1 and the transmission-side reference signal 235 output from the transmission-side reference signal generation unit 215. Is done. This switching is performed by the test mode signal 228 input to the parallel-serial conversion transmission circuit 214, and the transmission-side reference signal 235 is input while the test mode signal 228 indicating that the error rate is to be measured is rising. It has become so. While the test mode signal 228 falls, the parallel data input signal 221 is input. The parallel data input signal 221 or the transmission-side reference signal 235 input to the parallel-serial conversion transmission circuit 214 is converted into the serial signal 222, and the serial-parallel conversion reception circuit 216 of the reception circuit unit 209 via the transmission path 204 in FIG. Sent to. The transmission frequency of the serial signal 222 is based on a high-speed clock signal supplied from a PLL circuit (not shown) provided in the transmission side LSI 202 of FIG. 1, and this frequency is generated by the PLL circuit 211 of the reception side LSI 203. Corresponds to the clock signal. The parallel-serial conversion transmission circuit 214 further prevents the serial signal 222 from continuing the same level state for a long time and makes it easy to distinguish the control signal portion and the data signal portion of the serial signal 222, for example, a predetermined code such as 8B10B conversion. Conversion is to be performed.

  The transmission side reference signal generation unit 215 generates and outputs a transmission side reference signal 235 that is data having the same number of bits as the parallel data input signal 221 by a predetermined algorithm. The transmission side reference signal 235 is a pseudo random bit sequence (PRBS) signal, and repeats data frames having the same pattern at a predetermined cycle.

  The serial / parallel conversion reception circuit 216 of the reception circuit unit 209 receives the serial signal 222 from the parallel / serial conversion transmission circuit 214 of the transmission circuit unit 207. Then, based on the control signal included in the serial signal 222, the bit arrangement is reconfigured and decoded for the data signal included in the serial signal 222. As a result, the serial signal 222 is converted into a parallel data output signal 223 having the same bit arrangement as the parallel data input signal 221 input to the transmission circuit unit 207. This conversion process is performed based on a high-speed clock signal supplied from the PLL circuit 211 provided in the reception-side LSI 202 of FIG. In addition, the reception side reference signal generation unit 217 of the reception circuit unit 209 uses the same algorithm as that used by the transmission side reference signal generation unit 215 of the transmission circuit unit 207 to receive the reception side reference signal having the same pattern as the transmission side reference signal 235. A signal 236 is output.

  That is, when the transmission side reference signal 235 is input to the parallel-serial conversion transmission circuit 214, the parallel data output signal 223 is compared with the reception side reference signal 236, thereby generating a transmission error in the serial transmission circuit 210. Can be detected in bit units.

  The parallel data output signal 223 is input to the reception-side reference signal generation unit 217, and the transmission error clock signal 224 is supplied from the PLL circuit 211 in FIG. 1 as a reference clock signal when detecting a transmission error. . The parallel data output signal 223 is also input to the error detection unit 218. The reception-side reference signal generation unit 217 includes a frame detection circuit (not shown), reads the content of the control signal included in the parallel data output signal 223, and determines the start position of the data frame that is repeated at the predetermined period described above. To detect. Then, in synchronization with the transmission error clock signal 224, the error detection unit 218 can compare the parallel data output signal 223 with the same bit arrangement in accordance with the start position of the data frame of the detected parallel data output signal 223. The reception side reference signal 236 thus output is started. The error detection unit 218 compares the input reception-side reference signal 236 and the parallel data output signal 223 in bit units. An error signal 237 is output every time a different bit is detected. At this time, since the reception-side reference signal 236 is synchronized with the transmission error clock signal 224, the error signal 237 is also output in synchronization with the transmission error clock signal 224.

  The synchronization circuit 220 is supplied with a counter control signal 225 and is output as a synchronization switching signal 238 in synchronization with the transmission error clock signal 224 that is also supplied. The error counter circuit 219 receives the synchronization switching signal 238 and the error signal 237 output from the error detection unit 218, and is further supplied with a transmission error clock signal 224.

  The error counter circuit 219 counts the number of times the error signal 237 is input based on the transmission error clock signal 224 only during a period in which the synchronization switching signal 238 is rising (hereinafter, appropriately referred to as a count-up mode). . Then, the number of times the error signal 237 is counted during the count-up mode (hereinafter referred to as a transmission error occurrence amount) is held. Further, a shift clock signal 227 output from the error rate measuring unit 205 in FIG. 1 is input to the error counter circuit 219, and a transmission error occurrence amount is output as a shift-out signal 226 based on the shift clock signal 227. It has become. Also, a shift-in signal 239 for initializing the held transmission error occurrence value or setting it to a free value is supplied from a device unit (not shown) provided in the receiving LSI 203. .

FIG. 3 shows a specific circuit configuration of the error counter circuit. Error counter circuit 219, an adding circuit 241 for adding a transmission error amount, constituted by first to fourth D flip-flop circuits 242 _{1 to 242 4} holding respectively a transmission error occurrence amount that has been added to each digit Has been. Adding circuit 241 is constituted by the respective transmission error of one half adder for the addition performed for each digit (HA) 243 and the first to third full adder (FA) 244 ₁ ~244 ₃ , which correspond to the first to fourth D flip-flop circuits 242 _{1 to 242 4,} respectively. These first to fourth D flip-flop circuits 242 _{1 to 242 4} and the half adder 243 corresponding to these are between the first to third full adder 244 _{1-244 3,} the respective 1st to 4th switching circuits 245 _{1 to} 245 ₄ are arranged. Further, the fifth and the switching circuit 245 ₅ is provided, on its output side the input side of the first to fourth D flip-flop circuits 242 _{1 to 242 4} of the clock signal are commonly connected.

FIG. 4 shows a specific circuit configuration of the synchronization circuit. Synchronization circuit 220 is constituted by a D flip-flop circuit 242 ₆ the fifth D flip-flop circuit 242 ₅ 6. Each clock input terminal C, a transmission error the clock signal 224 is supplied to the data input terminal D of the fifth D flip-flop circuit 242 _5, the counter control signal 225 are supplied. The output terminal Q of the fifth D flip-flop circuit 242 ₅ is connected to the data input terminal D of the D flip-flop circuit 242 ₆ sixth. The synchronous switching signal 238 is output from the output terminal Q of the _sixth D flip-flop circuit 2426. Here, the D flip-flop circuit 242 ₅ of the fifth D flip-flop circuit 242 ₆ The sixth and to operate on the falling edge of the clock of the respective clock input terminal C, the fifth switch circuit 245 ₅ Make switching easier.

  With such a circuit configuration, when the counter control signal 225 rises, the synchronization switching signal 238 synchronized with the transmission error clock signal 224 rises correspondingly. This synchronization switching signal 238 is supplied to the error counter circuit 219 of FIG.

Returning to FIG. 3, the operation of the error counter circuit 219 will be described. The error signal 237 output from the error detection unit 218 in FIG. 2 is supplied to the input terminal B of the half adder 243 of the adder circuit 241. Further, the first to fourth switching circuits 245 _{1 to} 245 ₄ are supplied with the synchronization switching signal 238 output from the synchronization circuit 220 of FIG. 4, and the circuit connection is switched by the synchronization switching signal 238, respectively. While the synchronous switching signal 238 rises, the first to fourth D flip-flop circuits corresponding to the output terminals S of the half adder 243 and the first to third full adders 244 _{1 to} 244 ₃ , respectively. It is adapted to connect the 242 _{1-242 4} data input terminal D. Further, the synchronous switching signal 238 is supplied to the switching circuit 245 ₅ fifth, while the rise of the synchronizing switching signal 238, transmission errors clock signal 224 is the first to fourth D flip-flop circuits 242 _{1 to 242 4} The circuit connection is switched so as to be supplied to each clock input terminal C.

While the synchronization switching signal 238 rises, the first to fourth addition values 253 _{1 to} 253 output from the output terminals S of the half adder 243 and the first to third full adders 244 _{1 to} 244 ₃ , respectively. ₄ is supplied to the corresponding first to fourth D flip-flop circuits 242 _{1 to 242 4} of the data input terminal D. First to fourth D flip-flop circuits 242 _{1 to 242 4} outputs the first to fourth output data 251 _{1 to 251 4,} respectively based on the transmission error clock signal 224.

A half adder 243 and the first to third full adder 244 _{1-244 3} of each input terminal A of the adder circuit 241, each of the first to fourth D flip-flop circuits 242 _{1 to 242 4} first to fourth output data 251 _{1 to 251 4} from the output terminal Q is input. Further, the carry signal 252 ₁ output from the output terminal C _o of the half adder 243 are inputted to the first input terminal C _i of the full adder 244 _1. Similarly the carry signal 252 ₂ output from the first output terminal C _o of the full adder 244 ₁ to the second input terminal C _i of the full adder 244 _2, the second full adder 244 _{and second} output The carry signal 252 ₃ output from the terminal C _o is input to the input terminal C _i of the third full adder 244 ₃ .

While the synchronous switching signal 238 is up, i.e. an error signal 237 to the count-up mode is inputted to the adding circuit 241, first through the fourth output data 251 _{1 to 251 4} which is also input to the adder circuit 241 Is added. The first through fourth adder value 253 _{1-253 4} is the value after the addition, in synchronization with the input first to the fourth D flip-flop circuits 242 _{1 to 242 4} each transmission errors clock signal 224 Is done. Then, as the output data 251 _{1 to 251 4} at the next timing of the first to fourth transmission errors clock signal 224. By this is repeated, so that the transmission error generation amount is first to fourth holding the D flip-flop circuits 242 _{1 to 242 4} for each digit. The first D flip-flop circuit 242 ₁ indicates the digit at the bottom of the transmission error amount, order value digit is high becomes held in the fourth D flip-flop circuit 242 ₄ digit top Indicates.

On the other hand, during a period in which the synchronization switching signal 238 is not raised (hereinafter, referred to as a shift mode as appropriate), the first switching circuit 245 ₁ has the data input terminal D of the _first D flip-flop circuit 2421. The connection is switched so that a shift-in signal 239 having a value of “0” is input to. Further, in the second switching circuit 245 ₂ , the first output data 251 ₁ output from the first D flip-flop circuit 242 ₁ is input to the data input terminal D of the second D flip-flop circuit 242 _2. Switch the connection so that. In the third switching circuit 245 ₃ , the second output data 251 ₂ output from the second D flip-flop circuit 242 ₂ is input to the data input terminal D of the third D flip-flop circuit 242 _3. Switch connection. In the fourth switching circuit 245 ₄ , the third output data 251 ₃ output from the third D flip-flop circuit 242 ₃ is input to the data input terminal D of the fourth D flip-flop circuit 242 _4. Switch connection. That is, the first through the fourth D flip-flop circuits 242 _{1 to 242 4,} rather than the addition value 253 from the adding circuit 241, the output data of the shift-in signal 239 or one of the lower digit D flip-flop circuit 242, respectively The connection is switched so that 251 is input.

The fourth output data 251 ₄ output from the fourth D flip-flop circuit 242 ₄ is output to the outside of the error counter circuit 219 as the shift-out signal 226. Further, in the shift mode, the fifth switch circuit 245 _5, rather than the transmission error clock signal 224, the shift clock signal 227, each of the first to fourth D flip-flop circuits 242 _{1 to 242 4} clock input terminal C Switch the connection to be fed into.

  The shift clock generator 213 of the error rate measuring unit 205 in FIG. 1 is normally stopped and does not output the shift clock signal 227. The information processing device 212 outputs the generation start signal 229 after the counter control signal 225 shifts from the raised state to the lowered state, that is, after the count-up mode ends and shifts to the shift mode. Yes. When this generation start signal 229 is input, the shift clock generator 213 starts oscillation and starts outputting the shift clock signal 227.

With this configuration, shifting to the shift mode, the count of the transmission error amount is terminated, the respective values are held in the first to third D flip-flop circuits 242 _{1 to 242 3} are temporarily as it is held . When the output of the shift clock signal 227 is started by the shift clock generator 213, each held value is sequentially shifted bit by bit to the D flip-flop circuit 242 one digit higher. Then, the value of each digit of the transmission error occurrence amount is output as a serial shift-out signal 226 in order from the upper digit.

  First, an operation in the normal case where the error rate is not measured in the error measuring apparatus 201 having the circuit configuration described above will be described.

  In a normal case where the error rate is not measured, the test mode signal 228 input from the error rate measuring unit 205 to the transmission circuit unit 207 is in a falling state. At this time, the parallel-serial conversion transmission circuit 214 converts the parallel data input signal 221 output from the transmission-side logic circuit 206 into a serial signal 222 and sends the serial signal 222 to the reception circuit unit 209 through the transmission path 204. The serial / parallel conversion reception circuit 216 of the reception circuit unit 209 converts the received serial signal 222 into a parallel data output signal 223 having the same bit arrangement as the parallel data input signal 221 and sends the parallel data output signal 223 to the reception side logic circuit 208. In this way, parallel data is sent from the transmission-side logic circuit 206 to the reception-side logic circuit 208 via the transmission path 204 that transmits the serial signal.

  Next, the operation when the error measurement apparatus 201 measures the error rate of the serial transmission circuit 210 will be described.

  When measuring the error rate, the information processing device 212 of the error rate measuring unit 205 sets the test mode signal 228 to be input to the transmission circuit unit 207 while the transmission side LSI 202 and the reception side LSI 203 are operating. increase. Then, the parallel-serial conversion transmission circuit 214 converts the signal to be converted into the serial signal 222 from the parallel data input signal 221 output from the transmission-side logic circuit 206 to the transmission-side reference signal 235 output from the transmission-side reference signal generation unit 215. Switch. The serial signal 222 output from the parallel-serial conversion transmission circuit 214 is transmitted to the reception circuit unit 209 through the transmission path 204, and is converted into a parallel data output signal 223 having the same bit arrangement as the parallel data input signal 221 by the serial-parallel conversion reception circuit 216. The The test mode signal 228 keeps the rising state until the above-described count-up mode ends.

  The reception side reference signal generation unit 217 receives the parallel data output signal 223, and in the state synchronized with this, the same pattern as the transmission side reference signal 235 output from the transmission side reference signal generation unit 215 of the transmission circuit unit 207. The receiving side reference signal 236 which is the above signal is output. The error detection unit 218 determines whether or not the parallel data output signal 223 output from the serial-parallel conversion reception circuit matches the reception-side reference signal 236 in units of bits. When a transmission error is detected, an error signal 237 is output for each bit and sent to the error counter circuit 219. That is, the error signal 237 is sent to the error counter circuit 219 corresponding to the amount of transmission error that has occurred in the serial signal 222 when being transmitted through the transmission path 204.

  When measuring the error rate, the counter control signal 225 input to the receiving circuit unit 209 rises at the timing of starting measurement in the state described above. The counter control signal 225 is synchronized with the transmission error clock signal 224 in the synchronization circuit 220 and sent to the error counter circuit 219 as a synchronization switching signal 238. Since the synchronization between the transmission-side reference signal 235 and the reception-side reference signal 236 has already been established, the error counter circuit 219 can immediately shift to the count-up mode and start counting the transmission error occurrence amount. As described with reference to FIG. 3, the error counter circuit 219 counts the error signal 237 input based on the transmission error clock signal 224 as a transmission error occurrence amount in the count-up mode in which the synchronization switching signal 238 is rising. It has become.

  Then, the counter control signal 225 input to the receiving circuit unit 209 falls at the timing when the measurement is finished. Then, the error counter circuit 219 immediately shifts to the shift mode, finishes counting the transmission error occurrence amount, and no transmission error clock signal 224 is input to each D flip-flop circuit 242. The counted transmission error occurrence amount is held in the error counter circuit, and the shift clock signal 227 can be input to the error counter circuit 219 instead of the transmission error clock signal 224. In this state, the output of the shift clock signal 227 is started at the timing when the error rate measuring unit 205 starts reading the transmission error occurrence amount. When the input of the shift clock signal 227 is started, the error counter circuit 219 outputs the transmission error occurrence amount held during the previous count-up mode as a shift-out signal 226 that is serial data.

  The timing for raising and lowering the counter control signal 225 can be arbitrarily set by the information processing device 212 of the error rate measuring unit 205. That is, the error rate can be measured in an arbitrary period. Since the transmission frequency of the serial signal 222 is fixed to a predetermined value, the number of bits of the serial signal 222 transmitted through the transmission path 204 is determined by the length of the period when the counter control signal 225 is raised. Therefore, the error rate can be calculated by dividing the transmission error occurrence amount indicated by the shift-out signal 226 by the number of transmitted bits. This division is performed by the information processing device 212 of the error rate measuring unit 205 and displayed on a display device (not shown). In this way, the error rate of the serial transmission circuit 210 can be measured.

  Further, the transmission error clock signal 224 is not input to the error counter circuit 219 when the shift mode is switched, and the output of the shift-out signal 226 is started by the shift clock signal 227 later. As a result, even if the count-up mode is terminated at an arbitrary timing, the output timing of the shift-out signal 226 is independent, so the bit indicating the transmission error occurrence amount of the shift-out signal 226 on the error rate measuring device 205 side. The starting position can be reliably detected.

  Furthermore, since the amount of transmission error generated can be output as a serial signal, an increase in the number of output pins is suppressed. Conventionally, speeding up of input / output circuits connecting LSIs has not progressed with respect to speeding up of LSIs, and there is a problem that the input / output pins of LSIs are insufficient for transmission by parallel signals. A transmission circuit is one of the techniques for solving this problem. That is, the serial transmission circuit has an advantage that the transmission speed can be increased while suppressing an increase in the number of input / output pins of the LSI, but the amount of transmission errors can be output while taking advantage of this merit.

  As described above, the transmission circuit unit 207 and the reception circuit unit 209 of the error measurement apparatus 201 of this embodiment are incorporated in the serial transmission circuit 210, and an error counter circuit that switches between the count-up mode and the shift mode is transmitted. Outputs the amount of error as a serial signal. For this reason, the increase in the number of input / output pins of the transmission side LSI 202 is suppressed to one, and the increase in the number of input / output pins of the reception side LSI 203 is limited to three. That is, high integration of LSIs and simplification of the configuration of input / output circuits that connect LSIs are realized.

Further, the error rate can be measured by setting the error counter circuit 219 in the count-up mode in an arbitrary period by the counter control signal. As a result, even when the error rate is high, for example, “100%” and the error counter circuit 219 may overflow, the error rate can be reliably set by setting the time for the count-up mode short. It can be measured. On the contrary, even when the error rate is low, for example, “10 ⁻¹² or less” or “10 ⁻¹⁵ or less”, the error rate can be reliably measured by setting the count-up mode longer. That is, the error rate can be reliably measured regardless of the error rate.

  Further, the shift clock signal 227 used for outputting the transmission error occurrence amount is independent of other clock signals. Therefore, it is possible to start outputting the shift-out signal 226 at an arbitrary timing without stopping the operations of the transmission-side LSI 202 and the reception-side LSI 203 and to set independent frequencies. That is, even in the serial transmission circuit 210 that transmits the serial signal 222 at a high transmission frequency, the error rate is reliably measured using the actual transmission path 204 while the transmission side LSI 202 and the reception side LSI 203 are operating. Can do.

  Therefore, the operator can easily measure the error rate during an arbitrary period without being particularly aware of the error measuring device 201.

  Further, by inputting a predetermined value using the shift-in signal 239, the value held by the error counter circuit 219 can be freely set, and the operation of the error counter circuit 219 can be tested. Further, the value held by the error counter circuit 219 can be cleared by inputting the value “0” by the shift-in signal 239.

  It should be noted that when the value held by each D flip-flop circuit 242 of the error counter circuit 219 is shifted out or cleared, zero shift may be performed without inputting the shift-in signal 239. The test mode signal 228 is not output from the error rate measuring unit 205, but a signal output circuit or a switch for outputting the test mode signal 228 may be provided separately. Further, when the transmission-side reference signal generation unit 215 of the transmission circuit unit 207 inserts a control signal at regular intervals, the error detection unit does not compare the control signal portion. Alternatively, the transmission-side reference signal generation unit may temporarily stop the generation of the control signal when measuring the error rate. Also, the code conversion is performed by the parallel-serial conversion transmission circuit 214, and the start position of the data frame is detected by a frame detection circuit (not shown) provided in the reception-side reference signal generation unit 217, but the data signal is not subjected to code conversion. And serial signal conversion / transmission circuit 214 for control and control signal and receiving side reference signal generation unit 217 may be provided to detect the start position of the data frame.

<First Modification of Invention>

  In the embodiment described above, the case where there is one serial transmission circuit to be measured for the error rate has been described. In the first modification, an error measuring device capable of measuring an error rate at a time for a plurality of serial transmission circuits will be described.

FIG. 5 shows a main part of the circuit configuration of the error measuring apparatus according to the first modification, and corresponds to FIG. 2 of the embodiment. Therefore, the same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. Further, description will be made with reference to FIG. The transmission circuit 300 is disposed between the transmission side logic circuit 206 provided in the transmission side LSI 202 of FIG. 1 and the reception side logic circuit 208 provided in the reception side LSI 203 of the embodiment. m serial transmission circuits 310 _{1 to} 310 _m .

In the first modification, the first to m-th parallel data input signals 221 _{1 to} 221 _m are output from the transmission-side logic circuit 206 of FIG. 1, and the first to m-th serial transmission circuits are respectively provided. It is input to 310 _{1 to} 310 _m . Further, the first to have from the m serial transmission circuit 310 ₁ to 310 _m of the output parallel data output signal 223 ₁ to 223 _m of the first to m, respectively, the receiving side logic circuit 208 of FIG. 1 Has been entered. Further, the test mode signal 228 output from the error rate measuring unit 205 in FIG. 1 and the transmission error clock signal 224 output from the PLL circuit 211 are respectively transmitted to the first to m-th serial transmission circuits 310 _{1 to} 310 _m . Are input in common.

First serial transmission circuit 310 ₁ includes a transmission circuit unit 207 shown in FIG. 2 embodiment, a part of the reception circuit section 209 as a circuit unit of the reception side, corresponding to the transmission path 204 of FIG. 1 shown The first transmission path is not configured. The part of the reception circuit unit 209 is the serial-parallel conversion reception circuit 216, the reception-side reference signal generation unit 217, and the error detection unit 218 in FIG. The first parallel data input signal 221 ₁ is input to the parallel / serial conversion transmission circuit 214 of the transmission circuit unit 207, and the serial / parallel conversion reception circuit 216 of the reception circuit unit 209 outputs the first parallel data output signal 223 ₁ . It is supposed to be. The error detection unit 218 outputs a _first error signal 2371 that represents a transmission error that has occurred in the first transmission path (not shown). Output of the first other processing or signal of each device of the serial transmission circuit 310 ₁ is similar to the embodiment.

The second to m-th serial transmission circuits 310 _{2 to} 310 _m have the same configuration as that of the first serial transmission circuit 310 _{1 although} not shown. The second to mth error signals 237 _{2 to} 237 _m are output. Further, the same transmission frequency is used in the first to m-th transmission lines (not shown).

Of the portion corresponding to the reception circuit unit 209 of FIG. 2 embodiment, the remaining portion not included in the first serial transmission circuit 310 _1, i.e. the synchronization circuit 220 and the error counter circuit 219 and the input and output signals to these Is similar to FIG. However, unlike FIG. 2, the OR gate 303 is arranged on the side of the error counter circuit 219 that receives the error signal 237 so as to connect the output side thereof. The input side of the OR gate 303, so that the first through the error signal 237 ₁ ~237 _m of the m output respectively from the first to the serial transmission circuit 310 ₁ to 310 _m of the m is input . That is, when any one of the _{first to} mth error signals 237 _{1 to} 237 _m is input, the error signal 237 is sent to the error counter circuit 219. The error counter circuit 219 counts transmission errors generated in the _first to m-th serial transmission circuits 310 _{1 to} 310 _{m in} a combined form, and outputs the result as a shift-out signal 226. Yes.

The first to m-th parallel data input signals 221 _{1 to} 221 _m are signals inside the transmission-side LSI 202 in FIG. 1, and the first to m-th parallel data output signals 223 _{1 to} 223 _m and the _first to first m-th parallel data input signals 221 _{1 to} 221 _m The m error signals 237 _{1 to} 237 _m are signals inside the reception-side LSI 203. Therefore, similarly to the embodiment, the increase in the number of input / output pins of the transmission side LSI 202 is suppressed to one, and the increase of the input / output pins of the reception side LSI 203 is suppressed to three.

  As described above, according to the first modification, it is possible to reliably measure the error rate for a plurality of serial transmission circuits in an arbitrary period while suppressing an increase in input / output pins.

Furthermore, the first modification can also be applied when the first to m-th serial transmission circuits 310 _{1 to} 310 _m are connected to different transmission-side LSIs and reception-side LSIs. In this case, a wiring for the error signal 237 is added between the receiving-side LSI 203 and each receiving-side LSI in which the _{second to} m-th serial transmission circuits 310 _{2 to} 310 _m are incorporated. Further, a wiring for the test mode signal 228 is added between the error rate measuring unit 205 and each of the transmission side LSIs in which the _{second to} mth serial transmission circuits 310 _{2 to} 310 _m are incorporated. Increase of the input and output pins of the receiving side LSI 203 to the first serial transmission circuit 310 ₁ is incorporated, "m + 2" is suppressed in pieces, by providing appropriate gate to the outside of the receiving LSI 203, further the output It is also possible to suppress the increase in pins.

<Second Modification of Invention>

  In the first modification described above, the error rate can be measured for the entire input / output circuit composed of a plurality of serial transmission circuits, but how many transmission errors have occurred in each transmission path. It cannot be determined outside the input / output circuit. In the second modification, a synchronization circuit and an error counter circuit are provided in each serial transmission circuit, and each shift-out signal is sequentially shifted between the serial transmission circuits, thereby suppressing an increase in input / output pins. Enables error rate measurement for each transmission line.

FIG. 6 shows a main part of the circuit configuration of the error measuring apparatus according to the second modification, and corresponds to FIG. 5 of the first modification. Therefore, the same parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. Further, description will be made with reference to FIG. Similar to FIG. 5, the transmission circuit 400 is disposed between the transmission side logic circuit 206 provided in the transmission side LSI 202 of FIG. 1 and the reception side logic circuit 208 provided in the reception side LSI 203. The first to m-th serial transmission circuits 410 _{1 to} 410 _m are configured.

However, unlike FIG. 5, the first serial transmission circuit 410 ₁ also includes a synchronization circuit 220 and an error counter circuit 219, and no OR gate is arranged, and an error output from the error detection unit 218 is not provided. The signal 237 is input to the error counter circuit 219. The shift-out signal 226 ₁ output from the error counter circuit 219 is output to the outside of the first serial transmission circuit 410 ₁ .

The serial transmission circuit 410 ₂ - 410 _m of the second to m are also the same structure ₁ and the first serial transmission circuit 410, a shift-out signal 226 ₂ ~226 _m of second to m, respectively Output. Further, the test mode signal 228, the counter control signal 225, and the shift clock signal 227 output from the error rate measuring device 205 of FIG. 1 are supplied to the first to m-th serial transmission circuits 410 _{1 to} 410 _m , respectively. . Further, a transmission error clock signal 224 output from the PLL circuit 211 of FIG. 1 is also supplied.

Further, in the second modification, the second shift-out signal 226 ₂ output from the second serial transmission circuit 410 ₂ is sent to the error counter circuit 219 of the first serial transmission circuit 410 ₁ as a shift-in signal. Entered. A third shift-out signal 226 ₃ output from a third measurement circuit unit (not shown) is input as a shift-in signal to the second serial transmission circuit 410 ₂ . Similarly, the shift-out signal 226, each of the serial transmission circuit 410 is output are input to the first serial transmission circuit 410 ₁ by the near side next to the serial transmission circuit 410 as a shift-in signal .

As a result, when the first to m-th serial transmission circuits 410 _{1 to} 410 _m shift to the shift mode by the counter control signal 225 and the input of the shift clock signal 227 is started, the transmission error generation amount held for each of them is started. goes are sequentially shifted to the first serial transmission circuit 410 _1. As a result, the transmission error generation amounts obtained by the _first to m-th serial transmission circuits 410 _{1 to} 410 _m are sequentially output from the first serial transmission circuit 410 ₁ as the shift-out signal 226 ₁ . By dividing this at every 4 bits on the error rate measuring device 205 side in FIG. 1, the transmission error occurrence amount for each transmission path 204 of each serial transmission circuit 410 can be read, and the error rate is determined for each transmission path 204. It becomes possible to measure.

The second to m-th shift-out signals 226 _{2 to} 226 _m are signals inside the reception-side LSI 203 in FIG. Therefore, similarly to the embodiment and the first modification, the increase in the number of input / output pins of the transmission side LSI 202 is suppressed to one, and the increase of the input / output pins of the reception side LSI 203 is suppressed to three.

  As described above, according to the second modification, it is possible to reliably measure the respective error rates in a plurality of serial transmission circuits while suppressing an increase in input / output pins.

Further, similarly to the first modification, the second modification is also applied when the first to m-th serial transmission circuits 410 _{1 to} 410 _m are connected to different transmission-side LSIs and reception-side LSIs. Can be applied. In this case, the wiring of the shift-out signal 226 is added between the adjacent receiving-side LSIs among the receiving-side LSIs in which the first to m-th serial transmission circuits 410 _{1 to} 410 _m are incorporated. Further, a wiring for the test mode signal 228 is added between the error rate measuring unit 205 and each of the transmission-side LSIs in which the _{second to} m-th serial transmission circuits 410 _{2 to} 410 _m are incorporated. Increase of the input and output pins of the receiving side LSI203 the first serial transmission circuit 410 ₁ is incorporated will be suppressed to four.

It is the block diagram which showed the structure of the circuit apparatus of the error measuring device by one Example of this invention. It is the block diagram which showed the circuit structure of the serial transmission circuit by a present Example. It is a circuit diagram showing a circuit configuration of an error counter circuit according to the present embodiment. It is the circuit diagram which showed the specific circuit structure of the synchronization circuit by a present Example. It is the circuit diagram which showed the circuit structure of the error measuring device by a 1st modification. It is the circuit diagram which showed the circuit structure of the error measuring device by the 2nd modification.

Explanation of symbols

201 Error measuring device 202 Transmitting side LSI
203 Receiver LSI
204 Transmission path 205 Error rate measuring device 206 Transmission side logic circuit 207 Transmission circuit unit 208 Reception side logic circuit 209 Reception circuit unit 210, 310, 410 Serial transmission circuit 211 PLL circuit 212 Information processing device 213 Shift clock generator 214 Parallel serial conversion Transmission circuit 215 Transmission side reference signal generation unit 216 Serial parallel conversion reception circuit 217 Reception side reference signal generation unit 218 Error detection unit 219 Error counter circuit 220 Synchronization circuit 241 Adder circuit 242 D flip-flop circuit 243 Half adder 244 Full adder 245 Switching circuit 300, 400 Transmission circuit 303 OR gate

Claims (7)

Parallel data output means for outputting arbitrary parallel data, test data output means for outputting parallel data having the same bit configuration as the parallel data as test data during a test for measuring an error, and converting the parallel data into serial data Parallel data to be selected by the parallel-serial conversion means and parallel data output by the test data output means at the time of the test; otherwise, the parallel data output by the parallel data output means is selected and supplied to the parallel-serial conversion means A first integrated circuit comprising: selection means; and serial data sending means for sending the serial data converted by the parallel-serial conversion means to a predetermined transmission line;
Serial / parallel conversion means for converting serial data transmitted through the predetermined transmission path into parallel data, and a test for outputting parallel data converted by the serial / parallel conversion means at the time of the test to the test data output means An error detection means for detecting an error occurring in the serial data in comparison with the same parallel data as the data, an error storage means for storing the error detected by the error detection means over a predetermined period, and an error storage means An error measuring apparatus comprising: a second integrated circuit including error serial output means for serially outputting stored contents in synchronization with a predetermined read signal.   2. The error measuring apparatus according to claim 1, wherein the error storage means is means for storing a count value as the number of errors.   The error serial output means is a means for serially outputting the count value stored in the error storage means in synchronization with a predetermined read signal to be output after the end of the predetermined period. The error measurement device according to claim 2. Parallel data output means for outputting arbitrary parallel data, test data output means for outputting parallel data having the same bit configuration as the parallel data as test data during a test for measuring an error, and converting the parallel data into serial data Parallel data to be selected by the parallel-serial conversion means and parallel data output by the test data output means at the time of the test; otherwise, the parallel data output by the parallel data output means is selected and supplied to the parallel-serial conversion means A plurality of first integrated circuits comprising: selection means; and serial data sending means for sending the serial data converted by the parallel-serial conversion means to a predetermined transmission line;
The serial data that is provided corresponding to each of the plurality of first integrated circuits and that is transmitted through the predetermined transmission path through which the first integrated circuit corresponding to the own circuit transmits serial data is converted into parallel data. Serial / parallel conversion means, and test data output from the test data output means provided in the first integrated circuit corresponding to the circuit, the parallel data converted by the serial / parallel conversion means at the time of the test, A plurality of second integrated circuits comprising error detection means for detecting an error occurring in the serial data in comparison with the same parallel data;
Error storage means for storing errors detected by the error detection means provided in the plurality of second integrated circuits over a predetermined period, and the stored contents of the error storage means are serially output in synchronization with a predetermined read signal And a third integrated circuit having an error serial output means. Parallel data output means for outputting arbitrary parallel data, test data output means for outputting parallel data having the same bit configuration as the parallel data as test data during a test for measuring an error, and converting the parallel data into serial data Parallel data to be selected by the parallel-serial conversion means and parallel data output by the test data output means at the time of the test; otherwise, the parallel data output by the parallel data output means is selected and supplied to the parallel-serial conversion means A plurality of first integrated circuits comprising: selection means; and serial data sending means for sending the serial data converted by the parallel-serial conversion means to a predetermined transmission path;
The serial data that is provided corresponding to each of the plurality of first integrated circuits and that is transmitted through the predetermined transmission path through which the first integrated circuit corresponding to the own circuit transmits serial data is converted into parallel data. Serial / parallel conversion means, and test data output by the test data output means provided in the first integrated circuit corresponding to the circuit, the parallel data converted by the serial / parallel conversion means at the time of the test, Error detection means for detecting an error occurring in the serial data in comparison with the same parallel data, and error storage means for storing a count value as the number of errors detected by the error detection means over a predetermined period. A plurality of second integrated circuits;
The error storage means of these second integrated circuits are serially connected, and the count values stored in these error storage means are sequentially synchronized with a predetermined read signal whose output is started after the end of the predetermined period. An error measuring device comprising: error serial output means for outputting after shifting.   The first integrated circuit and the second integrated circuit are disposed on the same substrate, and on the substrate, a first time for transmitting the fact that the test is being performed to the parallel data selection unit and the error detection unit is performed. Transmitting means, second transmitting means for transmitting to the error storage means that the predetermined period is in the predetermined period for storing the error, and transmitting the predetermined read signal to the error serial output means. 6. The error measuring device according to claim 1, further comprising a test processing circuit including a third transmission unit. A serial data reception step during a test for receiving serial data sent from a specific integrated circuit through a transmission line from the start to the end of a test for measuring an error;
A serial-parallel conversion step for sequentially converting the serial data received in the serial data reception step during the test into parallel data of a bit configuration that is a target of error measurement;
An error presence / absence determination step for determining the presence / absence of an error by sequentially comparing parallel data after conversion in this serial / parallel conversion step with parallel data for test prepared in advance,
A count step for counting the number of errors determined in the error presence determination step;
An error measurement method comprising: an error serial output step for serially outputting data representing a count value counted in the count step at the time when the test is completed, one bit at a time in synchronization with a predetermined read clock.

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