KR102079729B1 - Apparatus for detecting communication error and communication system having the same - Google Patents

Abstract

The present invention is to provide a communication error detection device and a communication system having the same that is built in the receiver as well as performing a stable operation. The present invention includes a control logic unit provided in a receiver for receiving and processing a transmission signal including specific pattern data transmitted from a transmitter, and outputting a control clock signal; A reference data generator which receives the control clock signal and outputs reference data; And inputting the pattern data and the reference data, and initially performing an initial data setting operation for matching the sequence of the pattern data with the sequence of the reference data, and then detecting an error of the transmission signal. A communication error detection device having an error detection unit is provided.

Description

Apparatus for detecting communication error and communication system having the same}

The present invention relates to a communication error detecting apparatus for detecting an error of data transmitted from a transmitter and received at a receiver, and a communication system having the same.

Various types of electrical signals are transmitted between the device and the device. Here, the apparatus for transmitting the electrical signal corresponds to the transmitter, and the apparatus for receiving the signal corresponds to the receiver. Devices for transmitting and receiving signals may be comprised of integrated circuit chips, electronic devices, mobile communication terminals, interfaces, and the like. As such, when the transmitter transmits an electrical signal, the receiver receives the signal and performs signal processing, and then outputs the signal through a display device or a speaker to inform the user.

Ideally, the signal sent from the transmitter is received by the receiver as it is. In reality, however, the transmission signal may include noise in the external environment or by the transmission means in the process of transmitting the transmission signal. This noise is generally removed by the noise cancellation circuit of the receiver. In order to remove the noise, a noise detection device for checking whether the transmission signal contains noise is required. Most noise detection devices are provided separately from the transmitter and the receiver. In addition, when the noise detection device is embedded in the receiver, the frequency of the clock signal used in the transmitter and the receiver is very high, making it difficult to design the circuit and reducing the stability of the circuit operation.

The present invention is to provide a communication error detection device and a communication system having the same that is built in the receiver as well as performing a stable operation.

Communication error detection apparatus according to an embodiment of the present invention to solve the above problems,

A communication error detection apparatus provided in a receiver for receiving and processing a transmission signal including specific pattern data from a transmitter, the apparatus comprising: a control logic unit configured to output a control clock signal; A reference data generator which receives the control clock signal and outputs reference data; And inputting the pattern data and the reference data, and initially performing an initial data setting operation for matching the sequence of the pattern data with the sequence of the reference data, and then detecting an error of the transmission signal. An error detection unit is provided.

Communication error detection apparatus according to another embodiment of the present invention to solve the above problems,

A communication error detection apparatus provided in a receiver for receiving and processing a transmission signal including specific pattern data from a transmitter, the apparatus comprising: a pattern data separation unit for inputting the pattern data and separating the pattern data into a plurality; A plurality of seed aligners, each of which receives one of the plurality of pattern data and detects an error of the input pattern data; And an output unit which combines the error signals output from the plurality of seed aligners and outputs the transmission error signal of the transmission signal.

In order to solve the above problems, a communication system according to an embodiment of the present invention,

A transmitter including a pattern generator for generating and outputting specific pattern data and a transmitter for transmitting a transmission signal including the pattern data; And a receiver for receiving the transmission signal, wherein the receiver comprises a communication error detection device, wherein the communication error detection device comprises: a control logic unit configured to output a control clock signal; A reference data generator which receives the control clock signal and outputs reference data; And an error detection unit configured to detect an error of the transmission signal after first performing an initial data setting operation for inputting the pattern data and the reference data and matching the sequence of the pattern data with the sequence of the reference data. Have

In order to solve the above problems, a communication system according to another embodiment of the present invention,

A transmitter including a pattern generator for generating a plurality of sub-pattern data and outputting pattern data combining the plurality of sub-pattern data into one, and a transmitter for transmitting a transmission signal including the pattern data output from the pattern generator ; And a receiver for receiving the transmission signal, wherein the receiver comprises a communication error detection device, wherein the communication error detection device receives the pattern data and separates the pattern data into the plurality of sub pattern data. A pattern data separator; A plurality of seed aligners, each of which receives one of the plurality of subpattern data and detects an error of the input subpattern data; And an output unit for combining the error signals output from the plurality of seed aligners and outputting the transmission error signal of the transmission signal.

As described above, according to the present invention, a communication error detection device is provided in a receiver of a communication system. Therefore, the bit error rate of the transmission signal transmitted from the transmitter can be easily measured.

In addition, the communication error detection apparatus according to the present invention separates and processes the pattern data into a plurality of pattern data, thereby lowering the data processing speed of the communication error detection apparatus by twice, and stably detecting the error bits of the transmission signal.

1 is a block diagram of a communication system according to a first embodiment of the present invention.
2 is a block diagram of the communication error detection apparatus shown in FIG. 1.
FIG. 3 is a block diagram of the control logic unit shown in FIG. 2.
4 is a block diagram of an error detector illustrated in FIG. 2.
FIG. 5 is a timing diagram of signals of the communication error detection apparatus shown in FIG. 2.
6 is a block diagram of a communication system according to a second embodiment of the present invention.
FIG. 7 is a block diagram illustrating a first embodiment of the pattern generator illustrated in FIG. 6.
FIG. 8 is a timing diagram of signals of the pattern generator illustrated in FIG. 7.
9 is a block diagram according to a first embodiment of the communication error detection apparatus shown in FIG. 6.
10A and 10B are timing diagrams of signals of the communication error detection apparatus shown in FIG.
FIG. 11 is a block diagram illustrating a second embodiment of the pattern generator illustrated in FIG. 6.
FIG. 12 is a timing diagram of signals of the pattern generator illustrated in FIG. 11.
13 is a block diagram according to a second embodiment of the communication error detection apparatus shown in FIG. 6.
14A and 14B are timing diagrams of the signals shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The same reference numerals among the reference numerals shown in each drawing represent the same members.

1 is a block diagram of a communication system 101 according to a first embodiment of the present invention. Referring to FIG. 1, the communication system 101 includes a transmitter 110 and a receiver 120.

The transmitter 110 includes a pattern generator 111 and a transmitter 113. The pattern generator 111 generates pattern data TDT having a specific pattern. For example, the pattern generator 111 includes a linear feedback shift register to generate the pattern data TDT. The transmitter 113 transmits to the receiver 120 a state suitable for transmitting the transmission signal TX including the pattern data TDT, for example, modulates the transmission signal TX.

The receiver 120 includes a receiver 121, a communication error detection device 123, and a counter 125. The receiver 121 receives a signal RX transmitted from the transmitter 110 and demodulates a state suitable for processing the received signal RX in the receiver 120. At this time, the receiver 121 extracts the pattern data TDTR included in the received signal RX and transfers the pattern data TDTR to the communication error detection apparatus 123. The communication error detection device 123 receives the pattern data TDTR, and detects whether an error has occurred in the transmission process of the pattern data TDTR. The communication error detection device 123 includes the same device as the pattern generator 111 included in the transmitter 110, for example, a linear feedback shift register. That is, the pattern data TDT generated by the pattern generator 111 and the reference data generated by the communication error detection device 123 are configured in the same manner. As such, by comparing the pattern data TDT output from the pattern generator 111 with the reference data output from the communication error detection apparatus 123, it is possible to accurately detect whether an error has occurred in the received signal RX. There is a number. The counter 125 receives and counts an error signal ER output from the communication error detection device 123 and measures the bit error rate of the received signal RX.

As described above, by providing the communication error detection device 123 in the receiver 120, the bit error rate of the signal RX transmitted from the transmitter 110 and received by the receiver 120 can be easily measured. That is, until now, it is difficult to measure the bit error rate of the received signal RX by using an external device, but the present invention solves this difficulty by providing the communication error detection device 123 inside the receiver 120. There is a number.

2 is a block diagram of the communication error detection apparatus 123 shown in FIG. Referring to FIG. 2, the communication error detecting apparatus 123 includes a control logic unit 210, a reference data generator 220, and an error detector 230.

The control logic unit 210 outputs the control clock signal CLKO under the control of the external signals RST, DCLK, and FLG. That is, the control logic unit 210 receives an externally provided reset signal RST, an external clock signal DCLK, and a flag signal FLG output from the error detector 230. Output the clock signal CLKO. When the reset signal RST is activated, the control logic unit 210 outputs the control clock signal CLKO in synchronization with the external clock signal DCLK for a predetermined period. Initially, the flag signal FLG remains in an inactive state. Thus, initially, the control logic 210 is not affected by the flag signal FLG. The control logic unit 210 does not output the control clock signal CLKO after the predetermined period. When the flag signal FLG is activated, the control logic unit 210 outputs the control clock signal CLKO again. The control logic unit 210 will be described in detail with reference to FIG. 3.

The reference data generator 220 receives the reset signal RST and the control clock signal CLKO, and outputs the reference data RDT. The reference data generator 220 is reset when the reset signal RST is activated. In this state, the reference data generator 220 generates and outputs reference data RDT in response to the control clock signal CLKO. The reference data generator 220 may include a linear feedback shift register. Accordingly, the linear feedback shift register shifts the control clock signal CLKO to output the reference data RDT. The reference data generator 220 may be configured in the same manner as the pattern generator 111 provided in the transmitter 110. Therefore, the reference data generator 220 generates the same reference data RDT as the pattern generator 111.

The error detector 230 receives the pattern data TDTR, the reset signal RST, the external clock signal DCLK, the reference data RDT, and the control clock signal CLKO, and the flag signal FLG and the error signal ( ER). The error detector 230 is reset when the reset signal RST is activated. In this state, the error detector 230 compares the pattern data TDTR and the reference data RDT in synchronization with the external clock signal DCLK and the control clock signal CLKO. An error of the received signal RX is detected. When an error is detected in the received signal RX, the error signal ER is activated for a specific time to inform the outside that an error of the received signal RX has occurred. The flag signal FLG is initially maintained in an inactive state while the communication error detecting apparatus 123 performs the initial data setting operation, and is activated when the initial data setting operation is terminated.

The error detector 230 may include a sequence of the pattern data TDTR and a reference data generator at an initial stage before detecting an error of the received signal RX, that is, at an initial stage when the receiver 120 starts to operate. An initial data setting operation for comparing and matching sequences of the reference data RDT output from 220 is performed. In the initial data setting operation, if the sequence of the pattern data TDTR and the sequence of the reference data RDT match, the error detector 230 activates the flag signal FLG. The flag signal FLG remains in an inactive state during the initial data setting operation.

As such, the communication error detecting apparatus 123 initially performs an initial data setting operation that compares and matches the sequence of the pattern data TDTR and the sequence of the reference data RDT, and then receives the received signal RX. Detect an error. Therefore, the operation is simple and the size of the communication error detection device 123 is reduced.

3 is a block diagram of the control logic unit 210 shown in FIG. 2. Referring to FIG. 3, the control logic unit 210 includes a counter 211, a latch 212, an OR gate 213, and an AND gate 214. do.

The counter 211 receives a reset signal RST and an external clock signal DCLK, and outputs a counter enable signal CT_EN. When the reset signal RST is applied, the counter 211 activates the counter enable signal CT-EN for a predetermined period (m in FIG. 5) of the external clock signal DCLK and outputs the logic enable state, for example, in a logic high state. .

The latch 212 receives a flag signal FLG and outputs a comparison result signal COML. That is, the latch 212 outputs the comparison result signal COML in response to the flag signal FLG. The latch 212 may be configured as a delay flip-flop.

The OR gate 213 receives a counter enable signal CT-EN and a comparison result signal COML, and outputs a clock enable signal CLK_EN. That is, the OR gate 213 outputs the clock enable signal CLK_EN as logic high when any one of the counter enable signal CT_EN and the comparison result signal COML is logic high.

The AND gate 214 receives a clock enable signal CLK_EN and an external clock signal DCLK, and outputs a control clock signal CLKO. That is, the AND gate 214 outputs the control clock signal CLKO as a logic low when any one of the clock enable signal CLK_EN and the external clock signal DCLK is logic low.

The overall operation of the control logic unit 123A is as follows.

Initially, the flag signal FLG is deactivated, and accordingly, the comparison result signal COML is deactivated. In this state, when the reset signal RST is activated, the counter enable signal CT_EN is activated for a predetermined period (m in FIG. 5) of the external clock signal DCLK, and accordingly, the clock enable signal CLK_EN is also predetermined. It is activated during the cycle. Therefore, the control clock signal CLKO is generated in synchronization with the external clock signal DCLK during the predetermined period. After the predetermined period has passed, the counter enable signal CT_EN is inactivated, and thus the clock enable signal CLK_EN is also inactivated and the control clock signal CLKO is not generated. When the flag signal FLG is activated, the comparison result signal COML is activated, and accordingly, the clock enable signal CLK_EN is activated, and the control clock signal CLKO is synchronized again with the external clock signal DCLK. Will occur.

4 is a block diagram of the error detector 230 illustrated in FIG. 2. Referring to FIG. 4, the error detector 230 includes a pattern data shifting unit 231, a reference data shifting unit 232, and a data comparing unit 233.

The pattern data shifting unit 231 receives the pattern data TDTR, the reset signal RST, and the external clock signal DCLK, and transmits an output signal to the data comparator 233. The pattern data shifting unit 231 is reset when the reset signal RST is activated. The pattern data shifting unit 231 shifts and outputs the pattern data TDTR in synchronization with the external clock signal DCLK. The pattern data shifting unit 231 outputs the pattern data TDTR in parallel in bit units. The pattern data shifting unit 231 includes a shift register for shifting a signal.

The reference data shifting unit 232 receives the reference data RDT, the reset signal RST, and the control clock signal CLKO, and transmits an output signal to the data comparator 233. The reference data shifting unit 232 is reset when the reset signal RST is activated. The reference data shifting unit 232 shifts and outputs the reference data RDT in synchronization with the control clock signal CLKO. The reference data shifting unit 232 outputs the reference data RDT in parallel in bit units. The reference data shifting unit 232 includes a shift register for shifting a signal. The shift register provided in the pattern data shifting unit 231 and the shift register provided in the reference data shifting unit 232 may be the same.

The data comparison unit 233 compares the data output from the pattern data shifting unit 231 and the data output from the reference data shifting unit 232 bit by bit, and includes a plurality of XOR gates corresponding to the number of bits of each of the data. exclusive OR gate or XNOR gates 233a? 233n. Accordingly, the XOR gates corresponding to the case where the bits of the data output from the pattern data shifting unit 231 and the bits of the data output from the reference data shifting unit 232 do not coincide with a logic "1" (XNOR gate). (233a) 233n, logic "0" is outputted). When a plurality of XNOR gates 233a ■ 233n are provided in the data comparator 233, an error signal output from the data comparator 233 by further connecting an inverter 235 to an output terminal of the data comparator 233. The signal ER generated by inverting is outputted. When no error is detected in the pattern data TDTR, the data comparator 233 activates the flag signal FLG and outputs, for example, a logic high. In order to stabilize the flag signal FLG, the buffer 234 may be connected to an output terminal of the data comparator 233, and the flag signal FLG may be output through the buffer 234.

In this way, the error detection unit 123C compares the pattern data TDTR and the reference data RDT bit by bit to detect an error of the pattern data TDTR. Therefore, by counting the error of the pattern data TDTR, the bit error rate of the received signal RX can be measured accurately.

5 is a timing diagram of signals of the communication error detection apparatus 123 shown in FIG. 3 to 5, the operation of the communication error detection apparatus 123 shown in FIG. 2 will be described.

The communication error detecting apparatus 123 first performs an initial data setting operation before detecting an error of the received signal RX. That is, the communication error detecting apparatus 123 may include a sequence of the pattern data TDTR included in the signal RX received through the initial data setting operation, and the reference data RDT generated by the communication error detecting apparatus 123. Match the sequence.

The communication error detection apparatus 123 performs the initial data setting operation as follows. The control logic unit 123A outputs the control clock signal CLKO for a predetermined period m, the reference data generator 220 outputs the initial reference data RDT in response to the control clock signal CLKO, The error detector 123C compares the sequence of the pattern data TDTR included in the initially received signal RX transmitted initially among the received signals RX with the sequence of the initial reference data RDT. While performing the comparison operation, when the two data sequences match, the communication error detection device 123 ends the initial data setting operation.

Specifically, the flag signal FLG is initially deactivated, and thus the comparison result signal COML is deactivated. In this state, when the reset signal RST is activated, the counter enable signal CT_EN is activated for a predetermined period m of the external clock signal DCLK, and accordingly, the clock enable signal CT_EN is also set in the predetermined period ( m) is activated during. Therefore, the control clock signal CLKO is generated in synchronization with the external clock signal DCLK during the predetermined period m. After the predetermined period m has passed, the counter enable signal CT_EN is inactivated. Accordingly, the clock enable signal CLK_EN is also inactivated and the control clock signal CLKO is not generated. If the control clock signal CLKO does not occur, the reference data RDT does not occur, and the error detector 123C stops the operation of detecting an error of the received signal RX during this period p. In this state, if the sequence of the pattern data TDTR and the sequence of the reference data RDT match, the flag signal FLG is activated. Accordingly, the comparison result signal COML is activated, and the clock enable signal CLK_EN is also activated again. Therefore, the control clock signal CLKO is also generated again in synchronization with the external clock signal DCLK. Then, the reference data generator 220 outputs the reference data RDT and transmits it to the error detector 123C. Accordingly, the error detector 123C detects an error of the received signal RX. The error signal ER is generated when both the flag signal FLG and the comparison result signal COML are activated.

6 is a block diagram of a communication system according to a second embodiment of the present invention. Referring to FIG. 6, the communication system 601 includes a transmitter 610 and a receiver 620.

The transmitter 610 includes a pattern generator 611 and a transmitter 613. The pattern generator 611 generates pattern data TDT having a specific pattern. At this time, the pattern generator 611 generates a plurality of sub-pattern data (TDTA, TDTB), for example, two or four pattern data, combines them into one, and transmits them to the transmitter 613. For example, the pattern generator 611 includes a plurality of linear feedback shift registers to generate sub-pattern data TDTA and TDTB having a plurality of different patterns. The transmitter 613 transmits a state suitable for transmitting the transmission signal RX including the pattern data TDT output from the pattern generator 611, for example, a modulated transmission signal TX to the receiver 620. .

The receiver 620 includes a receiver 621, a communication error detection device 623, and a counter 625. The receiver 621 receives the signal RX transmitted from the transmitter 610 and demodulates a state suitable for processing in the receiver 620. At this time, the receiver 621 extracts the pattern data TDTR included in the received signal RX and transmits the pattern data TDTR to the communication error detection apparatus 623. The communication error detection apparatus 623 separates the input pattern data TDTR into a plurality of pieces, and detects whether an error has occurred in the transmission process for each of the plurality of pattern data TDTRA and TDTRB. The communication error detection device 623 may include a plurality of devices, for example, a linear feedback shift register, that are the same as the pattern generator 611 of the transmitter 610. Therefore, the pattern data TDT generated by the pattern generator 611 and the reference data generated by the communication error detection device 623 are configured in the same manner. Thus, the received signal RX is compared by comparing the plurality of sub-pattern data TDTRA and TDTRB included in the received signal RX with the plurality of reference data generated inside the communication error detection device 623, respectively. It is possible to accurately detect whether or not an error has occurred. The counter 625 can measure the bit error rate of the received signal RX by receiving and counting the error signal ER output from the communication error detection device 623.

As described above, the communication error detection device 623 is provided in the receiver 620 of the communication system 601 to facilitate the bit error rate of the signal RX transmitted from the transmitter 610 and received at the receiver 620. I can measure it easily. That is, until now, it is difficult to measure the bit error rate of the received signal RX using an external device. However, the present invention provides a communication error detection device 623 in the receiver 620 to solve this difficulty. I can solve it.

FIG. 7 is a block diagram according to the first embodiment of the pattern generator 611 illustrated in FIG. 6. Referring to FIG. 7, the pattern generator 611 includes a clock divider 710, a pattern generator 720, a shifting unit 730, and a coupling unit 740.

The clock divider 710 receives an external clock signal TCLK and generates two internal clock signals TCLKA and TCLKB, for example, first and second internal clock signals TCLKA and TCLKB. At this time, the frequencies of the first and second internal clock signals TCLKA and TCLKB are reduced to half of the frequency of the external clock signal TCLK.

The pattern generator 720 receives the first internal clock signal TCLKA and generates the first sub-pattern data TDTA by shifting the first internal clock signal TCLKA into a predetermined pattern. The pattern generator 720 may be configured with a linear feedback shifter register that generates constant pattern data.

The shifting unit 730 receives the first sub-pattern data TDTA and the second internal clock signal TCLKB, and shifts the first sub-pattern data TDTA in synchronization with the second internal clock signal TCLKB. shifted) to generate second sub-pattern data TDTB. The shifting unit 730 includes a plurality of flip-flops 730a to 730n, and the first flip-flop 730a includes the first sub-pattern data TDTA and the second internal clock signal TCLKB. The second and second flip-flops are input with a signal output from the flip-flop of the previous stage and the second internal clock signal TCLKB.

The combiner 740 receives the first subpattern data TDTA and the second subpattern data TDTB, combines them into one pattern data TDT, and outputs the output signal TDT of the pattern generator 611. As output. The combiner 740 may be configured as a multiplexer that combines the first and second pattern data TDTA and TDTB into one.

8 is a timing diagram of signals of the pattern generator 611 illustrated in FIG. 7. As shown in FIG. 8, the frequencies of the first and second internal clock signals TCLKA and TCLKB are lowered to half the frequency of the external clock signal TCLK, and the pattern data TDT is the first sub-pattern data. TDTA and second sub-pattern data TDTB. At this time, the first sub-pattern data TDTA is generated in synchronization with the rising edge of the first internal clock signal TCLKA, and the second sub-pattern data TDTB is generated from the second internal clock signal TCLKB. It is generated in synchronization with the rising edge of.

9 is a block diagram according to a first embodiment of the communication error detection apparatus 623 shown in FIG. Referring to FIG. 9, the communication error detecting apparatus 623 includes a signal separator 910, two seed aligners 921 and 922, and an output unit 930.

The signal separator 910 receives a signal RX, and outputs two sub-pattern data TDTRA and TDTRB from the pattern data TDTR included in the signal RX, that is, the first and second sub-pattern data TDTRA. , TDTRB) is extracted and output. The signal separator 910 includes a clock divider 9102 and a demultiplexer 911. The clock divider 912 separates the external clock signal DCLK into two internal clock signals DCLKA and DCLKB, for example, first and second internal clock signals DCLKA and DCLKB. At this time, the frequencies of the first and second internal clock signals DCLKA and DCLKB are lowered to half of the frequency of the external clock signal DCLK. The demultiplexer 911 separates the pattern data TDTR input from the outside into two sub-pattern data TDTRA and TDTRB, for example, first and second sub-pattern data TDTRA and TDTRB. That is, the demultiplexer 911 inputs the first and second internal clock signals DCLKA and DCLKB, and outputs the first sub pattern data TDTRA in synchronization with the first internal clock signal DCLKA. The second sub pattern data TDTRB is output in synchronization with the internal clock signal DCLKB.

Two seed aligners 921 and 922 receive one of the first and second subpattern data TDTRA and TDTRB, respectively, and detect a transmission error of the input subpattern data. The first seed aligner 921 of the two seed aligners 921 and 922 receives the first sub-pattern data TDTRA and the first internal clock signal DCLKA and is synchronized with the first internal clock signal DCLKA. When the transmission error of the first sub pattern data TDTRA is detected, the second seed aligner 922 receives the second sub pattern data TDTRB and the second internal clock signal DCLKB and receives the second internal clock signal ( In synchronization with DCLKB, a transmission error of the second subpattern data TDTRB is detected. The first and second seed aligners 921, 922 may each have the apparatus 123 shown in FIG. 2. That is, the first and second seed aligners 921 and 922 respectively reference the control logic unit 123A for outputting the control clock signal CLKO under the control of an external signal and in synchronization with the control clock signal CLKO. The reference data generator 220 for outputting the data RDT and the pattern data TDTR and the reference data RDT are input, and the sequence of the pattern data TDTR and the reference data RDT are initially input. After performing the matching initial data setting operation, an error detection unit 123C for detecting an error in the pattern data TDTR is provided.

The output unit 930 combines and outputs transmission errors ERA and EBR output from the first and second seed aligners 921 and 922. The output unit 930 includes a multiplexer 931 which combines and outputs transmission errors ERA and ERB output from the first and second seed aligners 921 and 922, and the first and second ones. And a flag signal generator 932 for combining and outputting the flag signals FLGA and FLGB output from the seed aligners 921 and 922 into one.

As described above, the communication error detecting apparatus 623 includes two seed aligners 921 and 922, and the pattern data TDTR included in the received signal RX is divided into two sub-pattern data TDTRA and TDTRB. ) And detects a transmission error (ER) included in the two sub-pattern data TDTRA and TDTRB in a state where the frequency is lowered by dividing the external clock signal DCLK into two.

10A and 10B are timing diagrams of signals of the communication error detection apparatus shown in FIG.

As shown in Fig. 10A, the pattern data TDTR input to the communication detection device 623 is separated into two sub-pattern data TDTRA and TDTRB.

In addition, as shown in FIG. 10B, the flag signal FLG output from the communication detection device 623 includes the flag signal FLGA output from the first seed aligner 921 and the second seed aligner 922. The flag signal FLGB is output from the combined signal, and the error signal ER output from the output unit 930 is the error signal ERA output from the first seed aligner 921 and the second seed aligner. The error signal ERB output from 922 is a combined signal.

As described above, the communication error detection device 623 separates and processes the pattern data TDTR into two sub-pattern data TDTRA and TDTRB, thereby lowering the data processing speed of the communication error detection device 623 by twice. The error bit of the pattern data TDTR can be stably detected.

FIG. 11 is a block diagram illustrating a second embodiment of the pattern generator illustrated in FIG. 6. Referring to FIG. 11, the pattern generator 611 includes a clock divider 1110, a pattern generator 1120, a shifting unit 1130, and a coupling unit 1140.

The clock divider 1110 receives an external clock signal TCLK and generates four internal clock signals TCLKA to TCLKD, for example, first to fourth internal clock signals TCLKA to TCLKD. At this time, the frequencies of the first to fourth internal clock signals TCLKA to TCLKD are lowered to half of the frequency of the external clock signal TCLK.

The pattern generator 1 generates the first sub-pattern data TDTA after the first internal clock signal TCLKA is input and shifted. The pattern generator () may be comprised of linear feedback shifter registers that produce specific pattern data.

The shifting unit 1130 receives the first sub-pattern data TDTA and the second to fourth internal clock signals TCLKB to TCLKD, and is synchronized with the second to fourth internal clock signals TCLKB to TCLKD. The first sub pattern data TDTA is shifted to generate second to fourth sub pattern data TDTB TDTD. The shifting unit 1130 includes three flip-flop groups 1131 to 1133. In the first flip-flop group 1131, the first sub-pattern data TDTA and the second internal clock signal TCLKA are input and are synchronized with the second internal clock signal TCLKA to shift the first sub-pattern data TDTA. To generate the second sub-pattern data TDTB, and the second flip-flop group 1132 receives the second sub-pattern data TDTB and the third internal clock signal TCLKC and receives the third internal clock signal TCLKC. The second sub-pattern data TDTB is shifted to generate the third sub-pattern data TDTC, and the third flip-flop group 1133 includes the third sub-pattern data TDTC and the fourth internal clock. The signal TCLKD is input and is synchronized with the fourth internal clock signal TCLKD to shift the third sub pattern data TDTC to generate the fourth sub pattern data TDTD. Each of the first to third flip-flop groups 1131 to 1133 includes a plurality of flip-flops.

The combiner 1140 receives the first to fourth sub-pattern data TDTA to TDTD, combines them into one pattern data TDT, and outputs the output signal TDT of the pattern generator 611. The combiner 1140 may be configured as a multiplexer that combines the first to fourth pattern data TDTA to TDTD into one.

12 is a timing diagram of signals of the pattern generator 611 illustrated in FIG. 11. As shown in FIG. 12, the frequencies of the first to fourth internal clock signals TCLKA to TCLKD are lowered to half of the frequencies of the external clock signal TCLK, respectively. The pattern data TDT includes all of the first to fourth sub-pattern data TDTA to TDTD.

FIG. 13 is a block diagram according to the second embodiment of the communication error detection apparatus 623 of the present invention shown in FIG. Referring to FIG. 13, the communication error detecting apparatus 623 includes a signal separator 1310, four seed aligners 1211 to 1214, and an output unit 1330.

The signal separation unit 1310 receives the received signal RX, separates the pattern data TDTR included in the signal RX into four, that is, the first to fourth subpattern data TDTRA to TDTRD. Extract it and print it out. The signal separator 1310 includes a clock divider 1312 and a demultiplexer 1311. The clock divider 1312 divides the external clock signal DCLK into four internal clock signals DCLKA to DCLKD, for example, the first to fourth internal clock signals DCLKA to DCLKD. At this time, the frequencies of the first to fourth internal clock signals DCLKA to DCLKD are lowered to half of the frequencies of the external clock signal DCLK. The demultiplexer 1311 outputs the pattern data TDTR input from the outside into four sub-pattern data TDTRA to TDTRD, for example, the first to fourth sub-pattern data TDTRA to TDTRD. That is, the demultiplexer 1311 outputs the first sub pattern data TDTRA in synchronization with the first internal clock signal DCLKA, and outputs the second sub pattern data TDTRB in synchronization with the second internal clock signal DCLKB. The third sub-pattern data TDTRC is output in synchronization with the third internal clock signal DCLKC, and the fourth sub-pattern data TDTRD is output in synchronization with the fourth internal clock signal TCLKD.

Each of the four seed aligners 1211 to 1214 receives one of four sub pattern data TDTRA to TDTRD and one of four internal clock signals DCLKA to DCLKD, respectively. One of four error signals ERA to ERD and one of four flag signals FLGA to FLGD are detected. That is, the first seed aligner 1211 detects an error of the first sub-pattern data TDTRA in synchronization with the first internal clock signal DCLKA, and the second seed aligner 1212 detects the second internal clock signal. An error of the second sub-pattern data TDTRB is detected in synchronization with the DCLKB, and the third seed aligner 1213 is an error of the third sub-pattern data TDTRC in synchronization with the third internal clock signal DCLKC. The fourth seed aligner 1214 detects an error of the fourth sub pattern data TDTRD in synchronization with the fourth internal clock signal DCLKD.

The first to fourth seed aligners 1211 to 1214 may have the apparatus 123 shown in FIG. 2, respectively.

The output unit 1330 combines and outputs the error signals ERA to EBR output from the first to fourth seed aligners 1211 to 1214 as one. The output unit 1330 is a multiplexer 1331 for combining and outputting the error signals ERA to ERD output from the first to fourth seed aligners 1211 to 1214 into one, and the first to fourth ones. And a flag signal generator 1332 which combines and outputs the flag signals FLGA to FLGD output from the fourth seed aligners 1211 to 1214.

As described above, the communication error detecting apparatus 623 includes four seed aligners 1211 to 1214, separates the pattern data TDTR into four sub-pattern data TDTRA to TDTRD, and an external clock. The transmission error contained in the four subpattern data TDTRA to TDTRD is detected in the state where the signal DCLK is divided into four and the frequency is lowered.

14A and 14B are timing diagrams of the signals shown in FIG.

As shown in Fig. 14A, the pattern data TDTR input to the communication error detection device 623 is separated into four sub-pattern data TDTRA to TDTRD.

In addition, as shown in FIG. 14B, the flag signal FLG output from the communication error detection device 623 is flag signals FLGA to FLGD output from the first to fourth seed aligners 1211 to 1214. ) Are combined into one, and the error signal ER output from the communication error detection device 623 includes error signals ERA to ERD output from the first to fourth seed aligners 1211 to 1214. It is a signal combined into one.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary and will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (19)

In the communication error detection device provided in a receiver for receiving and processing a transmission signal transmitted from a transmitter,
Receives a flag signal, a reset signal and an external clock signal, outputs a control clock signal for a predetermined period of the external clock signal upon activation of the reset signal, deactivates after the predetermined period passes, and controls the activation of the flag signal. A control logic section for outputting a clock signal;
A reference data generator which receives the control clock signal and outputs reference data; And
Receives the pattern data, the reset signal, the external clock signal, the reference data, the control clock signal included in the transmission signal, and the sequence and the sequence of the pattern data during the predetermined period when the reset signal is activated Perform an initial data setting operation for matching the sequence of reference data, and activate the flag signal when the sequence of the pattern data and the sequence of the reference data match, and the pattern data and the reference data are activated during activation of the flag signal. An error detection unit for comparing and detecting an error of the pattern data,
The control logic section
A counter for receiving the reset signal and the external clock signal and outputting a counter enable signal activated during the predetermined period when the reset signal is activated;
A first logic unit configured to receive the counter enable signal and the flag signal and output a clock enable signal that is activated when any one of the counter enable signal and the flag signal is activated; And
And a second logic unit configured to receive the clock enable signal and the external clock signal and to output the control clock signal in synchronization with the external clock signal when the clock enable signal is activated. Detection device. delete The method of claim 1, wherein the control logic unit,
The flag signal output from the error detection unit, the reset signal and the external clock signal provided from the outside are input,
When the reset signal is activated, the control clock signal is output in synchronization with the external clock signal during the predetermined period.
And not outputting the control clock signal after the predetermined period, and outputting the control clock signal again when the flag signal is activated after the initial data setting operation is terminated. The method of claim 1, wherein the reference data generating unit,
And a linear feedback shift register configured to generate the reference data in response to the control clock signal. The method of claim 1, wherein the error detection unit,
A pattern data shifting unit configured to input the pattern data and to shift the pattern data and output in parallel in units of bits;
A reference data shifting unit configured to input the reference data and to shift the reference data and output in parallel in units of bits;
Compares the sequence of the pattern data and the sequence of the reference data during the predetermined period, compares bits output from the pattern data shifting unit with bits output from the reference data shifting unit during activation of the flag signal, and A data comparing unit which outputs an error signal if there are bits that do not match as a result of the comparison; And
And a third logic unit for activating the flag signal when the sequence of the pattern data and the sequence of the reference data match each other. In the communication error detection device provided in a receiver for receiving and processing a transmission signal transmitted from a transmitter,
A pattern data separator for separating a plurality of pattern data included in the transmission signal into a plurality;
A plurality of seed aligners, each of which receives one of the plurality of pattern data and detects an error of the input pattern data; And
And an output unit for combining the error signals outputted from the plurality of seed aligners and outputting them as a transmission error signal of the transmission signal.
Each of the plurality of seed aligners,
Receives a flag signal, a reset signal and an external clock signal, outputs a control clock signal for a predetermined period of the external clock signal upon activation of the reset signal, deactivates after the predetermined period passes, and controls the activation of the flag signal. A control logic section for outputting a clock signal;
A reference data generator which receives the control clock signal and outputs reference data; And
Receives the pattern data, the reset signal, the external clock signal, the reference data, the control clock signal included in the transmission signal, and the sequence and the sequence of the pattern data during the predetermined period when the reset signal is activated Perform an initial data setting operation for matching the sequence of reference data, and activate the flag signal when the sequence of the pattern data and the sequence of the reference data match, and the pattern data and the reference data are activated during activation of the flag signal. And an error detection unit for comparing and detecting an error of the pattern data.
The control logic section
A counter for receiving the reset signal and the external clock signal and outputting a counter enable signal activated during the predetermined period when the reset signal is activated;
A first logic unit configured to receive the counter enable signal and the flag signal and output a clock enable signal that is activated when any one of the counter enable signal and the flag signal is activated; And
And a second logic unit configured to receive the clock enable signal and the external clock signal and to output the control clock signal in synchronization with the external clock signal when the clock enable signal is activated. Detection device. The method of claim 6, wherein the pattern data separator,
A clock divider configured to receive the external clock signal, generate a plurality of internal clock signals, and output a frequency of the plurality of internal clock signals lower than a frequency of the external clock signal; And
And a demultiplexer configured to input the pattern data and the plurality of internal clock signals and to separate and output the plurality of pattern data in synchronization with the plurality of internal clock signals. delete The method of claim 6, wherein the output unit,
A multiplexer for combining the error signals outputted from the plurality of seed aligners and outputting the combined error signals as the transmission error signal; And
And a flag signal generator for combining a plurality of flag signals outputted from the plurality of seed aligners and outputting one flag signal. The method of claim 6,
The pattern data separator divides and outputs the pattern data into two,
And the plurality of seed aligners are configured as two, and the two seed aligners each input one of the two pattern data. The method of claim 6,
The pattern data separator divides and outputs the pattern data into four pieces,
And the plurality of seed aligners are configured as four, and the four seed aligners each input one of the four pattern data. A transmitter including a pattern generator for generating and outputting specific pattern data, and a transmitter for transmitting a transmission signal including the pattern data; And
A receiver for receiving the transmission signal;
The receiver includes a communication error detection device,
The communication error detection device,
Receives a flag signal, a reset signal and an external clock signal, outputs a control clock signal for a predetermined period of the external clock signal upon activation of the reset signal, deactivates after the predetermined period passes, and controls the activation of the flag signal. A control logic section for outputting a clock signal;
A reference data generator which receives the control clock signal and outputs reference data; And
Initially receiving the pattern data, the reset signal, the external clock signal, the reference data, the control clock signal, and matching the sequence of the pattern data and the sequence of the reference data during the predetermined period when the reset signal is activated. And performing a data setting operation, activating the flag signal when the sequence of the pattern data and the sequence of the reference data match, and comparing the pattern data with the reference data during activation of the flag signal to correct an error of the pattern data. An error detection unit for detecting;
The control logic unit,
A first counter receiving the reset signal and the external clock signal and outputting a counter enable signal activated during the predetermined period when the reset signal is activated;
A first logic unit configured to receive the counter enable signal and the flag signal and output a clock enable signal that is activated when any one of the counter enable signal and the flag signal is activated; And
And a second logic unit configured to receive the clock enable signal and the external clock signal and output the control clock signal in synchronization with the external clock signal when the clock enable signal is activated. . The method of claim 12, wherein the receiver,
And a second counter for counting an error of the transmission signal output from the communication error detection device. The method of claim 12,
And the pattern generator of the transmitter and the reference data generator of the receiver have the same structure. A transmitter including a pattern generator for generating a plurality of sub-pattern data and outputting pattern data combining the plurality of sub-pattern data into one, and a transmitter for transmitting a transmission signal including the pattern data output from the pattern generator ; And
A receiver for receiving the transmission signal;
The receiver includes a communication error detection device,
The communication error detection device,
A pattern data separator configured to input the pattern data, and separate the pattern data into the plurality of sub pattern data;
A plurality of seed aligners, each of which receives one of the plurality of sub pattern data and detects an error of the input sub pattern data; And
And an output unit for combining the error signals outputted from the plurality of seed aligners and outputting the transmission error signal of the transmission signal.
Each of the plurality of seed aligners,
Receives a flag signal, a reset signal and an external clock signal, and outputs a control clock signal for a predetermined period of the external clock signal when the reset signal is activated, deactivated after the predetermined period, and the control when the flag signal is activated. A control logic section for outputting a clock signal;
A reference data generator which receives the control clock signal and outputs reference data; And
Receives the pattern data, the reset signal, the external clock signal, the reference data, the control clock signal included in the transmission signal, and the sequence and the sequence of the pattern data during the predetermined period when the reset signal is activated Perform an initial data setting operation for matching the sequence of reference data, and activate the flag signal when the sequence of the pattern data matches the sequence of the reference data, and during the activation of the flag signal, the pattern data and the reference data And an error detection unit for comparing and detecting an error of the pattern data.
The control logic section
A counter for receiving the reset signal and the external clock signal and outputting a counter enable signal activated during the predetermined period when the reset signal is activated;
A first logic unit configured to receive the counter enable signal and the flag signal and output a clock enable signal that is activated when any one of the counter enable signal and the flag signal is activated; And
And a second logic unit configured to receive the clock enable signal and the external clock signal and to output the control clock signal in synchronization with the external clock signal when the clock enable signal is activated. . The method of claim 15, wherein the pattern generator of the transmitter,
A clock divider configured to receive an external clock signal, generate a plurality of internal clock signals, and output a frequency of the plurality of internal clock signals lower than a frequency of the external clock signal;
A pattern generator to which one of the plurality of internal clock signals is input and to generate one sub pattern data of the plurality of sub pattern data;
Among the plurality of internal clock signals, all internal clock signals which are not input to the pattern generator and sub pattern data output from the pattern generator are input, and the input sub pattern data is synchronized with the input one or more clock signals. A shifting unit which shifts to generate and output one or more subpattern data; And
And a combiner for combining the sub-pattern data output from the pattern generator and one or more sub-pattern data output from the shifting unit into one and outputting the pattern data as pattern data of the pattern generator. delete The method of claim 15,
And the plurality of sub pattern data generated by the pattern generator of the transmitter and the plurality of reference data generated by the reference data generator of the plurality of seed aligners have the same data sequence. The method of claim 15,
The number of the plurality of sub-pattern data generated in the pattern generator of the transmitter and the number of the plurality of seed aligner is the same.

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