JP2005286129A - COMPOUND SEMICONDUCTOR SUBSTRATE WITH p-n JUNCTION - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate, whereby semiconductor element deterioration in the electrical characteristics of which is less than that of prior arts is manufactured. <P>SOLUTION: The compound semiconductor substrate includes a p-n junction comprising a p-layer and an n-layer, and at least one InGap layer between the p-layer and the n-layer. The InGap layer is not ordered and its carrier concentration is lower than 1×10<SP>17</SP>cm<SP>-3</SP>. In the manufacturing method of the compound semiconductor substrate, the p-layer, the n-layer and the disordered InGap layer between the p-layer and the n-layer are grown on an original substrate. The disordered InGap layer is grown at a growing temperature range of 450°C or higher and 600°C or lower, by using a gas amount of trimethyl gallium (TMG), trimethyl indium (TMI), and phosphin, equivalent to the amount x within a range of 0.45≤x≤0.55 in the formula In<SB>x</SB>Ga<SB>1-x</SB>P. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a compound semiconductor substrate having a pn junction and a manufacturing method thereof.

  A compound semiconductor substrate having a pn junction is used for manufacturing semiconductor elements such as a field effect transistor (FET), a laser diode (LD), a photodiode (PD), and a rectifier diode.

  It is generally known that electrical characteristics such as rectification characteristics and amplification factors of semiconductor elements manufactured using a semiconductor substrate having a pn junction decrease with time as current is applied. Therefore, there is a demand for a compound semiconductor substrate that provides a semiconductor element with little deterioration in electrical characteristics.

  As a compound semiconductor substrate that provides a semiconductor element with a lower electrical characteristic than before, there is a compound semiconductor substrate having a band gap between pn junctions and an ordered InGaP layer that is a layer that serves as a barrier for holes. Although it has been proposed (see, for example, Patent Document 1), prevention of deterioration of electrical characteristics has not been sufficient. Even if another intermediate layer is present between the p layer and the n layer forming the pn junction, such as the ordered InGaP layer, any one of the layers between the p layer and the n layer is present. If the pn junction function of bonding of electrons and holes is expressed at the position, the junction between the p layer and the n layer through the intermediate layer is referred to as a pn junction.

JP 2001-250939 A

  An object of the present invention is to provide a compound semiconductor substrate that provides a semiconductor device with less deterioration in electrical characteristics than in the past.

In order to solve the above problems, the present inventors have intensively studied a pn junction of a compound semiconductor substrate having a pn junction. As a result, a layer made of InGaP is provided between the pn junctions, and the InGaP is ordered. The compound semiconductor substrate becomes a compound semiconductor substrate that gives a semiconductor element with lower electrical characteristics than the conventional one when the carrier concentration is less than 1 × 10 ¹⁷ cm ^−3. It came to complete.

That is, the present invention is a compound semiconductor substrate having a pn junction and at least one layer made of InGaP between the pn junction, the InGaP is not ordered, and the carrier concentration of the InGaP is 1 × 10 Provided is a compound semiconductor substrate characterized by being less than ¹⁷ cm ⁻³ .

  The use of the compound semiconductor substrate of the present invention makes it possible to produce a semiconductor device with less deterioration in electrical characteristics due to use than before, and the present invention is extremely useful industrially.

The compound semiconductor substrate of the present invention has a pn junction and at least one layer made of InGaP sandwiched between the pn junctions, the InGaP is not ordered, and the carrier concentration of the InGaP is 1 × 10 It is characterized by being less than ¹⁷ cm ⁻³ .

  Here, the pn junction means any one of a pn junction of a diode, two pn junctions of a pnp junction of a transistor, and two pn junctions of an npn junction of a transistor. In the present invention, the pn junction is a diode pn junction. When the pn junction is a pn junction between the base and the collector in the npn junction of the transistor, the compound semiconductor substrate of the present invention tends to give a semiconductor element in which the electrical characteristics are particularly less deteriorated than before.

The unordered layer provided between the pn junctions and made of InGaP has the formula (1)
In _x Ga _1-x P (0 <x <1) (1)
And a layer in which In atoms and Ga atoms are randomly arranged on the crystal lattice. And when x is less than 0.45 or more than 0.55, it is known that the InGaP layer is not ordered. When x is 0.45 or more and 0.55 or less, the range of the energy gap value A (eV) depends on x, and the formula (2)
2.28−0.8x ≦ A ≦ 2.33−0.8x (2)
Since it is not ordered when it is in the range represented by formula (3)
2.29−0.8x ≦ A ≦ 2.31−0.8x (3)
More preferably, the range is represented by The energy gap can be measured by photoluminescence, and the value of the energy gap is measured as the peak energy of photoluminescence.

In the InGaP layer of the present invention, the carrier concentration is less than 1 × 10 ¹⁷ cm ⁻³ . When the carrier concentration is in this range, a compound semiconductor substrate having a pn junction and at least one layer made of InGaP sandwiched between the pn junctions gives a semiconductor element with lower electrical characteristics than before. The carrier of the InGaP layer is less than 1 × 10 ¹⁷ cm ⁻³ regardless of the carrier polarity (whether the carrier is an electron or a hole), and the carrier concentration of the InGaP layer is preferably low, preferably Is 1 × 10 ¹⁶ cm ⁻³ or less.

The pn junction is made of InGaP, is not ordered, and other than the InGaP layer of the present invention in which the carrier concentration is less than 1 × 10 ¹⁷ cm ⁻³ , in the range not impairing the object of the present invention. However, it is preferable that only the InGaP layer of the present invention is disposed between the pn junctions.

  The compound semiconductor substrate of the present invention can be produced by a known method using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or the like. The compound semiconductor substrate may be any of LD, PD, rectifier diode, FET, junction field effect transistor (JFET) and the like as long as it has a pn junction.

When the compound semiconductor substrate of the present invention is manufactured, it can be manufactured by growing a p layer and an n layer and an InGaP layer between the p layer and the n layer on the original substrate. When the unordered InGaP layer is manufactured by the MOCVD method, 0.45 ≦ x ≦ in the formula (1) using each gas of trimethylgallium (TMG), trimethylindium (TMI), and phosphine as starting materials. An amount of 0.55 is used, and if necessary, a gas such as disilane as a Si source serving as a dopant capable of increasing the carrier concentration is added to each of the above gases so that the carrier concentration is less than 1 × 10 ¹⁷ cm ⁻³ . It can manufacture by adding the quantity adjusted so that it may become and making it grow in the temperature range of 450 degreeC or more and 600 degrees C or less. When the growth temperature exceeds 600 ° C., the generated InGaP layer tends to be ordered. When the growth temperature is lower than 450 ° C., the growth rate becomes slow and industrial production becomes difficult.

  Hereinafter, an exemplary embodiment of the present invention will be described in detail with reference to the drawings. This drawing is only an example of the present invention, and the present invention is not limited to the element structure shown in this drawing.

FIG. 1 is a structural diagram of a compound semiconductor substrate 10 having a layer that becomes a pn junction, showing an example of an embodiment of a semiconductor material according to the present invention.
In FIG. 1, 1 is a semi-insulating GaAs base substrate, 2 is a buffer layer, and 3 is an n ⁺ -AlGaAs layer. The n ⁺ -AlGaAs layer top, there are i-InGaP layer 5, p ⁺ -GaAs layer 4 is laminated thereon. The following description will be made assuming that the compound semiconductor substrate 10 is manufactured using the MOCVD method.

In the compound semiconductor substrate 10, the target Al amount, carrier concentration, and film thickness of the n ⁺ -AlGaAs layer 3 are 0.25, 3 × 10 ¹⁸ cm ⁻³ , and 150 μm, respectively. The growth temperature is 650 ° C., trimethylaluminum, trimethylgallium (TMG), and arsine (AsH ₃ ) are used, and disilane is used as a carrier dopant material. The target carrier concentration and film thickness of the p ⁺ -GaAs layer 4 are 4 × 10 ¹⁹ cm ⁻³ and 800 mm, respectively. The growth temperature is 510 ° C., TMG and AsH ₃ are used as raw materials, and CBrCl ₃ is used as dopant starting materials. The In composition of the unordered i-InGaP layer 5 inserted between the layers 3 and 4 is x = 0.48 in the formula (1) and the film thickness is 400Å. The layer 7 can be grown at about 550 ° C. at which In and Ga are not ordered, using trimethylindium, TMG, and AsH ₃ as starting materials and without flowing a gas serving as a carrier dopant material. The buffer layer 2 is made of a multilayer containing AlGaAs for the purpose of taking in impurities.

  EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples, but the present invention is not limited thereto.

Example 1
The epitaxial substrate shown in FIG. 1 was produced by the following procedure. The GaAs substrate 1 cleaned with an alkaline solution was mounted on an epitaxial film manufacturing apparatus, and the substrate surface was cleaned in an AsH ₃ gas atmosphere at about 700 ° C. Next, on the GaAs substrate 1, a layer including an AlGaAs layer was grown as a buffer layer at about 650 ° C. at 650 ° C. Next, the n ⁺ -AlGaAs layer 3 was grown at 650 ° C., and the temperature was set to 550 ° C. to grow the i-InGaP (where x = 0.48 in the formula (1)) layer 5. Under this growth condition, the band gap of InGaP was measured by photoluminescence, and as a result, it was 1.92 eV (the range of formula (2) was 1.90 ≦ A ≦ 1.95), and there was no regularity in the arrangement of In and Ga. It became a so-called disordered state. A p ⁺ -GaAs layer 4 was grown thereon at 510 ° C.

Comparative Example 1
The epitaxial substrate shown in FIG. 1 was produced under the same conditions as in Example 1 except that an i-InGaP (x = 0.48 in Formula (1)) layer 5 was grown at 620 ° C. At this time, the band gap of InGaP was measured by photoluminescence to be 1.86 eV (the range of the formula (2) is 1.90 ≦ A ≦ 1.95), and In and Ga are regularly arranged, so-called ordering. It became a state.

A pn junction element 11 having a layer structure shown in FIG. 2 was produced using the compound semiconductor substrate produced in Example 1 and Comparative Example 1. First, the p ⁺ -GaAs layer 4 was etched with phosphoric acid, leaving a portion with a diameter of about 130 μm. Etching stops on the i-InGaP layer 5 due to selectivity. Next, AuGe, Ni, and Au are vapor-deposited in this order on the n-electrode 6 having an outer periphery of about 10 μm from the outer periphery of the remaining p ⁺ -GaAs layer 4 and annealed at about 400 ° C. The ohmic contact with the n ⁺ -AlGaAs layer 3 below the i-InGaP layer 5 was formed by alloying. Next, a circular p-electrode 7 having an outer periphery of about 10 μm from the outer periphery of the remaining p ⁺ -GaAs layer 4 was prepared by depositing AuZn and Au in this order. This electrode became an ohmic electrode without annealing.

Changes in the forward characteristics of the pn junction element shown in FIG. 2 fabricated using the compound semiconductor substrate of Example 1 and Comparative Example 1 before and after the application of the current stress are shown in FIGS. 3 and 4, respectively. In the element using the compound semiconductor substrate of Example 1, a current of 2.8 kA / cm ² at 9.5 V, and in the element using the compound semiconductor substrate of Comparative Example 1, it is 2.4 kA / at 9.5 V. A current of cm ² was applied in the forward direction for 60 minutes to apply current stress. Comparing before and after current stress application, in the element using the substrate of Comparative Example 1, the current-voltage curve before and after application of current stress increases the amount of current at low voltage, and leakage current is applied when voltage is applied in the reverse bias direction. Can be seen. That is, it can be seen that leakage occurs in the barrier of the diode due to the pn junction, and the rectification characteristics are deteriorated. On the other hand, in the element using the substrate of Example 1, there is no change in the current-voltage curve before and after the application of the current stress, and no reverse leakage current is generated, so that the rectification characteristics are not deteriorated. I understand.

The layer structure figure of the epitaxial substrate which shows an example of embodiment of this invention. The cross-section figure of the pn junction element produced using the epitaxial substrate of this invention. FIG. 6 is a diagram of forward current-voltage characteristics of a pn junction element using the compound semiconductor substrate of Example 1, and shows changes in current-voltage characteristics before and after application of current stress. It is a forward direction current-voltage characteristic view of the pn junction element using the compound semiconductor substrate of the comparative example 1, Comprising: The figure which shows the change of the current-voltage characteristic applied before and after current stress application.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 Buffer layer 3 n ^<+> -AlGaAs layer 4 p ^<+> -GaAs layer 5 i-InGaP layer 6 n electrode 7 p electrode 8 p ⁺ -GaAs layer 9 left circularly by etching 10 Alloying part 10 of n electrode Compound semiconductor substrate 11 Diode

Claims (4)

A compound semiconductor substrate having at least one InGaP layer between a pn junction and the pn junction, the InGaP is not ordered, and the carrier concentration of the InGaP is less than 1 × 10 ¹⁷ cm ⁻³ A compound semiconductor substrate characterized in that: The range of the energy gap value A (eV) of the layer made of InGaP is expressed by the formula In _x Ga _1-x P
Using x in
2.28−0.8x ≦ A ≦ 2.33−0.8x
(However, 0.45 ≦ x ≦ 0.55)
The compound semiconductor substrate according to claim 1, which is in a range represented by:   2. The method of manufacturing a compound semiconductor substrate according to claim 1, wherein a p layer, an n layer, and an unordered InGaP layer are grown between the p layer and the n layer on the original substrate. The unordered InGaP layer is added in amounts such that trimethylgallium (TMG), trimethylindium (TMI), and phosphine are 0.45 ≦ x ≦ 0.55 in the formula In _x Ga _1-x P. The growth method according to claim 3, wherein the growth temperature is in the range of 450 ° C to 600 ° C.

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