JP2005286079A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing current leaks, decreasing the number of erroneous operations, and reducing power consumption. <P>SOLUTION: A voltage source 11a applies a potential higher than that of an n<SP>+</SP>diffusion layer 41c to the p<SP>+</SP>diffusion layer 43c of the cell to be driven. This causes a current to flow to a thin-film resistor 30c for the production of heat. A voltage source 11b applies a potential higher than the potential of the p<SP>+</SP>diffusion layer 43 to the n<SP>+</SP>diffusion layers 41 of the cells other than the cell to be driven. A voltage source 12 applies a negative potential to a p-substrate 50. No current leak occurs because the bias between the n<SP>+</SP>diffusion layers 41 of the cells other than the cell to be driven, and the p<SP>+</SP>diffusion layer 43 is reverse to the bias between the n<SP>-</SP>diffusion 42 and the p-substrate 50. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a heat generating semiconductor device used as a drive circuit such as a waveguide type optical switch, and more particularly to a semiconductor device in which current wraparound is improved between elements constituting the semiconductor device.

  A thin film heater has been proposed as a heating element used for heating a minute region. An integrated semiconductor device in which cells including a plurality of thin film heaters are arranged in a matrix is applied to a waveguide type optical switch for an optical communication system. Hereinafter, application examples of the semiconductor device to the waveguide type optical switch will be described.

  A waveguide type optical switch is an element that switches an optical path serving as a communication path in an optical communication system. In a waveguide type optical switch, a plurality of optical waveguides arranged in the row direction intersect with a plurality of optical waveguides arranged in the column direction, and a groove is provided at the intersection, and the above-described heating element is disposed above the groove. ing. A liquid having a refractive index similar to that of the core portion of the optical waveguide is injected into the groove. When this liquid is at the intersection, light passing through the optical waveguide passes through the liquid and travels straight through the same optical waveguide. Further, when the liquid is energized and heated by the heat generating element, the liquid moves from the intersection, and the air moves to the intersection where the liquid disappears. In this state, the light passing through the optical waveguide is totally reflected by the wall surface of the groove and travels through the other optical waveguide. The optical path is switched as described above.

  FIG. 6 is a top view of a semiconductor device used for the waveguide type optical switch described above. In addition, each structure in a figure is drawn with the block diagram for the simplification. The same applies to the drawings used in the following description. In the figure, 1 is a row power line, and 2 is a column power line. 3 is a thin film heater which generates heat by Joule heating during energization. The intersecting portion of the row power line 1 and the column power line 2 is multi-layered so that they do not intersect. When a certain voltage is applied between the specific row power line 1 and the column power line 2, a current flows through the thin film heater 3 connected to both, and the thin film heater 3 generates heat.

  However, in the semiconductor device shown in FIG. 6, a reverse current flows through the thin film heaters 3 other than the thin film heater 3 to be driven corresponding to the row power line 1 and the column power line 2 to which the potential is applied. For example, it is assumed that a potential difference is applied between the row power line 1b and the column power line 2b so that a current flows through the thin film heater 3e. In this case, a current in the direction opposite to that of the thin film heater 3e may also flow into the thin film heater 3a, 3c, 3g, 3i, or the like.

  FIG. 7 is a top view of the semiconductor device in which the reverse current is improved. In the figure, 4 is a diode, which prevents current from flowing in the opposite direction. When a positive potential is applied to a specific row power line 1 and a potential lower than that of the row power line 1 is applied to the column power line 2, power is supplied to the corresponding thin film heater 3, and the thin film heater 3 generates heat. To do.

In the semiconductor device applied to the waveguide type optical switch described above, the length of one side of the unit cell is about 250 μm. Patent Document 1 describes a waveguide type optical switch that uses a heating element as a drive source.
JP 2000-244610 A

  In the conventional semiconductor device, the thin film heater and the diode are arranged in a matrix as shown in FIG. 7 in order to prevent a current from flowing into a thin film heater other than the desired thin film heater among the thin film heaters arranged in a matrix. Was arranged. This structure can be realized by arranging a plurality of single diodes. However, in the application example to the waveguide type optical switch, the distance between the thin film heaters is as narrow as about 250 μm, so that the diode structure is formed on the semiconductor substrate. Need to be realized by integrating.

An integrated diode structure is shown in FIG. This structure is formed as follows. An N ⁻ diffusion layer 42 having a depth of several μm is formed on a P ⁻ substrate 50 made of a P-type single crystal, and an N ⁺ diffusion layer 41 and a P ⁺ diffusion layer 43 are formed in this region. The N ⁻ diffusion layer 42 is a low concentration diffusion region, and the N ⁺ diffusion layer 41 and the P ⁺ diffusion layer 43 are high concentration diffusion regions. The N ⁺ diffusion layer 41, the N ⁻ diffusion layer 42, and the P ⁺ diffusion layer 43 constitute a diode. Subsequently, a thin film heater is formed on the P ⁺ diffusion layer 43 (or N ⁺ diffusion layer 41). In the figure, reference numeral 12 denotes a thin film resistor indicating the resistance of the thin film heater. The thin film resistors 30 adjacent in the row (or column) direction are connected by wiring in the row direction, and the N ⁺ diffusion layers 41 (or P ⁺ diffusion layers 43) adjacent in the column (or row) direction are connected in the column direction. Connect with. In the figure, 60 is a field oxide film for a protective film, and 11 is a voltage source for applying a voltage to the thin film resistor 30. Reference numeral 12 denotes a substrate bias voltage source which maintains a reverse bias between the P ⁻ substrate 50 and the N ⁻ diffusion layer 42 to prevent current from flowing.

  FIG. 9 is a top view of the semiconductor device having the above diode structure. In the figure, in order to apply a voltage to a desired thin film heater 3, a positive voltage is applied to the row power line 1 to which the thin film heater 3 is connected, and the column power line 2 to which the thin film heater 3 is connected. Ground. For example, when a voltage is applied to the row power line 1b and the column power line 2b is grounded, a current flows through the thin film heater 3e and the diode 4e. However, in this case, there is a problem that current flows around the adjacent thin film heaters 3d and 3f and the power consumption increases.

Hereinafter, the cause of the current wraparound (leakage current) will be described. FIG. 10 is a cross-sectional view of a conventional semiconductor device having a diode structure. In a process for forming a semiconductor device, an ionic substance such as sodium may be mixed. As another example, in a process for manufacturing a waveguide type optical switch, glass containing sodium is bonded to a semiconductor device by anodic bonding and then covered. When an ionic substance such as sodium generated by these steps enters and contaminates the field oxide film 60, the inversion layer 100 is formed immediately below the field oxide film 60 between the adjacent N ⁻ diffusion layers 42. Because it is the same polarity as the charge of the diffusion layer 42, N ^{- -} charge in the inversion layer 100 is N current flows to the diffusion layer 42.

This current causes the parasitic transistor to conduct, and a parasitic transistor current is generated. The generation of parasitic transistor current will be described with reference to FIG. When the inversion layer 100 is generated as shown in FIG. 10, a current flows between the collector C1 and the emitter E1 of the parasitic bipolar transistor 201 composed of the N ⁻ diffusion layer 42, the P 2 ⁻ substrate 50, and the N 2 ⁻ diffusion layer 42. Subsequently, a current flows through the base B2 of the parasitic bipolar transistor 202 including the P ⁺ diffusion layer 43, the N ⁻ diffusion layer 42, and the P ⁻ substrate 50, and the parasitic bipolar transistor 202 becomes conductive. As a result, a current flows through the base B1 of the parasitic bipolar transistor 201, and the parasitic bipolar transistor 201 becomes conductive (thyristor operation).

  When the current sneak occurs as described above, there is a problem that a plurality of sneak currents 301 are generated in addition to the main current 300 as shown in FIG. As a result, the semiconductor device provided with the above-described thin film heater not only heats only a desired specific part, but also malfunctions that other parts are heated by a sneak current. There is also a problem that power consumption increases due to a sneak current.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device capable of preventing leakage current and reducing malfunction and power consumption.

  The present invention has been made to solve the above-described problems. The invention according to claim 1 is directed to an N-type first region formed on a main surface of a P-type semiconductor substrate, and the first region. A plurality of cells including a diode formed of a P-type second region and an N-type third region formed on the surface, and a current driving element having one end connected to the second region or the third region; In the first case where the one end is connected to the second region, the other ends of the plurality of current driving elements are connected, and in the second case where the one end is connected to the third region. Is a first that applies a potential higher than the potential of the third region of the cell to be driven to the signal line connecting the plurality of second regions and the signal line connected to the cell to be driven. And in the first case, connected to the signal line, excluding the cell to be driven A potential is applied to the third region of the plurality of cells, and in the second case, the other end of the current driving element of the plurality of cells connected to the signal line, excluding the cell to be driven And a third means for applying a potential to the semiconductor substrate. The potential applied to the third region by the second means is the first means. The semiconductor device is characterized in that the potential applied to the second region by the means is higher and the potential applied by the third means is lower than the potential of the third region in the cell to be driven.

  According to a second aspect of the present invention, a P-type first region formed on a main surface of an N-type semiconductor substrate, a P-type second region formed on the surface of the first region, and an N-type first region A plurality of cells including a diode composed of three regions, the second region or a current driving element having one end connected to the third region, and the first end connected to the second region. In the second case, the other ends of the plurality of current drive elements are connected, and the one end is connected to the third region. In the second case, the signal lines connecting the plurality of second regions and driving are connected. First means for applying a potential higher than the potential of the third region of the cell to be driven to the signal line connected to the target cell; and in the first case, A potential is applied to the third region of the plurality of cells connected to the signal line excluding the cell, and the first region In the case of 2, the second means for applying a potential to the other end of the current driving element of the plurality of cells connected to the signal line, excluding the driving target cell, and the semiconductor substrate And the third means for applying a potential to the third region by the second means is lower than the potential applied to the second region by the first means. The semiconductor device is characterized in that the potential applied by the means is higher than the potential of the third region in the cell to be driven.

  According to a third aspect of the present invention, an N-type first region formed on a main surface of a P-type semiconductor substrate, a P-type second region formed on a surface of the first region, and an N-type first region A plurality of cells including a diode composed of three regions and the second region or a current driving element having one end connected to the third region; and formed on the main surface between the adjacent first regions. In the first case where the high-concentration P-type fourth region and the one end are connected to the second region, the other ends of the plurality of current driving elements are connected, and the one end is the third In the second case of being connected to a region, the third of the cell to be driven is connected to the signal line connecting the plurality of first regions and the signal line connected to the cell to be driven. A first means for applying a potential higher than the potential of the region, and a potential of the third region relative to the fourth region; A semiconductor device comprising: a second means for applying a low potential; and a third means for applying a potential lower than the potential of the third region to the semiconductor substrate.

  According to a fourth aspect of the present invention, there is provided a P-type first region formed on the main surface of the N-type semiconductor substrate, a P-type second region formed on the surface of the first region, and an N-type first region. A plurality of cells including a diode composed of three regions and the second region or a current driving element having one end connected to the third region; and formed on the main surface between the adjacent first regions. In the first case where the high-concentration N-type fourth region and the one end are connected to the second region, the other ends of the plurality of current driving elements are connected, and the one end is the third In the second case of being connected to a region, the third of the cell to be driven is connected to the signal line connecting the plurality of first regions and the signal line connected to the cell to be driven. A first means for applying a potential higher than the potential of the region, and the potential of the second region relative to the fourth region; A semiconductor device comprising: a second means for applying a high potential; and a third means for applying a potential higher than the potential of the second region to the semiconductor substrate.

  According to a fifth aspect of the present invention, an N-type layer formed on a main surface of a high-concentration P-type semiconductor substrate, a P-type first region and an N-type layer formed on the surface of the N-type layer A plurality of cells each including a diode formed of a second region and a current driving element having one end connected to the first region or the second region; and between the adjacent cells in the N-type layer In a first case where a high-concentration P-type third region formed so as to connect the surface of the N-type layer and the main surface, and the one end connected to the first region, In the second case where the other ends of the plurality of current driving elements are connected and the one end is connected to the second region, a signal line connecting the plurality of first regions and a cell to be driven are connected. First means for applying a potential higher than a potential of the second region of the cell to be driven to the connected signal line. , With respect to the semiconductor substrate, a semiconductor device characterized by comprising a second means for providing a potential lower than the potential of the second region.

  According to a sixth aspect of the present invention, a P-type layer formed on a main surface of a high-concentration N-type semiconductor substrate, a P-type first region formed on the surface of the P-type layer, and an N-type A plurality of cells including a diode composed of a second region and a current driving element having one end connected to the first region or the second region; and between the adjacent cells in the P-type layer In a first case where a high-concentration P-type third region formed so as to connect the surface of the N-type layer and the main surface, and the one end connected to the first region, In the second case where the other ends of the plurality of current driving elements are connected and the one end is connected to the second region, a signal line connecting the plurality of first regions and a cell to be driven are connected. First means for applying a potential higher than a potential of the second region of the cell to be driven to the connected signal line. , With respect to the semiconductor substrate, a semiconductor device characterized by comprising a second means for providing a potential higher than the potential of the first region.

  According to a seventh aspect of the present invention, in the semiconductor device according to any one of the first to sixth aspects, the current driving element is an element that generates heat due to Joule heat during energization. .

  According to the present invention, it is possible to obtain an effect of preventing leakage current and reducing malfunction and power consumption.

The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention. In this semiconductor device, a voltage is applied so that other PN junctions except the PN junction to be energized are reverse-biased in order to prevent current from flowing. In FIG. 1, a diode composed of an N ⁺ diffusion layer 41, an N ⁻ diffusion layer 42 c, and a P ⁺ diffusion layer 43 and the thin film resistor 30 constitute one cell. A voltage source 11a applies a voltage to a cell to be driven. Reference numeral 11b denotes a voltage source that applies a reverse bias voltage to the N ⁺ diffusion layers 41b, 41d, and 41e in the other cells excluding the cell to be driven in order to prevent a sneak current. A voltage source 12 applies a negative voltage to the P ⁻ substrate 50.

By a voltage source 11a, the potential of the ^{P +} diffusion layer 43c is higher than the potential of the ^{N +} diffusion layer 41c, the bias for the PN junction between the ^{P +} diffusion layer 43c and the ^{N +} diffusion layer 41c becomes forward biased. Thereby, a current flows through the thin film resistor 30c, and heat is generated. A voltage is applied from the voltage source 11b to the N ⁺ diffusion layers 41b, 41d, and 41e in the other cells excluding the cell to be driven. The relationship between the potential V ₁ of the P ⁺ diffusion layer 43 and the potential V ₂ of the N ⁺ diffusion layer 41 of other cells excluding the cell to be driven is V ₁ <V ₂ . In other cells excluding the cell to be driven, the bias between the N ⁺ diffusion layer 41 and the P ⁺ diffusion layer 43 is a reverse bias, and thus a leakage current between the N ⁺ diffusion layer 41 and the P ⁺ diffusion layer 43. Does not occur.

Also, P ^- since the negative voltage to the substrate 50 is applied, P ^- relationship between the potential _{V 4} of the ^{N +} diffusion layer 41c in potential _{V 3} and the driving target cell substrate _{50, V} 3 < V is _4. Relationship between the potential _{V 1} of the N ⁺ diffusion layer 41c potential _{V 4} in a ^{P +} diffusion layer 43 _{is V} 4 <V _1. Accordingly, since the bias between the N ⁻ diffusion layer 42 and the P 2 ⁻ substrate 50 is a reverse bias, no leakage current is generated between the N 2 ⁻ diffusion layer 42 and the P 2 ⁻ substrate 50. Note that the voltage applied to the P ⁻ substrate 50 is not limited to a negative voltage, as long as the relationship of V ₃ <V ₄ is satisfied.

Note that an N ⁻ substrate may be used instead of the P ⁻ substrate 50 as the semiconductor substrate. In that case, a P ⁻ diffusion layer is used instead of the N ⁻ diffusion layer 42. The P ⁺ diffusion layer in the cell to be driven is biased so that the potential of the P ⁺ diffusion layer is higher than the potential of the N ⁺ diffusion layer, and a current flows through the thin film resistor to be driven. Further, the potential of the N ⁺ diffusion layer in other cells excluding the cell to be driven is biased so as to be higher than the potential of the P ⁺ diffusion layer, so that the potential of the N ⁻ substrate is higher than the potentials of all the N ⁺ diffusion layers. Also biased to be higher.

  FIG. 2 is a top view of the semiconductor device and the external control circuit. In the figure, reference numeral 13 denotes a PMOS which is a P-type MOS (Metal Oxide Semiconductor) transistor. Reference numeral 14 denotes an NMOS which is an N-type MOS transistor. A control unit 15 applies voltage to the gate electrodes of the PMOS 13 and the NMOS 14 and controls on / off of the PMOS 13 and the NMOS 14. Reference numeral 70 denotes a diode array including the thin film heater 3 and the diode 4.

  The PMOS 13 and the NMOS 14 are arranged in pairs. In the paired PMOS 13 and NMOS 14, the drain electrode is shared and connected to the row power line 1 or the column power line 2. A positive voltage is applied to the source electrode of the PMOS 13 and the source electrode of the NMOS 14 is grounded. The gate electrodes of the PMOS 13 and the NMOS 14 are common and are connected to the control unit 15.

  The operation when energizing a specific thin film heater 3, for example, the thin film heater 3f, is as follows. The controller 15 applies a zero voltage to the gate electrodes of the PMOS 13b and NMOS 14b, and applies a positive voltage to the gate electrodes of the PMOS 13f and NMOS 14f. As a result, the PMOS 13b is turned on, the NMOS 14b is turned off, and a positive voltage is applied to the row power line 1b. Further, the PMOS 13f is turned off, the NMOS 14f is turned on, and the column power line 2c is grounded. Therefore, a current flows through the thin film heater 3f and the diode 4f.

  The control unit 15 applies a positive voltage to the gate electrodes of the PMOSs 13a and 13c and the NMOSs 14a and 14c, and applies a zero voltage to the gate electrodes of the PMOSs 13d and 13e and the NMOSs 14d and 14e. As a result, the PMOSs 13a and 13c are turned off, the NMOSs 14a and 14c are turned on, and a negative voltage is applied to the row power lines 1a and 1c. Further, the PMOSs 13d and 13e are turned on, the NMOSs 14d and 14e are turned off, and a positive voltage is applied to the column power lines 2a and 2b. Therefore, since a reverse bias voltage is applied to the other diodes 4 except the diode 4f in the cell to be driven, no current flows through these diodes 4 and the thin film heater 3 connected thereto.

Next, a second embodiment of the present invention will be described. FIG. 3 is a sectional view showing a sectional structure of the semiconductor device according to the second embodiment. In this semiconductor device, a P ⁺ diffusion layer 80 is provided between adjacent N ⁻ diffusion layers 42. The P ⁺ diffusion layer 80 prevents the inversion layer from being formed so as to straddle between the adjacent N ⁻ diffusion layers 42. The P ⁺ diffusion layer 80 is a P-type diffusion layer in which impurities (acceptors) such as boron are diffused at a high concentration. The impurity concentration is desirably 10 ¹⁸ / cm ³ or more.

3, the voltage source 11a, ^{P +} potential of the diffusion layer 43b is higher than the potential of the ^{N +} diffusion layer 41b, the bias for the PN junction between the ^{P +} diffusion layer 43b and the ^{N +} diffusion layer 41b is sequentially It becomes a bias. Thereby, a current flows through the thin film resistor 30b and heat is generated. No voltage is applied to the N ⁺ diffusion layer 41a, and the N ⁺ diffusion layer 41a is in an open state. Note that the N ⁺ diffusion layer 41a is preferably in an open state or in a state where a potential higher than the potential of the P ⁺ diffusion layer 43 is applied.

Due to the voltage source 11b, the potential of the N ⁺ diffusion layer 41b becomes higher than the potential of the P ⁺ diffusion layer 80. As a result, the PN junction between the N ⁺ diffusion layer 41b and the P ⁺ diffusion layer 80 is reverse-biased. Therefore, no leakage current is generated between the N ⁺ diffusion layer 41 b and the P ⁺ diffusion layer 80. A P ⁺ diffusion layer 80 is provided between adjacent N ⁻ diffusion layers 42. The P ⁺ diffusion layer 80 prevents the inversion layer from being formed so as to straddle between the adjacent N ⁻ diffusion layers 42 and prevents the parasitic bipolar transistor from conducting accidentally.

Further, since a negative voltage is applied to the P ⁻ substrate 50 by the voltage source 12, the potential of the N ⁻ diffusion layer 42 becomes higher than the potential of the P ⁻ substrate 50. As a result, the bias between the N ⁻ diffusion layer 42 and the P ⁻ substrate 50 is a reverse bias. Accordingly, no leakage current is generated between the N ⁻ diffusion layer 42 and the P ⁻ substrate 50. Incidentally, P ^- although a negative voltage relative to the substrate 50 is applied, P ^- need only be lower than the potential of the potential of the substrate 50 is N ⁺ diffusion layer 41, the voltage applied to the P ⁺ substrate 51 It is not limited to negative voltage.

Note that an N ⁻ substrate may be used instead of the P ⁻ substrate 50 as the semiconductor substrate. In that case, a P ⁻ diffusion layer is used instead of the N ⁻ diffusion layer 42. The P ⁺ diffusion layer in the cell to be driven is biased so that the potential of the P ⁺ diffusion layer is higher than the potential of the N ⁺ diffusion layer, and a current flows through the thin film resistor to be driven. Further, an N ⁺ diffusion layer is used instead of the P ⁺ diffusion layer 80, and the N ⁺ diffusion layer is biased so that the potential of the N ⁺ diffusion layer is higher than the potential of the P ⁺ diffusion layer. Further, the N ⁻ substrate potential is biased to be higher than the P ⁺ diffusion layer potential.

Next, a third embodiment of the present invention will be described. FIG. 4 is a sectional view showing a sectional structure of the semiconductor device according to the third embodiment. In the figure, 44a and 44b are N ^- epi layers, which are formed by epitaxial growth. Reference numeral 51 denotes a high-concentration P-type P ⁺ substrate. Reference numeral 81 denotes a P ⁺ separation diffusion layer, which is formed between adjacent N ⁻ diffusion layers 44. The impurity concentrations of the P ⁺ substrate 51 and the P ⁺ isolation diffusion layer 81 are desirably 10 ¹⁸ / cm ³ or more.

The structure of this semiconductor device is formed as follows. First, the N ⁻ epi layer 44 is formed on the P ⁺ substrate 51 by epitaxial growth. Subsequently, high concentration diffusion regions of the N ⁺ diffusion layer 41 and the P ⁺ diffusion layer 43 are formed in the N ⁻ epi layer 44. Further, a high concentration P ⁺ isolation diffusion layer 81 is formed in the N ⁻ epi layer 44. At this time, the P ⁺ isolation diffusion layer 81 and the P ⁺ substrate 51 are formed so as to be directly connected. Subsequently, a thin film heater is formed on the high concentration diffusion region of the P ⁺ diffusion layer 43 (or N ⁺ diffusion layer 41). N ⁺ diffusion layer 41, P ⁺ diffusion layer 43, and N ⁻ epi layer 44 constitute a diode.

The operation of this semiconductor device is as follows. By a voltage source 11, the potential of the ^{P +} diffusion layer 43b is higher than the potential of the ^{N +} diffusion layer 41b, the bias for the PN junction between the ^{P +} diffusion layer 43b and the ^{N +} diffusion layer 41b becomes forward biased. Thereby, a current flows through the thin film resistor 30b and heat is generated. No voltage is applied to the N ⁺ diffusion layer 41a, and the N ⁺ diffusion layer 41a is in an open state. Note that the N ⁺ diffusion layer 41a is preferably in an open state or in a state where a potential higher than the potential of the P ⁺ diffusion layer 43 is applied.

Each diode is isolated by the P ⁺ isolation diffusion layer 81. The P ⁺ isolation diffusion layer 81 is connected to the P ⁺ substrate 51, and a negative voltage is applied by the voltage source 12. As a result, the potential of the N ⁺ diffusion layer 41 becomes higher than the potential of the P ⁺ substrate 51. That N ^- potential of the epitaxial layer 44 is higher than the potential of the ^{P +} substrate 51, N ^- bias between the epitaxial layer 44 and the ^{P +} substrate 51 is reverse biased. Accordingly, no leakage current is generated between the N ⁻ epi layer 44 and the P ⁺ substrate 51.

Since the P ⁺ isolation diffusion layer 81 has a high impurity concentration, it can be prevented that an inversion layer is formed on the surface thereof. The P ⁺ isolation diffusion layer 81 corresponds to the base of a parasitic bipolar transistor including the N ⁻ epi layer 44a, the P ⁺ isolation diffusion layer 81, and the N ⁻ epi layer 44b. Since the impurity concentration of the base is high and the width is wide, the parasitic bipolar transistor is prevented from conducting accidentally.

Incidentally, with respect to ^{P +} substrate 51, but a negative voltage is applied by the voltage source 12, need only be the potential of the ^{P +} substrate 51 is lower than the potential of the ^{N +} diffusion layer 41, ^{P +} substrate The voltage applied to 51 is not limited to a negative voltage.

Note that an N ⁺ substrate may be used instead of the P ⁺ substrate 51 as the semiconductor substrate. In that case, N ^- the epitaxial layer ^- P instead of the epitaxial layer 44. The P ⁺ diffusion layer in the cell to be driven is biased so that the potential of the P ⁺ diffusion layer is higher than the potential of the N ⁺ diffusion layer, and a current flows through the thin film resistor to be driven. Further, the N ⁺ substrate is biased so that the potential of the N ⁺ substrate becomes higher than the potential of the P ⁻ epi layer.

  FIG. 5 is a top view of the semiconductor device and the external control circuit according to the third embodiment. In the figure, a positive voltage is applied to the source electrode of the PMOS 13, and the drain electrode is connected to the row power line 1. The source electrode of the NMOS 14 is grounded, and the drain electrode is connected to the column power line 2. The gate electrodes of the PMOS 13 and NMOS 14 are connected to the control unit 15.

  The operation when energizing a specific thin film heater 3, for example, the thin film heater 3f, is as follows. The controller 15 applies a zero voltage to the gate electrode of the PMOS 13b, and applies a positive voltage to the gate electrode of the NMOS 14c. As a result, the PMOS 13b is turned on, and a positive voltage is applied to the row power line 1b. Further, the NMOS 14c is turned on, and the column power line 2c is grounded. Therefore, a current flows through the thin film heater 3f and heat is generated.

  The control unit 15 applies a positive voltage to the gate electrodes of the PMOSs 13a and 13c. Thereby, PMOSs 13a and 13c are turned off, and no voltage is applied to row power lines 1a and 1c. The control unit 15 also grounds the gate electrodes of the NMOSs 14a and 14b. As a result, the NMOSs 14a and 14b are turned off, and no voltage is applied to the column power lines 2a and 2b. With the structure of FIG. 4, no leakage current flows through the other thin film heaters 3 and diodes 4 except the thin film heater 3f and the diode 4f to be driven. According to the above configuration, the external circuit can be simplified.

  As described above, according to the first to third embodiments, it is possible to prevent a leakage current from being generated in a thin film heater other than the thin film heater to be driven. Therefore, malfunctions and power consumption associated with leakage current can be reduced.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings, but the specific configuration is not limited to these embodiments, and includes design changes and the like within a scope not departing from the gist of the present invention. It is.

  As an application example of the present invention, the above-described waveguide type optical switch can be cited. Further, it can be applied to a driving circuit of a liquid crystal display whose color and deflection are changed by heat.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a top view of the semiconductor device and the external control circuit according to the same embodiment. It is sectional drawing of the semiconductor device by the 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device by the 3rd Embodiment of this invention. FIG. 3 is a top view of the semiconductor device and the external control circuit according to the same embodiment. It is a top view of the conventional semiconductor device. It is a top view of the conventional semiconductor device provided with the diode. It is sectional drawing of the conventional semiconductor device provided with the diode. It is a top view of the conventional semiconductor device provided with the diode structure. It is sectional drawing of the semiconductor device for demonstrating current wraparound in the conventional semiconductor device provided with the diode structure. It is sectional drawing of the semiconductor device for demonstrating generation | occurrence | production of the parasitic transistor current in the conventional semiconductor device provided with the diode structure. It is sectional drawing of the semiconductor device for demonstrating current wraparound in the conventional semiconductor device provided with the diode structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a-1d ... Row power line, 2, 2a-2c ... Column power line, 3, 3a-3i ... Thin film heater, 4, 4a-4i ... Diode, 11, 11a, 11b, 12 ... Voltage source, 13, 13a to 13f ... PMOS, 14, 14a to 14f ... NMOS, 15 ... Control unit, 30, 30a to 30d ... Thin film resistor, 41, 41a to 41e ·· ^{N +} diffusion layer, 42,42a~42e ··· N ^- diffusion layer, 43,43a~43d ··· ^{P +} diffusion layer, 44,44a, 44b ··· N ^- epitaxial layer, 50 ... P ^- substrate, 51 ... P ⁺ substrate, 60 ... field oxide film, 70 ... diode array, 80 ... P ⁺ diffusion layer, 81 ... P ⁺ isolation diffusion layer.

Claims (7)

A diode comprising an N-type first region formed on a main surface of a P-type semiconductor substrate, and a P-type second region and an N-type third region formed on the surface of the first region; A plurality of cells including a current driving element having one end connected to the second region or the third region;
In the first case where the one end is connected to the second region, the other ends of the plurality of current drive elements are connected, and in the second case where the one end is connected to the third region. A plurality of signal lines connecting the second regions;
First means for applying a potential higher than the potential of the third region of the cell to be driven to the signal line connected to the cell to be driven;
In the first case, a potential is applied to the third region of a plurality of cells connected to the signal line excluding the cell to be driven, and in the second case, the drive target cell A second means for applying a potential to the other end of the current driving elements of a plurality of cells connected to the signal line, excluding cells;
A third means for applying a potential to the semiconductor substrate;
Comprising
The potential applied to the third region by the second means is higher than the potential applied to the second region by the first means;
The semiconductor device, wherein the potential applied by the third means is lower than the potential of the third region in the cell to be driven. A diode comprising a P-type first region formed on a main surface of an N-type semiconductor substrate, and a P-type second region and an N-type third region formed on the surface of the first region; A plurality of cells including a current driving element having one end connected to the second region or the third region;
In the first case where the one end is connected to the second region, the other ends of the plurality of current drive elements are connected, and in the second case where the one end is connected to the third region. A plurality of signal lines connecting the second regions;
First means for applying a potential higher than the potential of the third region of the cell to be driven to the signal line connected to the cell to be driven;
In the first case, a potential is applied to the third region of a plurality of cells connected to the signal line excluding the cell to be driven, and in the second case, the drive target cell A second means for applying a potential to the other end of the current driving elements of a plurality of cells connected to the signal line, excluding cells;
A third means for applying a potential to the semiconductor substrate;
Comprising
The potential applied to the third region by the second means is lower than the potential applied to the second region by the first means,
The semiconductor device, wherein the potential applied by the third means is higher than the potential of the third region in the cell to be driven. A diode comprising an N-type first region formed on a main surface of a P-type semiconductor substrate, and a P-type second region and an N-type third region formed on the surface of the first region; A plurality of cells including a current driving element having one end connected to the second region or the third region;
A high-concentration P-type fourth region formed on the main surface between the adjacent first regions;
In the first case where the one end is connected to the second region, the other ends of the plurality of current drive elements are connected, and in the second case where the one end is connected to the third region. A plurality of signal lines connecting the first regions;
First means for applying a potential higher than the potential of the third region of the cell to be driven to the signal line connected to the cell to be driven;
A second means for applying a potential lower than the potential of the third region to the fourth region;
Third means for applying a potential lower than the potential of the third region to the semiconductor substrate;
A semiconductor device comprising: A diode comprising a P-type first region formed on a main surface of an N-type semiconductor substrate, and a P-type second region and an N-type third region formed on the surface of the first region; A plurality of cells including a current driving element having one end connected to the second region or the third region;
A high-concentration N-type fourth region formed on the main surface between the adjacent first regions;
In the first case where the one end is connected to the second region, the other ends of the plurality of current drive elements are connected, and in the second case where the one end is connected to the third region. A plurality of signal lines connecting the first regions;
First means for applying a potential higher than the potential of the third region of the cell to be driven to the signal line connected to the cell to be driven;
Second means for applying a higher potential to the fourth region than the potential of the second region;
A third means for applying a potential higher than the potential of the second region to the semiconductor substrate;
A semiconductor device comprising: A diode comprising an N-type layer formed on a main surface of a high-concentration P-type semiconductor substrate, and a P-type first region and an N-type second region formed on the surface of the N-type layer; A plurality of cells including a current driving element having one end connected to the first region or the second region;
A high-concentration P-type third region formed so as to connect the surface of the N-type layer and the main surface between the adjacent cells in the N-type layer;
In the first case where the one end is connected to the first region, the other ends of the plurality of current drive elements are connected, and in the second case where the one end is connected to the second region. A plurality of signal lines connecting the first regions;
First means for applying a potential higher than the potential of the second region of the cell to be driven to the signal line connected to the cell to be driven;
Second means for applying a potential lower than the potential of the second region to the semiconductor substrate;
A semiconductor device comprising: A diode comprising a P-type layer formed on the main surface of a high-concentration N-type semiconductor substrate, and a P-type first region and an N-type second region formed on the surface of the P-type layer; A plurality of cells including a current driving element having one end connected to the first region or the second region;
A high-concentration P-type third region formed so as to connect the surface of the N-type layer and the main surface between the adjacent cells in the P-type layer;
In the first case where the one end is connected to the first region, the other ends of the plurality of current drive elements are connected, and in the second case where the one end is connected to the second region. A plurality of signal lines connecting the first regions;
First means for applying a potential higher than the potential of the second region of the cell to be driven to the signal line connected to the cell to be driven;
A second means for applying a potential higher than the potential of the first region to the semiconductor substrate;
A semiconductor device comprising: The semiconductor device according to claim 1, wherein the current driving element is an element that generates heat due to Joule heat during energization.

Images