JP2005285994A - Surface-mounted multiple capacitor - Google Patents

Surface-mounted multiple capacitor Download PDF

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JP2005285994A
JP2005285994A JP2004095957A JP2004095957A JP2005285994A JP 2005285994 A JP2005285994 A JP 2005285994A JP 2004095957 A JP2004095957 A JP 2004095957A JP 2004095957 A JP2004095957 A JP 2004095957A JP 2005285994 A JP2005285994 A JP 2005285994A
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capacitor
capacitor elements
internal electrodes
laminate
dielectric layers
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Hisashi Sato
恒 佐藤
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Kyocera Corp
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Kyocera Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a surface-mounted multiple capacitor that can effectively prevent the occurrence of short circuits between solder adhered to terminal electrodes even when the size of the whole structure of the capacitor is reduced by narrowing the interval between adjacent capacitor elements and is excellent in mountability. <P>SOLUTION: The surface-mounted multiple capacitor is manufactured by forming a rectangular parallelepiped laminate by laminating many dielectric layers upon another and, at the same time, arranging n-pieces (wherein, n is a natural number of ≥2) of capacitor elements formed by respectively interposing a plurality of internal electrodes between adjacent dielectric layers in a row in the direction of lamination of the dielectric layers, and sticking the terminal electrodes provided correspondingly to the capacitor elements to the side faces of the laminate. The terminal electrodes are commonly connected to the outer peripheral sections of the internal electrodes positioned to the central areas of the capacitor elements, at least, near the mounting surface of the laminate. At the same time, the internal electrodes positioned to the central areas and both end areas of the capacitor elements are electrically connected to each other at portions of the side faces of the laminate separated from the mounting surface. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、マザーボード等の外部配線基板上に表面実装された上、携帯電話機等の各種電子機器に組み込まれる表面実装型多連コンデンサに関するものである。   The present invention relates to a surface-mounted multiple capacitor that is surface-mounted on an external wiring board such as a mother board and is incorporated into various electronic devices such as a mobile phone.

従来より、各種電子機器に組み込まれる電子部品として、内部に複数個のコンデンサ素子を備えた表面実装型の多連コンデンサが用いられている。   2. Description of the Related Art Conventionally, surface mount multiple capacitors each having a plurality of capacitor elements have been used as electronic components incorporated into various electronic devices.

かかる従来の多連コンデンサとしては、例えば図5に示す如く、チタン酸バリウム等から成る多数の誘電体層22を積層してなる積層体21の内部に、複数個のコンデンサ素子24a,24b,24cを配設するとともに、積層体21の側面に各コンデンサ素子24a,24b,24cと対応する一対の端子電極25を被着させた構造のものが知られている(例えば、特許文献1参照。)。   As such a conventional multiple capacitor, for example, as shown in FIG. 5, a plurality of capacitor elements 24a, 24b, 24c are provided in a laminated body 21 in which a large number of dielectric layers 22 made of barium titanate or the like are laminated. And a structure in which a pair of terminal electrodes 25 corresponding to the capacitor elements 24a, 24b, and 24c are attached to the side surface of the multilayer body 21 is known (see, for example, Patent Document 1). .

前記コンデンサ素子24a,24b,24cは、複数個の誘電体層22とこれら誘電体層間22‐22に介在されている内部電極23a,23b,23cとで構成されており、これら全ての内部電極23を積層体21の下面や側面において、コンデンサ素子毎に、対応する一対の端子電極25のいずれか一方と電気的に接続させている。   The capacitor elements 24a, 24b, and 24c are composed of a plurality of dielectric layers 22 and internal electrodes 23a, 23b, and 23c interposed between the dielectric layers 22-22. Is electrically connected to either one of the corresponding pair of terminal electrodes 25 for each capacitor element on the lower surface or side surface of the multilayer body 21.

かかる従来の多連コンデンサは、一対の端子電極25を介して各コンデンサ素子24a,24b,24cの内部電極間に所定の電圧を印加し、各コンデンサ素子24a,24b,24cの内部電極間に配されている誘電体層22に所定の静電容量を形成することによって多連コンデンサとして機能する。   In such a conventional multiple capacitor, a predetermined voltage is applied between the internal electrodes of the capacitor elements 24a, 24b, and 24c via the pair of terminal electrodes 25, and is arranged between the internal electrodes of the capacitor elements 24a, 24b, and 24c. By forming a predetermined capacitance in the dielectric layer 22 that is formed, it functions as a multiple capacitor.

尚、上述した従来の多連コンデンサは、マザーボード等の外部配線基板上に従来周知の半田付け等によって表面実装されるようになっている。具体的には、上述した多連コンデンサを、端子電極25と外部配線基板の対応する接続パッドとの間にクリーム半田等が介在されるようにして外部配線基板上に載置させた後、クレーム半田を高温で加熱・溶融させて多連コンデンサの端子電極25を外部配線基板の接続パッドに半田接合させることによって多連コンデンサの実装が行われる。
特開平11−16778号公報
The conventional multiple capacitors described above are surface-mounted on an external wiring board such as a mother board by known soldering or the like. Specifically, after placing the above-described multiple capacitor on the external wiring board such that cream solder or the like is interposed between the terminal electrode 25 and the corresponding connection pad of the external wiring board, the claim The multiple capacitors are mounted by heating and melting the solder at a high temperature and soldering the terminal electrodes 25 of the multiple capacitors to the connection pads of the external wiring board.
Japanese Patent Laid-Open No. 11-16778

しかしながら、上述した従来の多連コンデンサにおいては、各コンデンサ素子の全ての内部電極が積層体の下面や側面等で対応する端子電極と電気的に接続されていることから、隣接するコンデンサ素子間の間隔を狭くして全体構造の小型化を図った場合、隣接する端子電極間の間隔も狭くなってしまう。その場合、多連コンデンサを半田付けによってマザーボード等の外部電気回路上に実装した際に、端子電極と外部配線基板の接続パッドとを接合する半田が隣の半田と接触して短絡を起こすことがあり、実装不良を招く欠点が誘発される。   However, in the conventional multiple capacitor described above, all the internal electrodes of each capacitor element are electrically connected to the corresponding terminal electrodes on the lower surface, side surface, etc. of the multilayer body. When the interval is reduced to reduce the size of the entire structure, the interval between adjacent terminal electrodes is also reduced. In that case, when multiple capacitors are mounted on an external electric circuit such as a mother board by soldering, the solder joining the terminal electrode and the connection pad of the external wiring board may contact the adjacent solder and cause a short circuit. There is a drawback that leads to mounting defects.

本発明は上記欠点に鑑み案出されたもので、その目的は、隣接するコンデンサ素子間の間隔を狭くして全体構造の小型化を図る場合であっても、端子電極に付着される半田同士の短絡を有効に防止することができる、実装性に優れた表面実装型多連コンデンサを提供することにある。   The present invention has been devised in view of the above-described drawbacks, and its purpose is to reduce the overall structure by reducing the interval between adjacent capacitor elements, so that the solder attached to the terminal electrodes can be connected to each other. It is an object of the present invention to provide a surface mount multiple capacitor excellent in mountability that can effectively prevent short circuit.

本発明の表面実装型多連コンデンサは、多数の誘電体層を積層して直方体状の積層体を形成するとともに、該積層体の内部で、隣接する誘電体層間に複数個の内部電極を1個ずつ介在させてなるn個(nは2以上の自然数)のコンデンサ素子を誘電体層の積層方向に一列状に配設し、前記積層体の側面に各コンデンサ素子と対応して設けられる端子電極を被着させてなる表面実装型多連コンデンサにおいて、前記端子電極は、前記コンデンサ素子の中央域に位置する内部電極の外周部に少なくとも前記積層体の実装面近傍で共通接続されているとともに、前記積層体側面のうち前記実装面より離間した部位でコンデンサ素子の中央域に位置する内部電極と両端域に位置する内部電極とが電気的に接続されていることを特徴とするものである。   The surface mount type multiple capacitor according to the present invention forms a rectangular parallelepiped laminate by laminating a large number of dielectric layers, and includes a plurality of internal electrodes 1 between adjacent dielectric layers within the laminate. Terminals provided corresponding to each capacitor element on the side surface of the multilayer body in which n (n is a natural number of 2 or more) capacitor elements are arranged in a line in the direction of the dielectric layer lamination. In the surface-mounted multiple capacitor formed by attaching electrodes, the terminal electrode is commonly connected to the outer peripheral portion of the internal electrode located in the central region of the capacitor element at least in the vicinity of the mounting surface of the laminate. The internal electrode located in the central area of the capacitor element and the internal electrodes located in both end areas are electrically connected to each other at a part of the side surface of the laminate that is separated from the mounting surface. .

また本発明の表面実装型多連コンデンサは、前記端子電極が、各内部電極の外周部を起点として前記積層体の表面に析出させた無電解めっき膜から成っていることを特徴とするものである。   Further, the surface mount type multiple capacitor of the present invention is characterized in that the terminal electrode is composed of an electroless plating film deposited on the surface of the laminate from the outer peripheral portion of each internal electrode. is there.

更に本発明の表面実装型多連コンデンサは、前記コンデンサ素子の中央域に位置する内部電極と両端域に位置する内部電極とを電気的に接続する連結部が、隣接するもの同士、コンデンサ素子の配列方向と直交する方向にずらして配置されていることを特徴とするものである。   Further, in the surface mount type multiple capacitor of the present invention, the connecting portion that electrically connects the internal electrode located in the central area of the capacitor element and the internal electrode located in both end areas is adjacent to each other, It is characterized by being shifted in a direction orthogonal to the arrangement direction.

本発明の表面実装型多連コンデンサによれば、コンデンサ素子の中央域に位置する内部電極を積層体の実装面付近で積層体表面の端子電極に接続するとともに、コンデンサ素子の中央域に位置する内部電極と両端域に位置する内部電極とを積層体の実装面より離間した部位で電気的に接続するようにしたことから、隣接するコンデンサ素子間の間隔を狭くして全体構造の小型化を図る場合であっても、実装面付近の端子電極の幅は中央域の幅と同等の狭い幅として隣接する端子電極間の間隔を広く確保することができる。従って、表面実装型多連コンデンサを半田付けによってマザーボード等の外部電気回路上に実装する際、端子電極と外部配線基板の接続パッドとを接合する半田が隣の半田と接触して短絡を起こすのが有効に防止されるようになる。   According to the surface mount type multiple capacitor of the present invention, the internal electrode located in the central region of the capacitor element is connected to the terminal electrode on the surface of the multilayer body in the vicinity of the mounting surface of the multilayer body and located in the central area of the capacitor element. Since the internal electrode and the internal electrode located at both end regions are electrically connected at a location separated from the mounting surface of the laminate, the interval between adjacent capacitor elements is reduced to reduce the overall structure. Even in this case, the width of the terminal electrode in the vicinity of the mounting surface can be set to a narrow width equivalent to the width of the central region, so that a wide interval between the adjacent terminal electrodes can be secured. Therefore, when a surface mount type multiple capacitor is mounted on an external electric circuit such as a mother board by soldering, the solder joining the terminal electrode and the connection pad of the external wiring board contacts the adjacent solder and causes a short circuit. Is effectively prevented.

しかも、本発明の表面実装型多連コンデンサによれば、端子電極に接続されている内部電極は積層体の実装面より離間した部位で両端域に位置する内部電極と接続されるようになっているため、外部電気回路上への実装時、溶融した半田が端子電極を伝って這い上がってきても、上述した端子電極の連結部付近まで上がってくることは少なく、隣接する端子電極の連結部同士が半田を介して短絡する恐れも殆どない。   In addition, according to the surface mount type multiple capacitor of the present invention, the internal electrode connected to the terminal electrode is connected to the internal electrode located in both end regions at a portion separated from the mounting surface of the laminate. Therefore, even when the molten solder crawls up along the terminal electrode when mounted on an external electric circuit, it rarely rises to the vicinity of the terminal electrode connecting portion described above, and the connecting portion of the adjacent terminal electrode There is almost no risk of short-circuiting each other through the solder.

また本発明の表面実装型多連コンデンサによれば、積層体表面の端子電極を、各内部電極の外周部を起点として積層体の表面に析出させた無電解めっき膜で形成することにより、内部電極の外周部を部分的に露出させておいた積層体を無電解めっき用のめっき液に所定時間浸漬しておくだけの簡単な加工によって端子電極を形成することができ、表面実装型多連コンデンサの生産性向上に供することも可能となる。   Further, according to the surface mount type multiple capacitor of the present invention, the terminal electrode on the surface of the multilayer body is formed by an electroless plating film deposited on the surface of the multilayer body starting from the outer peripheral portion of each internal electrode. The terminal electrode can be formed by simple processing by simply immersing the laminate with the outer periphery of the electrode partially exposed in a plating solution for electroless plating for a predetermined time. It is also possible to improve the productivity of the capacitor.

更に本発明の表面実装型多連コンデンサによれば、コンデンサ素子の中央域に位置する内部電極と両端域に位置する内部電極とを電気的に接続する連結部を、隣接するもの同士、コンデンサ素子の配列方向と直交する方向にずらして配置させておくことにより、外部電気回路上への実装時、仮に溶融した半田が端子電極を伝って連結部付近まで這い上がってきたとしても、隣接する連結部同士が半田を介して短絡するのを有効に防止することができる。   Furthermore, according to the surface mount type multiple capacitor of the present invention, the connecting portions that electrically connect the internal electrode located in the central area of the capacitor element and the internal electrodes located in both end areas are adjacent to each other. By disposing in a direction perpendicular to the arrangement direction of the adjacent connection, even when the solder that has been melted crawls up to the vicinity of the connection portion through the terminal electrode when mounted on the external electric circuit, the adjacent connection It is possible to effectively prevent the parts from being short-circuited via the solder.

以下、本発明を添付図面に基づいて詳細に説明する。   Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

図1は本発明の一実施形態に係る表面実装型多連コンデンサの外観斜視図、図2(a)は図1の表面実装型多連コンデンサのA−A線断面図、図2(b)は図1の表面実装型多連コンデンサのB−B線断面図、図3は図1の表面実装型多連コンデンサの分解斜視図であり、同図に示す表面実装型多連コンデンサは、内部にn個(nは2以上の自然数)のコンデンサ素子4a,4b,4cを有した積層体1の側面に、上端及び下端を積層体1の実装面及び上面まで延在させた一対の端子電極5a,5b,5cを、コンデンサ素子4a,4b,4cと対応させて被着・形成した構造を有している。尚、本実施形態においてはコンデンサ素子の個数nを「3」に設定した例について説明するものとする。   1 is an external perspective view of a surface-mounted multiple capacitor according to an embodiment of the present invention, FIG. 2A is a cross-sectional view of the surface-mounted multiple capacitor of FIG. 1, taken along line AA, and FIG. 1 is a cross-sectional view of the surface mount multi-capacitor of FIG. 1 taken along the line BB, FIG. 3 is an exploded perspective view of the surface mount multi-capacitor of FIG. 1, and the surface mount multi-capacitor shown in FIG. A pair of terminal electrodes having the upper end and the lower end extending to the mounting surface and the upper surface of the multilayer body 1 on the side surface of the multilayer body 1 having n capacitor elements 4a, 4b, and 4c (n is a natural number of 2 or more). 5a, 5b, and 5c are attached and formed corresponding to the capacitor elements 4a, 4b, and 4c. In the present embodiment, an example in which the number n of capacitor elements is set to “3” will be described.

前記積層体1は、多数の誘電体層2を積層することにより形成されており、n個のコンデンサ素子4a,4b,4cは誘電体層2の積層方向に一列状に配され、これらコンデンサ素子4a,4b,4cの形成領域には隣接する誘電体層間に内部電極3a,3bが介在されている。   The multilayer body 1 is formed by laminating a large number of dielectric layers 2, and n capacitor elements 4a, 4b, 4c are arranged in a line in the laminating direction of the dielectric layers 2, and these capacitor elements Internal electrodes 3a and 3b are interposed between adjacent dielectric layers in the formation regions of 4a, 4b and 4c.

前記誘電体層2は、例えば、チタン酸バリウム、チタン酸カルシウム、チタン酸ストロンチウム等を主成分とする誘電体材料によって1層あたり1μm〜3μmの厚みに形成されており、かかる誘電体層2を、表面実装型多連コンデンサの実装面と平行な方向に、例えば20層〜2000層だけ積層することによって積層体1が形成される。尚、図1乃至図3においては本実施形態の表面実装型多連コンデンサを簡略化して示すために誘電体層2の積層数を42層とした場合を図示している。   The dielectric layer 2 is formed to a thickness of 1 μm to 3 μm per layer by a dielectric material mainly composed of, for example, barium titanate, calcium titanate, strontium titanate, and the like. The stacked body 1 is formed by stacking, for example, 20 to 2000 layers in a direction parallel to the mounting surface of the surface-mounted multiple capacitor. FIGS. 1 to 3 show a case where the number of stacked dielectric layers 2 is 42 in order to simplify the surface-mounted multiple capacitor of this embodiment.

このような誘電体層2は、例えば、チタン酸バリウムを主成分とする誘電体材料から成る場合、チタン酸バリウムの粉末に適当な有機溶剤、ガラスフリット、有機バインダ等を添加・混合して泥漿状になすとともに、これを従来周知のドクターブレード法等によって所定形状、所定厚みのセラミックグリーンシートと成し、しかる後、得られたセラミックグリーンシートを従来周知のグリーンシート積層法等にて所定の枚数だけ積層・圧着させることによりセラミックグリーンシートから成る積層素体を形成し、最後にこの積層素体を、例えば1100℃〜1400℃の温度で焼成することによって製作される。   For example, when the dielectric layer 2 is made of a dielectric material mainly composed of barium titanate, an appropriate organic solvent, glass frit, organic binder, or the like is added to and mixed with the barium titanate powder. This is formed into a ceramic green sheet having a predetermined shape and thickness by a conventionally known doctor blade method or the like, and then the obtained ceramic green sheet is predetermined by a conventionally known green sheet laminating method or the like. A laminated body made of ceramic green sheets is formed by laminating and press-bonding the same number of sheets, and finally the laminated body is manufactured by firing at a temperature of 1100 ° C. to 1400 ° C., for example.

一方、前記積層体1の内部で、各コンデンサ素子4a,4b,4cの形成領域に配設されている多数の内部電極3a,3bは、間に誘電体層2を介して交互に配置される第1の内部電極3aと第2の内部電極3bとで構成されており、隣接する第1の内部電極3a及び第2の内部電極3bは間に誘電体層2を介して一部が対向するように配置させてあるため、第1の内部電極3aと第2の内部電極3bとの間に電圧が印加されると、両者の対向領域で所定の静電容量が発生するようになっている。   On the other hand, a large number of internal electrodes 3a, 3b disposed in the formation regions of the capacitor elements 4a, 4b, 4c are alternately disposed with the dielectric layer 2 therebetween in the multilayer body 1. The first internal electrode 3a and the second internal electrode 3b are configured so that the first internal electrode 3a and the second internal electrode 3b adjacent to each other partially face each other with the dielectric layer 2 therebetween. Therefore, when a voltage is applied between the first internal electrode 3a and the second internal electrode 3b, a predetermined capacitance is generated in a region opposite to the first internal electrode 3a and the second internal electrode 3b. .

また、このような内部電極3a,3bのうち、各コンデンサ素子4a,4b,4cの中央域に配されている複数個の第1の内部電極3aは外周の一部が積層体1の側面まで延在された上、少なくとも積層体1の実装面(図中の下面)付近を含む部位において一方の端子電極5a,5b,5cと共通接続され、各コンデンサ素子4a,4b,4cの中央域に配されている複数個の第2の内部電極5bも外周の一部が積層体1の側面まで延在された上、少なくとも積層体1の実装面付近を含む部位において他方の端子電極5a,5b,5cに共通接続されている。   Among the internal electrodes 3 a and 3 b, the plurality of first internal electrodes 3 a arranged in the central area of the capacitor elements 4 a, 4 b and 4 c have a part of the outer periphery extending to the side surface of the multilayer body 1. In addition to being extended, it is commonly connected to one of the terminal electrodes 5a, 5b, 5c at a portion including at least the vicinity of the mounting surface (the lower surface in the drawing) of the multilayer body 1, and in the central region of each capacitor element 4a, 4b, 4c. The plurality of second internal electrodes 5b arranged also extend to the side surface of the multilayer body 1 at a part of the outer periphery, and the other terminal electrodes 5a and 5b at least in the region including the vicinity of the mounting surface of the multilayer body 1 , 5c.

そして、内部電極3a,3bのうち、コンデンサ素子4a,4b,4cの両端域に位置する内部電極5a,5bは、積層体1の側面のうち実装面より離間した部位、例えば積層体1の積層方向と直交する方向の中央付近でコンデンサ素子4a,4b,4cの中央域に位置する内部電極と端子電極5a,5bを介して電気的に接続されており、この部位(以下、連結部という。)でもってコンデンサ素子4a,4b,4cに設けられている全ての第1の内部電極3aが一方の端子電極5a,5b,5cに、全ての第2の内部電極3bが他方の端子電極5a,5b,5cに共通接続されている。   Of the internal electrodes 3a and 3b, the internal electrodes 5a and 5b located in both end regions of the capacitor elements 4a, 4b and 4c are portions of the side surface of the multilayer body 1 separated from the mounting surface, for example, the lamination of the multilayer body 1 The internal electrodes located in the central region of the capacitor elements 4a, 4b, 4c are electrically connected via the terminal electrodes 5a, 5b near the center in the direction orthogonal to the direction, and this portion (hereinafter referred to as a connecting portion). Thus, all the first internal electrodes 3a provided in the capacitor elements 4a, 4b, 4c are connected to one terminal electrode 5a, 5b, 5c, and all the second internal electrodes 3b are connected to the other terminal electrode 5a, Commonly connected to 5b and 5c.

ここで各コンデンサ素子4a,4b,4cの“中央域”、“両端域”とは各コンデンサ素子4a,4b,4cを3つの領域に区画すべく便宜上、使用している表現であって、両端からの寸法や全体の中の割合等によって決定されるものではなく、各コンデンサ素子4a,4b,4cの形成領域内において適宜決定することができるものである。即ち、各コンデンサ素子4a,4b,4cの両端より少しでも内側に位置する領域であれば、その領域を中央域ということができ、その両側の領域が両端域となる。   Here, the “central area” and “both end areas” of the capacitor elements 4a, 4b, and 4c are expressions used for convenience to divide the capacitor elements 4a, 4b, and 4c into three areas. It is not determined by the dimensions from the above, the ratio in the whole, etc., but can be appropriately determined in the formation region of each capacitor element 4a, 4b, 4c. That is, if it is a region located slightly inside both ends of each capacitor element 4a, 4b, 4c, this region can be called a central region, and both regions are both end regions.

尚、前記内部電極3a,3bは、ニッケル、銅、ニッケル/銅、銀/パラジウム等の金属を主成分とする導体材料によって、例えば0.5μm〜8.0μmの厚みに形成されており、積層体1の形成に際して用いられるセラミックグリーンシートの主面に、上述した金属材料の粉末に適当な有機溶剤、ガラスフリット、有機バインダ等を添加・混合して得た導体ペーストを従来周知のスクリーン印刷等によって所定パターンに塗布しておいたり、或いは、所定パターンのメッキ膜を被着・転写させておくことにより形成される。   The internal electrodes 3a and 3b are formed of a conductive material mainly composed of a metal such as nickel, copper, nickel / copper, silver / palladium or the like to a thickness of 0.5 μm to 8.0 μm, for example. Conductor paste obtained by adding and mixing a suitable organic solvent, glass frit, organic binder, etc. to the above-mentioned metal material powder on the main surface of the ceramic green sheet used for forming the body 1 is conventionally known screen printing, etc. It is formed by applying to a predetermined pattern or by depositing and transferring a plating film of a predetermined pattern.

一方、前記積層体1の側面等に被着されている端子電極5a,5b,5cは、表面実装型多連コンデンサをマザーボード等の外部配線基板上に実装する際、外部配線基板の接続パッドに半田等を介して電気的に接続される外部接続用の端子として機能するものであり、積層体1の実装面から側面を介して上面にかけて、被着・形成されている。   On the other hand, the terminal electrodes 5a, 5b, and 5c attached to the side surfaces of the multilayer body 1 are used as connection pads of the external wiring board when the surface mount type multiple capacitors are mounted on the external wiring board such as a mother board. It functions as a terminal for external connection that is electrically connected via solder or the like, and is deposited and formed from the mounting surface of the laminate 1 to the upper surface via the side surface.

ここで端子電極5a,5b,5cを積層体1の実装面から側面を介して上面にかけて形成するようにしているのは、表面実装型多連コンデンサをマザーボード等の外部配線基板上に実装する際、上下の方向性を考慮することなく実装作業を行うことができるようにするためであり、端子電極5a,5b,5cと外部配線基板の接続パッドとを半田接合した際、実際に半田が濡れる領域は端子電極5a,5b,5cの下部領域、例えば端子電極5a,5b,5cの下端より高さ方向の3分の1程度までの領域となる。   Here, the terminal electrodes 5a, 5b, 5c are formed from the mounting surface of the multilayer body 1 to the upper surface through the side surface when the surface mount type multiple capacitor is mounted on an external wiring substrate such as a mother board. This is so that the mounting operation can be performed without taking the vertical direction into consideration, and when the terminal electrodes 5a, 5b, 5c and the connection pads of the external wiring board are soldered, the solder actually gets wet. The region is a lower region of the terminal electrodes 5a, 5b, 5c, for example, a region from the lower end of the terminal electrodes 5a, 5b, 5c to about one third in the height direction.

なお、これらの端子電極5a,5b,5cは、例えば従来周知の無電解めっき法、具体的には、積層体1の表面に各内部電極3a,3bの外周部を起点として金属を析出させるとともに、これらの析出物同士を相互に連結させることによって形成される。上記端子電極5a,5b,5cを無電解めっき法にて形成する場合、その断面は図2(c)に示されるような形状となる。この場合、内部電極3a,3bの外周部を部分的に露出させておいた積層体1を無電解めっき用のめっき液に所定時間浸漬しておくだけの簡単な加工によって端子電極5a,5b,5cを所望するパターンに形成することができ、表面実装型多連コンデンサの生産性向上に供することが可能である。   These terminal electrodes 5a, 5b, and 5c are formed by, for example, a conventionally known electroless plating method, specifically, depositing metal on the surface of the laminate 1 starting from the outer peripheral portion of each internal electrode 3a, 3b. These precipitates are formed by interconnecting each other. When the terminal electrodes 5a, 5b, 5c are formed by electroless plating, the cross section has a shape as shown in FIG. In this case, the terminal electrodes 5a, 5b, and 5b are simply processed by simply immersing the laminate 1 in which the outer peripheral portions of the internal electrodes 3a and 3b are partially exposed in a plating solution for electroless plating for a predetermined time. 5c can be formed in a desired pattern, and can be used for improving the productivity of the surface mount type multiple capacitor.

かくして上述した表面実装型多連コンデンサは、従来周知の半田付け等によって一度の実装でn個のコンデンサ素子がマザーボード等の外部配線基板上に搭載されるようになっており、個々のコンデンサ素子4a,4b,4cに対応する一対の端子電極5a,5b,5cを介して所定の電圧を印加し、複数個の静電容量を形成することによって表面実装型多連コンデンサとして機能することとなる。   Thus, in the surface mount type multiple capacitors described above, n capacitor elements are mounted on an external wiring board such as a mother board by a single mounting by conventionally known soldering or the like, and each capacitor element 4a , 4b, 4c, a predetermined voltage is applied through a pair of terminal electrodes 5a, 5b, 5c to form a plurality of capacitances, thereby functioning as a surface mount type multiple capacitor.

以上のような本実施形態の表面実装型多連コンデンサによれば、コンデンサ素子4a,4b,4cの中央域に位置する内部電極3a,3bを積層体1の実装面付近で積層体表面の端子電極5a,5b,5cに接続するとともに、コンデンサ素子4a,4b,4cの中央域に位置する内部電極3a,3bと両端域に位置する内部電極3a,3bとを積層体1の実装面より離間した部位で相互に電気的に接続させるようにしたことから、隣接するコンデンサ素子間の間隔を狭くして全体構造の小型化を図る場合であっても、実装面付近の端子電極5a,5b,5cの幅はコンデンサ素子4a,4b,4cの中央域の幅と同等の狭い幅として隣接する端子電極間の間隔を広く確保することができる。従って、表面実装型多連コンデンサを半田付けによってマザーボード等の外部電気回路上に実装する際、端子電極5a,5b,5cと外部配線基板の接続パッドとを接合する半田が隣の半田と接触して短絡を起こすのが有効に防止されるようになる。   According to the surface mount-type multiple capacitor of the present embodiment as described above, the internal electrodes 3a and 3b located in the center area of the capacitor elements 4a, 4b and 4c are connected to the terminals on the surface of the multilayer body in the vicinity of the mounting surface of the multilayer body 1. Connected to the electrodes 5a, 5b, 5c, and the internal electrodes 3a, 3b located in the center area of the capacitor elements 4a, 4b, 4c and the internal electrodes 3a, 3b located in both end areas are separated from the mounting surface of the multilayer body 1 Even if the overall structure is downsized by narrowing the interval between adjacent capacitor elements, the terminal electrodes 5a, 5b, The width of 5c is a narrow width equivalent to the width of the central area of the capacitor elements 4a, 4b, 4c, so that a wide interval between adjacent terminal electrodes can be secured. Accordingly, when the surface mount type multiple capacitors are mounted on an external electric circuit such as a mother board by soldering, the solder that joins the terminal electrodes 5a, 5b, 5c and the connection pads of the external wiring board comes into contact with the adjacent solder. This effectively prevents a short circuit from occurring.

しかも、前記端子電極5a,5b,5cに接続されている内部電極3a,3bは積層体1の実装面より離間した部位で両端域に位置する内部電極3a,3bと接続されるようになっているため、外部電気回路上への実装時、溶融した半田が端子電極5a,5b,5cを伝って這い上がってきても、これが端子電極5a,5b,5cの連結部付近まで上がってくることは少なく、隣接する端子電極5a,5b,5cの連結部同士が半田を介して短絡する恐れも殆どない。   In addition, the internal electrodes 3a, 3b connected to the terminal electrodes 5a, 5b, 5c are connected to the internal electrodes 3a, 3b located in both end regions at a portion separated from the mounting surface of the laminate 1. Therefore, even when the molten solder crawls up along the terminal electrodes 5a, 5b, and 5c when mounted on the external electric circuit, it does not rise to the vicinity of the connecting portion of the terminal electrodes 5a, 5b, and 5c. There is little possibility that the connecting portions of the adjacent terminal electrodes 5a, 5b, and 5c are short-circuited via solder.

また上述した実施形態において、図4に示す如く、コンデンサ素子4a,4b,4cの中央域に位置する内部電極3a,3bと両端域に位置する内部電極3a,3bとを電気的に接続する連結部を、隣接するもの同士、コンデンサ素子4a,4b,4cの配列方向と直交する方向にずらして配置させておくようにすれば、表面実装型多連コンデンサを半田付けによって外部電気回路上に実装する際、溶融した半田が端子電極5a,5b,5cを伝って連結部付近まで這い上がってきたとしても、隣接する連結部の先端部同士は離れているため、この部分が半田を介して短絡してしまうのが有効に防止される。従って、コンデンサ素子4a,4b,4cの中央域に位置する内部電極3a,3bと両端域に位置する内部電極3a,3bとを電気的に接続する連結部を、隣接するもの同士、コンデンサ素子4a,4b,4cの配列方向と直交する方向にずらして配置させておくことが好ましい。   In the above-described embodiment, as shown in FIG. 4, the internal electrodes 3a, 3b located in the central area of the capacitor elements 4a, 4b, 4c and the internal electrodes 3a, 3b located in both end areas are electrically connected. If the parts are arranged so as to be shifted from each other in the direction orthogonal to the arrangement direction of the capacitor elements 4a, 4b, 4c, the surface mount type multiple capacitors are mounted on the external electric circuit by soldering. In this case, even if the molten solder crawls up to the vicinity of the connecting portion through the terminal electrodes 5a, 5b, and 5c, the tip portions of the adjacent connecting portions are separated from each other, so this portion is short-circuited via the solder. This is effectively prevented. Therefore, the connecting portions that electrically connect the internal electrodes 3a, 3b located in the center area of the capacitor elements 4a, 4b, 4c and the internal electrodes 3a, 3b located in both end areas are adjacent to each other, the capacitor element 4a. , 4b, 4c are preferably shifted in the direction perpendicular to the arrangement direction.

更に上述した実施形態において、積層体1のうち、内部電極3a,3b等が存在していない隣接するコンデンサ素子間の領域Aを、コンデンサ素子4a,4b,4cを形成している誘電体層2と同材質の誘電体材料から成る誘電体層により形成するとともに、前記領域Aを形成する誘電体材料の気孔率をコンデンサ素子4a,4b,4cを形成している誘電体材料の気孔率より大となしておくようにすれば、隣接するコンデンサ素子間の電気的干渉を良好に低減せしめ、所望する特性を備えた多連コンデンサを得ることができる。従って、積層体1のうち、内部電極3a,3b等が存在していない隣接するコンデンサ素子間の領域Aを、コンデンサ素子4a,4b,4cを形成している誘電体層2と同材質の誘電体材料から成る誘電体層により形成するとともに、前記領域Aを形成する誘電体材料の気孔率をコンデンサ素子4a,4b,4cを形成している誘電体材料の気孔率より大となしておくことが好ましい。   Furthermore, in the above-described embodiment, the dielectric layer 2 forming the capacitor elements 4a, 4b, and 4c in the region 1 between the adjacent capacitor elements in the stacked body 1 where the internal electrodes 3a and 3b and the like are not present. And the porosity of the dielectric material forming the region A is larger than the porosity of the dielectric material forming the capacitor elements 4a, 4b, 4c. As a result, it is possible to satisfactorily reduce electrical interference between adjacent capacitor elements and to obtain a multiple capacitor having desired characteristics. Therefore, in the multilayer body 1, the region A between adjacent capacitor elements in which the internal electrodes 3 a, 3 b, etc. are not present is formed in the same material as the dielectric layer 2 forming the capacitor elements 4 a, 4 b, 4 c. The dielectric layer made of a body material is used, and the porosity of the dielectric material forming the region A is made larger than the porosity of the dielectric material forming the capacitor elements 4a, 4b, 4c. Is preferred.

尚、本発明は上述した実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更、改良等が可能である。   The present invention is not limited to the above-described embodiments, and various changes and improvements can be made without departing from the scope of the present invention.

例えば、上述した実施形態において、内部電極3a,3b中に誘電体層2を形成している誘電体材料を添加・混合させておくようにしても良い。   For example, in the above-described embodiment, the dielectric material forming the dielectric layer 2 may be added and mixed in the internal electrodes 3a and 3b.

また上述した実施形態においては端子電極を無電解めっき膜により形成するようにしたが、これに代えて、導体ペーストの塗布等によって形成するようにしても構わない。   In the above-described embodiment, the terminal electrode is formed of the electroless plating film. However, instead of this, the terminal electrode may be formed by applying a conductive paste or the like.

更に上述した実施形態においては、積層体1の内部に設けられるコンデンサ素子の個数nを「3」に設定した例について説明するようにしたが、コンデンサ素子の個数nは2以上の自然数であればいくつであっても良い。   Further, in the embodiment described above, an example in which the number n of capacitor elements provided in the multilayer body 1 is set to “3” has been described. However, if the number n of capacitor elements is a natural number of 2 or more, Any number is acceptable.

また更に上述した実施形態の表面実装型多連コンデンサを、いわゆる‘複数個取り’の手法を採用し、大型積層体より切り出して形成しても良いことは言うまでもない。   Furthermore, it goes without saying that the surface mount type multiple capacitors of the above-described embodiment may be formed by cutting out from a large-sized laminate by adopting a so-called 'multiple pick-up' technique.

更にまた上述した実施形態においては、内部電極を誘電体層一層毎に交互に配設するようにしたが、本発明はそのような形態に限定されるものではない。内部電極は、介在する間隔が広く成りすぎる場合であっても、静電容量等の影響のないダミー電極を、連結する内部電極の間に形成・露出しておくことにより、無電解めっき法等で形成した端子電極及び連結導体によって容易に接続することができる。   Furthermore, in the embodiment described above, the internal electrodes are alternately arranged for each dielectric layer, but the present invention is not limited to such a form. Even when the intervening spacing is too wide, by forming and exposing a dummy electrode that is not affected by capacitance etc. between the connecting internal electrodes, an electroless plating method, etc. It can be easily connected by the terminal electrode and the connecting conductor formed in (1).

本発明の一実施形態に係る表面実装型多連コンデンサの外観斜視図である。1 is an external perspective view of a surface-mounted multiple capacitor according to an embodiment of the present invention. (a)は図1の表面実装型多連コンデンサのA−A線断面図、(b)は図1の表面実装型多連コンデンサのB−B線断面図である。(A) is the sectional view on the AA line of the surface mount-type multiple capacitor of FIG. 1, (b) is the BB sectional view of the surface-mount type multiple capacitor of FIG. 図1の表面実装型多連コンデンサの分解斜視図である。FIG. 2 is an exploded perspective view of the surface mount type multiple capacitor of FIG. 1. 本発明の他の実施形態に係る表面実装型多連コンデンサの外観斜視図である。It is an external appearance perspective view of the surface mount-type multiple capacitor | condenser which concerns on other embodiment of this invention. 従来の多連コンデンサの断面図である。It is sectional drawing of the conventional multiple capacitor | condenser.

符号の説明Explanation of symbols

1・・・積層体
2・・・誘電体層
3a・・・第1の内部電極(内部電極)
3b・・・第2の内部電極(内部電極)
4a,4b,4c・・・コンデンサ素子
5a,5b,5c・・・端子電極
DESCRIPTION OF SYMBOLS 1 ... Laminated body 2 ... Dielectric layer 3a ... 1st internal electrode (internal electrode)
3b ... second internal electrode (internal electrode)
4a, 4b, 4c: Capacitor elements 5a, 5b, 5c: Terminal electrodes

Claims (3)

多数の誘電体層を積層して直方体状の積層体を形成するとともに、該積層体の内部で、隣接する誘電体層間に複数個の内部電極を1個ずつ介在させてなるn個(nは2以上の自然数)のコンデンサ素子を誘電体層の積層方向に一列状に配設し、前記積層体の側面に各コンデンサ素子と対応して設けられる端子電極を被着させてなる表面実装型多連コンデンサにおいて、
前記端子電極は、前記コンデンサ素子の中央域に位置する内部電極の外周部に少なくとも前記積層体の実装面近傍で共通接続されているとともに、前記積層体側面のうち前記実装面より離間した部位でコンデンサ素子の中央域に位置する内部電極と両端域に位置する内部電極とが電気的に接続されていることを特徴とする表面実装型多連コンデンサ。
A large number of dielectric layers are laminated to form a rectangular parallelepiped laminate, and n pieces (n is a number) where a plurality of internal electrodes are interposed between adjacent dielectric layers inside the laminate. (2 or more natural number) capacitor elements are arranged in a line in the stacking direction of the dielectric layers, and a terminal electrode provided corresponding to each capacitor element is attached to the side surface of the stack. For ream capacitors,
The terminal electrode is commonly connected at least in the vicinity of the mounting surface of the multilayer body to the outer peripheral portion of the internal electrode located in the central region of the capacitor element, and at a portion of the side surface of the multilayer body that is separated from the mounting surface. A surface mount type multiple capacitor characterized in that an internal electrode located in a central area of a capacitor element and an internal electrode located in both end areas are electrically connected.
前記端子電極が、各内部電極の外周部を起点として前記積層体の表面に析出させた無電解めっき膜から成っていることを特徴とする請求項1に記載の表面実装型多連コンデンサ。 2. The surface mount type multiple capacitor according to claim 1, wherein the terminal electrode is made of an electroless plating film deposited on the surface of the multilayer body starting from the outer peripheral portion of each internal electrode. 前記コンデンサ素子の中央域に位置する内部電極と両端域に位置する内部電極とを電気的に接続する連結部が、隣接するもの同士、コンデンサ素子の配列方向と直交する方向にずらして配置されていることを特徴とする請求項1または請求項2に記載の表面実装型多連コンデンサ。 The connecting portions that electrically connect the internal electrodes located in the central area of the capacitor element and the internal electrodes located in both end areas are arranged so as to be shifted from each other in a direction perpendicular to the arrangement direction of the capacitor elements. The surface mount type multiple capacitor according to claim 1, wherein the surface mount type multiple capacitor is provided.
JP2004095957A 2004-03-29 2004-03-29 Surface-mounted multiple capacitor Pending JP2005285994A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101525672B1 (en) * 2013-07-15 2015-06-03 삼성전기주식회사 Array-type multi-layered ceramic electronic component and board for mounting the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101525672B1 (en) * 2013-07-15 2015-06-03 삼성전기주식회사 Array-type multi-layered ceramic electronic component and board for mounting the same

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