JP2005285866A - Multiple wiring board - Google Patents

Multiple wiring board Download PDF

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JP2005285866A
JP2005285866A JP2004093855A JP2004093855A JP2005285866A JP 2005285866 A JP2005285866 A JP 2005285866A JP 2004093855 A JP2004093855 A JP 2004093855A JP 2004093855 A JP2004093855 A JP 2004093855A JP 2005285866 A JP2005285866 A JP 2005285866A
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wiring board
wiring
region
outer peripheral
conductor
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Makoto Hashimoto
誠 橋元
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Kyocera Corp
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Kyocera Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiple wiring board capable of manufacturing a plurality of wiring boards arranged longitudinally and laterally excellent in electrical connection reliability without generating any crack etc. upon division capable of preventing inconvenience such as warping from happening in a thinned wide area ceramic master substrate. <P>SOLUTION: The multiple wiring board comprises a square-shaped master board 1 where a plurality of wiring board regions 2 are arranged longitudinally and laterally at the center of a principal surface into a square shape as a whole, and a frame-shaped margin region 4 is formed on an outer peripheral part; wiring conductors 3 formed on the respective wiring board regions 2; dividing grooves 5' formed at boundaries 5 of the wiring board regions 2; through conductors 11 formed on extension lines of the dividing grooves 5' of the margin region 4; and an outer peripheral metalized layer 6 formed over the entire periphery alternately on upper and lower surfaces of the margin region 4 for coupling the adjacent through conductors 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、広面積の母基板の中央部に各々が半導体素子や水晶振動子等の電子部品を搭載するための小型の配線基板となる多数の配線基板領域を縦横の並びに一体的に配列形成して成る多数個取り配線基板に関するものである。   In the present invention, a large number of wiring board regions, each of which is a small wiring board for mounting electronic components such as a semiconductor element and a crystal resonator, are arranged in a central portion of a large-area mother board in a vertical and horizontal arrangement. This relates to a multi-piece wiring board.

従来、例えば半導体素子や水晶振動子等の電子部品を収納するための電子部品収納用パッケージに用いられる小型の配線基板は、酸化アルミニウム質焼結体等のセラミック材料から成り、表面に配線導体が形成された四角平板状のセラミック絶縁層を複数層、上下に積層した構造である。この配線基板に電子部品を収納し、電子部品の電極を配線導体の露出部分に半田やボンディングワイヤ等を介して電気的に接続することにより電子装置が形成される。   Conventionally, for example, a small wiring board used for an electronic component storage package for storing an electronic component such as a semiconductor element or a crystal resonator is made of a ceramic material such as an aluminum oxide sintered body, and has a wiring conductor on the surface. In this structure, a plurality of formed rectangular flat ceramic insulating layers are stacked one above the other. An electronic device is formed by housing an electronic component on the wiring board and electrically connecting the electrode of the electronic component to an exposed portion of the wiring conductor via solder, a bonding wire, or the like.

ところで、このような配線基板は近時の電子装置の小型化の要求に伴い、その大きさが数mm角程度の極めて小さなものとなってきており、多数個の配線基板の取り扱いを容易とするために、また配線基板および電子装置の製作を効率よくするために1枚の広面積の母基板中から多数個の配線基板を同時集約的に得るようになした、いわゆる多数個取り配線基板の形態で製作されている。   By the way, with the recent demand for miniaturization of electronic devices, the size of such wiring boards has become extremely small, about several mm square, and it is easy to handle a large number of wiring boards. Therefore, in order to efficiently manufacture a wiring board and an electronic device, a so-called multi-cavity wiring board is obtained which simultaneously obtains a large number of wiring boards from one large-area mother board. It is manufactured in the form.

このような多数個取り配線基板の一例を図2(a),(b)に示す。ここで、図2(a)は多数個取り配線基板の平面図であり、図2(b)はそのB−B’における断面図である。   An example of such a multi-piece wiring board is shown in FIGS. Here, FIG. 2A is a plan view of a multi-piece wiring substrate, and FIG. 2B is a cross-sectional view taken along B-B ′.

同図において、多数個取り配線基板は、四角形状の配線基板領域32が縦横に複数配列形成されるとともに外周部に枠状の捨て代領域34が形成された四角形状の母基板31と、各配線基板領域32に形成された配線導体33と、配線基板領域32の境界35に形成された分割溝35’とを具備した構造である。   In the figure, a multi-piece wiring board includes a rectangular mother board 31 in which a plurality of rectangular wiring board regions 32 are arranged in rows and columns and a frame-shaped discard margin region 34 is formed on the outer periphery, and In this structure, a wiring conductor 33 formed in the wiring board region 32 and a dividing groove 35 ′ formed in a boundary 35 of the wiring board region 32 are provided.

各配線基板領域32の上面には、電子部品を搭載し収容するための凹部から成る搭載部42が形成されており、配線導体33は、一部が配線基板領域32の上面の搭載部42、またはその周辺に露出するとともに、他の一部が配線基板領域32の下面や側面等に露出するようにして形成されている。   On the upper surface of each wiring board region 32, a mounting portion 42 is formed which is a recess for mounting and housing electronic components. The wiring conductor 33 is partially mounted on the upper surface of the wiring board region 32. Alternatively, it is formed so that it is exposed to the periphery and the other part is exposed to the lower surface and side surfaces of the wiring board region 32.

そして、配線基板領域32の搭載部42に電子部品(図示せず)を搭載固定するとともに電子部品の電極をボンディングワイヤや半田等の電気的接続手段を介して搭載部42またはその周辺に露出している配線導体33に電気的に接続し、配線基板領域32の上面に搭載部42を塞ぐようにして金属やガラス等から成る蓋体を接合したり、搭載部42内にエポキシ樹脂等から成る樹脂製充填材を充填することにより、搭載部42の内部に電子部品を気密に収納することによって、多数の電子装置が縦横の並びに配列形成された多数個取りの状態で形成される。しかる後、この多数個取りの状態の電子装置を個々の配線基板領域32に分割することにより多数個の製品としての電子装置が形成される。なお、配線基板領域32への電子部品の搭載は、多数個取り配線基板を個々の配線基板領域32に分割した後に行われる場合もある。   Then, an electronic component (not shown) is mounted and fixed on the mounting portion 42 of the wiring board region 32, and the electrodes of the electronic component are exposed to the mounting portion 42 or its periphery through an electrical connection means such as a bonding wire or solder. It is electrically connected to the wiring conductor 33, and a lid made of metal, glass or the like is joined to the upper surface of the wiring board region 32 so as to close the mounting portion 42, or the mounting portion 42 is made of epoxy resin or the like. By filling the resin filler, the electronic parts are housed in the mounting portion 42 in an airtight manner, so that a large number of electronic devices are formed in a multi-piece state in which the horizontal and vertical arrangements are formed. Thereafter, the electronic device in the multi-cavity state is divided into individual wiring board regions 32 to form an electronic device as a large number of products. The electronic component may be mounted on the wiring board region 32 after the multi-piece wiring board is divided into the individual wiring board regions 32.

この場合、配線導体33は、その露出する表面に、あらかじめニッケルや金等のめっき層(図示せず)が被着されている。配線導体33にめっき層を被着させておくと、配線導体33の酸化を効果的に防止することができるとともに、配線導体33に対するボンディングワイヤのボンディング性や、半田の濡れ性等の特性を向上させることができる。   In this case, the wiring conductor 33 has a plating layer (not shown) made of nickel, gold or the like applied in advance to the exposed surface. If the plating layer is applied to the wiring conductor 33, the wiring conductor 33 can be effectively prevented from being oxidized, and the bonding wire bonding property to the wiring conductor 33 and the characteristics such as solder wettability are improved. Can be made.

配線導体33にめっきを施すには、多数個取り配線基板をニッケル,金等のめっき液中に浸漬し、配線導体33に所定のめっき用の電流を供給する。母基板31の一対の辺部等にはめっき導通用パターン38が、配線導体33と電気的に接続するようにして形成されており、めっき用治具(ラック)に設けられた導通用端子(図示せず)をめっき導通用パターン38に接触させるとともに、導通用端子の一対の端部でめっき導通用パターン38を上下から挟み込むことにより、電源から導通用端子とめっき導通用パターン38とを介して配線導体33にめっき用の電流が供給される。   In order to plate the wiring conductor 33, a multi-piece wiring board is immersed in a plating solution such as nickel or gold, and a predetermined plating current is supplied to the wiring conductor 33. A plating conduction pattern 38 is formed on a pair of sides of the mother board 31 so as to be electrically connected to the wiring conductor 33, and a conduction terminal (on a plating jig (rack)) is provided. (Not shown) is brought into contact with the plating conduction pattern 38, and the plating conduction pattern 38 is sandwiched from above and below by a pair of ends of the conduction terminal, whereby the conduction terminal and the plating conduction pattern 38 are connected from the power source. Thus, a current for plating is supplied to the wiring conductor 33.

なお、めっき導通用パターン38は図2に示すように、母基板31の一対の端面に形成された楕円弧状、または円弧状の切り欠き部39の内面にメタライズ層等の導体層を被着形成することにより形成されている。   As shown in FIG. 2, the plating conduction pattern 38 is formed by depositing a conductor layer such as a metallized layer on the inner surface of the elliptical arc-shaped or arc-shaped cutout 39 formed on the pair of end surfaces of the mother substrate 31. It is formed by doing.

この場合、一般に、電解めっき法においては、被めっき部位の外周部に近いほど電流が流れ易く電流密度が高くなること、また、めっき液の循環供給がされやすいこと等から、めっき速度が速く、めっき厚みが厚くなることが知られている。   In this case, in general, in the electroplating method, the closer to the outer peripheral portion of the portion to be plated, the easier the current flows, the higher the current density, and the easier the circulating supply of the plating solution. It is known that the plating thickness increases.

そのため、配線基板領域32の配線導体33に被着形成されるニッケルや金等のめっきの厚みを均一なものとするために、母基板31の捨て代領域34の主面(通常は、電子部品が搭載される上側の主面)には枠状の外周メタライズ層36が、めっき導通用パターン38および配線導体33と電気的に接続して形成されている。   Therefore, in order to make the thickness of the plating such as nickel or gold deposited on the wiring conductor 33 in the wiring board region 32 uniform, the main surface (usually an electronic component) A frame-like outer peripheral metallized layer 36 is formed on the plating main conduction pattern 38 and the wiring conductor 33 on the upper main surface).

外周メタライズ層36は、その内側の被めっき部位に被着しようとするニッケル,金等のめっき金属を、自身のほうに被着させて、被めっき部位のめっき厚みのばらつきを抑える、いわゆる補助陰極として機能し、内側の配線基板領域32の配線導体33に被着されるめっきの厚みばらつきが生じることを防止している。   The outer peripheral metallized layer 36 is a so-called auxiliary cathode in which a plating metal such as nickel or gold to be deposited on the inner portion to be plated is deposited on itself to suppress variation in the plating thickness of the portion to be plated. And prevents variations in the thickness of the plating applied to the wiring conductor 33 in the inner wiring board region 32.

なお、隣接する配線基板領域32の境界35上には、ビア導体40が形成されており、このビア導体40は、隣接する配線基板領域32の配線層間や上下の配線層間を電気的に接続するように形成されており、個々の配線基板領域32に分割する際に縦に分割されることにより、配線基板の側面に位置する側面導体(キャスタレーション導体)となる。
特開2000−340898号公報
A via conductor 40 is formed on the boundary 35 of the adjacent wiring board region 32, and the via conductor 40 electrically connects the wiring layers of the adjacent wiring board region 32 and the upper and lower wiring layers. Thus, when divided into individual wiring board regions 32, they are divided vertically so that side conductors (castellation conductors) located on the side faces of the wiring board are obtained.
JP 2000-340898 A

しかしながら、近年、電子部品収納用パッケージ等に用いられる小型の配線基板は、電子装置に対する小型化,低背化の要求のため、より一層の小型化、特に薄型化が必要となってきており、これに応じて母基板31は、例えば厚みが0.5mm以下と非常に薄型化されるようになってきている。   However, in recent years, small wiring boards used for electronic component storage packages and the like have been required to be further reduced in size, particularly reduced in thickness due to demands for downsizing and low profile of electronic devices. In response to this, the mother board 31 has become very thin, for example, with a thickness of 0.5 mm or less.

このように母基板31が薄型化されると、外周メタライズ層36と成る金属ペーストと母基板31と成るセラミックグリーンシートとの焼成時の収縮率の違いにより、母基板31の上面等の一つの主面の外周部分の各辺において、各辺の全長にわたる大きな応力が一方向に作用し、この応力により母基板31が凹状、または凸状に反ってしまい、各配線基板領域32を個片状に分割する際に、各配線基板領域32の間や、配線基板領域32と捨て代領域34との間の境界線が歪むため個々の配線基板においてクラックやバリが発生するという問題点を有していた。   When the mother substrate 31 is thinned in this way, one of the upper surface of the mother substrate 31 and the like is caused by the difference in shrinkage rate during firing between the metal paste that becomes the outer metallized layer 36 and the ceramic green sheet that becomes the mother substrate 31. A large stress over the entire length of each side acts in one direction on each side of the outer peripheral portion of the main surface, and the mother substrate 31 is warped in a concave or convex shape due to this stress, and each wiring board region 32 is separated into individual pieces. When dividing into two, the boundary lines between the respective wiring board regions 32 and between the wiring board region 32 and the disposal margin region 34 are distorted, so that cracks and burrs are generated in the individual wiring boards. It was.

本発明はかかる問題点に鑑み案出されたものであり、その目的は、より一層の小型化、特に薄型化が進んだ配線基板32において、母基板31の外周の捨て代領域34の主面にめっき厚みのばらつきを防止するための外周メタライズ層36を設けたとしても、母基板31において反り等の不具合が生じることを防止できるとともに、各配線基板領域32を分割する際にクラックや欠けが発生することを防止することが可能であり、かつ配線導体33の表面に良好なめっき層を被着させることが可能な多数個取り配線基板を提供することにある。   The present invention has been devised in view of such a problem, and the object thereof is the main surface of the disposal margin region 34 on the outer periphery of the mother board 31 in the wiring board 32 which has been further miniaturized, particularly thinned. Even if the outer peripheral metallized layer 36 for preventing the variation in the plating thickness is provided, it is possible to prevent problems such as warping in the mother board 31 and to generate cracks and chips when the wiring board regions 32 are divided. An object of the present invention is to provide a multi-piece wiring board that can prevent the occurrence and can adhere a good plating layer to the surface of the wiring conductor 33.

本発明の多数個取り配線基板は、主面の中央部に複数の配線基板領域が縦横に全体として四角形状に配列形成されるとともに、外周部に枠状の捨て代領域が形成された四角枠状の母基板と、前記各配線基板領域に形成された配線導体と、前記配線基板領域の境界に形成された分割溝と、前記捨て代領域の前記分割溝の延長線上に形成された貫通導体と、隣接する該貫通導体間を連結するとともに前記捨て代領域の上下主面に交互に全周にわたって形成された外周メタライズ層とを具備していることを特徴とするものである。   The multi-cavity wiring board according to the present invention is a square frame in which a plurality of wiring board regions are arranged in a square shape as a whole in the center portion of the main surface, and a frame-shaped discard margin region is formed in the outer peripheral portion. -Shaped mother board, wiring conductors formed in each of the wiring board regions, split grooves formed at the boundaries of the wiring board regions, and through conductors formed on the extension lines of the split grooves in the discard margin region And an outer peripheral metallization layer that connects the adjacent through conductors and is alternately formed on the upper and lower main surfaces of the discard margin region over the entire circumference.

また、本発明の多数個取り配線基板は、好ましくは、前記外周メタライズ層は、前記配線基板領域全体の一つの辺部において、その辺部に沿っているものの形状が全て同じであるとともに、平面視で全体として直線状に形成されていることを特徴とするものである。   Further, in the multi-cavity wiring board of the present invention, it is preferable that the outer peripheral metallization layer has the same shape along the side in one side of the entire wiring board region, and is planar. It is characterized by being formed linearly as a whole.

本発明の多数個取り配線基板によれば、外周部に枠状の捨て代領域が形成された四角形状の母基板と、各配線基板領域に形成された配線導体と、配線基板領域の境界に形成された分割溝と、捨て代領域の分割溝の延長線上に形成された貫通導体と、隣接する該貫通導体間を連結するとともに捨て代領域の上下主面に交互に全周にわたって形成された外周メタライズ層とを具備していることから、外周メタライズ層と母基板との間で焼成時の収縮率の違いに起因して応力が生じたとしても、その応力は捨て代領域の上下主面に交互に全周にわたって形成された外周メタライズ層の各部位ごとに断続して生じるとともに、上側の主面と下側の主面との間で応力が相殺することになるので、母基板の一つの主面の各辺の全長にわたって一方向に大きな応力が作用することはなく、母基板の反りを防止することが可能となる。これにより、各配線基板領域を個片状に分割する際にクラックやバリが発生することを防止できる。また、母基板を分割しない状態で半導体素子等の電子部品を実装する際に、搭載精度の悪化を防止して実装不良を防止することができる。   According to the multi-cavity wiring board of the present invention, a rectangular mother board having a frame-shaped discard margin area formed on the outer periphery, wiring conductors formed in each wiring board area, and the boundary of the wiring board area The formed dividing grooves, the through conductors formed on the extension lines of the dividing grooves in the disposal margin area, and the adjacent through conductors are connected, and the upper and lower main surfaces of the disposal margin area are alternately formed over the entire circumference. Since the outer peripheral metallized layer is provided, even if stress is generated due to the difference in shrinkage rate during firing between the outer peripheral metallized layer and the mother substrate, the stress is disposed on the upper and lower main surfaces of the disposal margin region. Are alternately generated at each part of the outer peripheral metallization layer formed over the entire circumference, and stress cancels out between the upper main surface and the lower main surface. Large in one direction over the entire length of each side of one main surface Never stress acts, it is possible to prevent warping of the mother board. Thereby, cracks and burrs can be prevented from occurring when each wiring board region is divided into individual pieces. In addition, when mounting electronic components such as semiconductor elements without dividing the mother board, mounting accuracy can be prevented from being deteriorated and mounting defects can be prevented.

また、形成された外周メタライズ層がいわゆる補助陰極として作用することから、各配線導体に流れる電流が均一になり、広面積の母基板の縦横に複数配列形成した配線基板領域の主面の配線導体に被着されるめっき層の厚みを均一で安定したものとすることができる。   Further, since the formed outer peripheral metallization layer acts as a so-called auxiliary cathode, the current flowing through each wiring conductor becomes uniform, and the wiring conductor on the main surface of the wiring board region formed in a plurality of rows and columns on a large area mother board. The thickness of the plating layer deposited on the substrate can be made uniform and stable.

また、捨て代領域の分割溝の延長線上に貫通導体が形成されていることから、母基板の捨て代領域の外周メタライズ層を越えて分割溝を形成したとしても、上下主面の外周メタライズ層が分割溝で分断されて電気的導通が阻害されることがなく、母基板の上下主面の外周メタライズ層の全周にわたって確実に通電させて配線導体に被着させるめっき層の厚さのバラつきを確実に抑えることができるとともに母基板の各配線基板領域を効率良く個片状に分割することができる。   In addition, since the through conductor is formed on the extension line of the dividing groove in the discard margin region, even if the dividing groove is formed beyond the outer peripheral metallization layer in the discard margin region of the mother board, the outer peripheral metallization layer on the upper and lower main surfaces The thickness of the plating layer that adheres to the wiring conductor by energizing the entire circumference of the outer metallization layer on the upper and lower main surfaces of the mother board without causing any electrical continuity is divided. Can be reliably suppressed, and each wiring board region of the mother board can be efficiently divided into individual pieces.

さらに、例えば、捨て代領域に形成された貫通導体を、貫通孔内に導体が完全に充填されたものとせず、貫通孔の内壁にのみ導体が被着されたものとすることにより、母基板が大きくなったとしても、貫通導体の内側の空洞を介して母基板の表裏面間のめっき液の循環をスムーズに行わせることができることから、広面積の母基板の縦横に複数配列形成した配線基板領域の主面の配線導体に被着されるめっき層の厚みを均一で安定したものとすることができる。   Further, for example, the through-conductor formed in the abandon margin region is not the one in which the conductor is completely filled in the through-hole, and the conductor is attached only to the inner wall of the through-hole. Since the plating solution can be smoothly circulated between the front and back surfaces of the mother board through the cavity inside the through conductor even when the size of the wiring becomes larger, the wiring formed in a plurality of rows and columns on a large area of the mother board The thickness of the plating layer deposited on the wiring conductor on the main surface of the substrate region can be made uniform and stable.

また、本発明の多数個取り配線基板によれば、好ましくは、外周メタライズ層は、配線基板領域全体の一つの辺部において、その辺部に沿っているものの形状が全て同じであるとともに、平面視で全体として直線状に形成されていることから、母基板の上下各主面のそれぞれの全周にわたって外周メタライズ層と母基板との間で焼成時の収縮率の違いに起因して発生する応力がほぼ等しくなり、より一層確実に母基板の反りを防止することが可能となる。その結果、電気的な接続信頼性に優れた配線基板を作製可能な多数個取り配線基板を提供することができる。   Further, according to the multi-cavity wiring board of the present invention, preferably, the outer peripheral metallized layer has the same shape along the side in one side of the entire wiring board region and is flat. Since it is formed linearly as a whole, it occurs due to the difference in shrinkage rate during firing between the outer peripheral metallized layer and the mother substrate over the entire circumference of each of the upper and lower main surfaces of the mother substrate. Since the stresses are almost equal, it is possible to prevent warping of the mother substrate even more reliably. As a result, it is possible to provide a multi-piece wiring board capable of producing a wiring board having excellent electrical connection reliability.

次に、本発明の多数個取り配線基板を添付の図面を基に説明する。図1(a)は本発明の多数個取り配線基板の実施の形態の一例を示す平面図であり、図1(b)は図1(a)の多数個取り配線基板のA−A’線における断面図ある。同図において1は母基板、2は配線基板領域、3は配線導体、4は捨て代領域、6は外周メタライズ層、8はめっき導通用パターン、11は貫通導体である。なお、各配線基板領域2の配線導体3は、実際には複雑なパターンであるが、図面を見易くするために、四角形状のパターンに略して示している。   Next, a multi-piece wiring board according to the present invention will be described with reference to the accompanying drawings. FIG. 1A is a plan view showing an example of an embodiment of a multi-cavity wiring board according to the present invention, and FIG. 1B is an AA ′ line of the multi-cavity wiring board of FIG. FIG. In the figure, 1 is a mother board, 2 is a wiring board area, 3 is a wiring conductor, 4 is a margin area, 6 is an outer metallization layer, 8 is a pattern for plating conduction, and 11 is a through conductor. Note that the wiring conductors 3 in each wiring board region 2 are actually complicated patterns, but in order to make the drawing easier to see, they are abbreviated as rectangular patterns.

そして、主として母基板1、配線基板領域2、配線導体3、外周メタライズ層6、貫通導体11で本発明の多数個取り配線基板が構成されている。   The mother board 1, the wiring board region 2, the wiring conductor 3, the outer peripheral metallized layer 6, and the through conductor 11 constitute the multi-cavity wiring board of the present invention.

母基板1は、酸化アルミニウム質焼結体や窒化アルミニウム質焼結体,ムライト質焼結体,ガラスセラミックス等のセラミック材料から成るセラミック層を積層して成り、主面の中央部に複数の配線基板領域2が縦横に全体として四角形状に配列形成されている。   The mother board 1 is formed by laminating ceramic layers made of a ceramic material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, or a glass ceramic, and a plurality of wirings are provided at the center of the main surface. The substrate region 2 is arranged in a square shape as a whole in the vertical and horizontal directions.

また、各配線基板領域2は、例えば一辺の長さが2〜20mm程度で厚みが0.4〜2mm程度の四角形状である。そして、各配線基板領域2の上面中央部に電子部品を収納し搭載するための凹部から成る搭載部12が設けられている。   Moreover, each wiring board area | region 2 is the square shape whose length of one side is about 2-20 mm and thickness is about 0.4-2 mm, for example. A mounting portion 12 including a recess for storing and mounting an electronic component is provided at the center of the upper surface of each wiring board region 2.

また、母基板1の外周部には、枠状の捨て代領域4が形成されている。捨て代領域4は、多数個取り配線基板の取り扱いを容易とすることや、後述するように、配線導体3にめっき層を被着させる際のめっき層の形成を容易、かつ均一で安定したものとすること等のために形成されている。   In addition, a frame-shaped discard margin region 4 is formed on the outer peripheral portion of the mother board 1. The disposal allowance region 4 is one that facilitates handling of a multi-piece wiring board, and facilitates uniform, stable formation of a plating layer when a plating layer is deposited on the wiring conductor 3 as will be described later. And so on.

このような母基板1は、例えば酸化アルミニウム質焼結体から成る場合であれば、酸化アルミニウム等の原料粉末をシート状に成形したセラミックグリーンシートを複数枚準備するとともに縦横に区画して配線基板領域2および捨て代領域4を設け、次に、このセラミックグリーンシートの一部のものについて適当な打ち抜き加工を施した後、積層、焼成することによって作製される。   If such a mother substrate 1 is made of, for example, an aluminum oxide sintered body, a plurality of ceramic green sheets prepared by forming a raw material powder such as aluminum oxide into a sheet shape are prepared, and the wiring substrate is partitioned vertically and horizontally. The region 2 and the disposal margin region 4 are provided, and then a part of this ceramic green sheet is subjected to an appropriate punching process, and then laminated and fired.

各配線基板領域2には、配線導体3が形成されている。配線導体3は、搭載部に搭載される電子部品の電極とボンディングワイヤや半田等を介して電気的に接続され、これを配線基板領域2の下面や側面に導出する導電路として機能する。   A wiring conductor 3 is formed in each wiring board region 2. The wiring conductor 3 is electrically connected to an electrode of an electronic component mounted on the mounting portion via a bonding wire, solder, or the like, and functions as a conductive path that leads to the lower surface or side surface of the wiring board region 2.

配線導体3は、タングステンやモリブデン,銅,銀等の金属材料から成り、例えば、タングステンから成る場合であれば、タングステンの金属ペーストを母基板1となるセラミックグリーンシートに所定の配線導体3のパターンで印刷しておき、セラミックグリーンシートと同時焼成することにより形成される。   The wiring conductor 3 is made of a metal material such as tungsten, molybdenum, copper, or silver. For example, if the wiring conductor 3 is made of tungsten, a pattern of a predetermined wiring conductor 3 is formed on a ceramic green sheet that becomes the base substrate 1 using a tungsten metal paste. It is formed by printing and printing together with a ceramic green sheet.

また、母基板1は、配線基板領域2の境界5に沿って、主面(図1の例では上面)に分割溝5’が形成されている。   Further, the mother substrate 1 has a dividing groove 5 ′ formed on the main surface (upper surface in the example of FIG. 1) along the boundary 5 of the wiring substrate region 2.

分割溝5’は、母基板1を各配線基板領域2に分割する際の分割の作業を容易とするためのものである。分割溝5’を中心として母基板1をたわませることにより、分割溝5’の底面から対向する母基板1の主面(図1の例では下面)にかけて母基板1が破断し、分割が行われる。なお、分割溝5’は母基板1の上下両主面に形成してもよい。また、配線基板領域2と捨て代領域4との境界5に沿った部分にも形成することが望ましい。   The division grooves 5 ′ are for facilitating the division work when dividing the mother board 1 into the respective wiring board regions 2. By bending the mother substrate 1 around the dividing groove 5 ′, the mother substrate 1 is broken from the bottom surface of the dividing groove 5 ′ to the main surface of the opposing mother substrate 1 (the lower surface in the example of FIG. 1). Done. The dividing grooves 5 ′ may be formed on the upper and lower main surfaces of the mother substrate 1. Moreover, it is desirable to form also in the part along the boundary 5 of the wiring board area | region 2 and the discard margin area | region 4. FIG.

このような分割溝5’は、例えば、母基板1となるセラミックグリーンシートの積層体の主面に、配線基板領域2の境界5に沿って金属刃を押圧して所定の深さで切り込みを入れること等により形成される。   Such a dividing groove 5 ′ is cut at a predetermined depth by pressing a metal blade along the boundary 5 of the wiring board region 2, for example, on the main surface of the laminate of ceramic green sheets to be the mother board 1. It is formed by inserting.

そして、配線基板領域2の搭載部に電子部品(図示せず)を搭載固定するとともに電子部品の電極をボンディングワイヤや半田等の電気的接続手段を介して搭載部またはその周辺に露出している配線導体3に電気的に接続し、配線基板領域2の上面に搭載部を塞ぐようにして金属やガラス等から成る蓋体を接合したり、搭載部内にエポキシ樹脂等から成る樹脂製充填材を充填することにより、搭載部の内部に電子部品を気密に収納することによって、多数の電子装置が縦横の並びに配列形成された多数個取りの状態で形成される。しかる後、この多数個取りの状態の電子装置を個々の配線基板領域2に分割することにより多数個の製品としての電子装置が形成される。なお、配線基板領域2への電子部品の搭載は、多数個取り配線基板を個々の配線基板領域2に分割した後に行うようにしてもよい。   Then, an electronic component (not shown) is mounted and fixed on the mounting portion of the wiring board region 2 and the electrodes of the electronic component are exposed to the mounting portion or its periphery via an electrical connection means such as a bonding wire or solder. Electrically connected to the wiring conductor 3, a lid made of metal, glass or the like is bonded to the upper surface of the wiring board region 2 so as to close the mounting portion, or a resin filler made of epoxy resin or the like is placed in the mounting portion. By filling, the electronic components are housed in the mounting portion in an airtight manner, so that a large number of electronic devices are formed in a multi-piece state in which the electronic devices are arranged vertically and horizontally. Thereafter, the electronic device in the multi-cavity state is divided into individual wiring board regions 2 to form an electronic device as a large number of products. The mounting of electronic components on the wiring board region 2 may be performed after the multi-piece wiring board is divided into individual wiring board regions 2.

この場合、配線導体3の露出した表面には、酸化腐食を防止するとともに、半田やボンディングワイヤを接続する際の半田の濡れ性、ボンディングワイヤのボンディング性等の特性を向上させるために、ニッケルや金等のめっき層(図示せず)があらかじめ被着されている。   In this case, in order to prevent oxidation corrosion on the exposed surface of the wiring conductor 3 and improve characteristics such as solder wettability and bonding wire bonding property when connecting the solder or bonding wire, A plating layer (not shown) such as gold is previously applied.

なお、配線導体3にめっきを施すには、多数個取り配線基板をニッケル,金等のめっき液中に浸漬し、配線導体3に所定のめっき用の電流を供給する。母基板1の一対の辺部等にはめっき導通用パターン8が、配線導体3と電気的に接続するようにして形成されており、めっき用治具(ラック)に設けられた導通用端子(図示せず)をめっき導通用パターン8に接触させるとともに、導通用端子の一対の端部でめっき導通用パターン8を上下から挟み込むことにより、電源から導通用端子とめっき導通用パターン8とを介して配線導体3にめっき用の電流が供給されることとなる。   In order to plate the wiring conductor 3, a multi-piece wiring board is immersed in a plating solution such as nickel or gold, and a predetermined plating current is supplied to the wiring conductor 3. A plating conduction pattern 8 is formed on a pair of sides of the mother board 1 so as to be electrically connected to the wiring conductor 3, and a conduction terminal (rack) provided on a plating jig (rack). (Not shown) is brought into contact with the plating conduction pattern 8, and the plating conduction pattern 8 is sandwiched from above and below by a pair of ends of the conduction terminal, whereby the conduction terminal and the plating conduction pattern 8 are connected from the power source. Thus, a current for plating is supplied to the wiring conductor 3.

この場合、配線基板領域2同士の間や、配線基板領域2と外周メタライズ層6との間にビア導体10を形成し、これらの間の電気的な接続を容易とするようにしてもよい。   In this case, via conductors 10 may be formed between the wiring board regions 2 or between the wiring board region 2 and the outer peripheral metallized layer 6 to facilitate electrical connection therebetween.

ビア導体10は、母基板1となるセラミックグリーンシートに貫通孔を形成し、この貫通孔の内部や内側面に、配線導体3を形成するのと同様の金属ペーストを印刷塗布または充填することにより形成される。   The via conductor 10 is formed by forming a through hole in the ceramic green sheet to be the mother substrate 1 and printing or filling or filling a metal paste similar to that for forming the wiring conductor 3 inside or inside the through hole. It is formed.

外周メタライズ層6は、配線導体3に被着されるめっき層のばらつきを低減し、均一にするためのものである。すなわち、外周メタライズ層6は、いわゆる補助陰極として機能し、これにより、内側の配線基板領域2の配線導体3に被着されるめっき厚みが外周部で厚くなってめっき層の厚さにばらつきが生じることを防止している。   The outer peripheral metallized layer 6 is for reducing and uniforming the plating layer deposited on the wiring conductor 3. In other words, the outer peripheral metallized layer 6 functions as a so-called auxiliary cathode, whereby the plating thickness deposited on the wiring conductor 3 in the inner wiring board region 2 is increased at the outer peripheral portion, and the thickness of the plating layer varies. It is prevented from occurring.

外周メタライズ層6は、配線導体3のめっき厚みのばらつきを防止するためには、2mm以上の幅で形成することが好ましい。   The outer peripheral metallized layer 6 is preferably formed with a width of 2 mm or more in order to prevent variations in the plating thickness of the wiring conductor 3.

なお、外周メタライズ層6は、配線導体3を形成するのと同様の金属ペーストを、セラミックグリーンシートの外周の捨て代領域4の主面に所望の形状に印刷塗布しておき、セラミックグリーンシートと同時焼成することにより形成される。外周メタライズ層6は、生産性等を考慮すると、配線導体3と同じ材料で形成することが好ましい。   The outer peripheral metallization layer 6 is formed by applying a metal paste similar to that for forming the wiring conductor 3 in a desired shape on the main surface of the disposal margin region 4 on the outer periphery of the ceramic green sheet. It is formed by simultaneous firing. The outer peripheral metallized layer 6 is preferably formed of the same material as the wiring conductor 3 in consideration of productivity and the like.

本発明の多数個取り配線基板において、外周メタライズ層6は、捨て代領域4の分割溝5’の延長線上に形成された貫通導体11の隣接するもの同士の間を連結するとともに、捨て代領域4の上下主面に交互に全周にわたるようにして形成されている。   In the multi-cavity wiring board of the present invention, the outer peripheral metallized layer 6 connects adjacent ones of the through conductors 11 formed on the extension line of the dividing groove 5 ′ of the discard margin region 4 and also discards margin region. The four upper and lower main surfaces are alternately formed over the entire circumference.

この構成により、外周メタライズ層6と母基板1との間で焼成時の収縮率の違いに起因して応力が生じたとしても、その応力は捨て代領域4の上下主面に交互に全周にわたって形成された外周メタライズ層6の各部位ごとに断続して生じるとともに、上側の主面と下側の主面との間で応力が相殺することになるので、母基板1の一つの主面の各辺の全長にわたって一方向に大きな応力が作用することはなく、母基板1の反りを防止することが可能となる。これにより、各配線基板領域2を個片状に分割する際にクラックやバリが発生することを防止できる。   With this configuration, even if stress is generated between the outer peripheral metallized layer 6 and the mother substrate 1 due to the difference in shrinkage rate during firing, the stress is alternately alternately applied to the upper and lower main surfaces of the disposal margin region 4 over the entire periphery. One of the main surfaces of the mother substrate 1 is generated intermittently for each part of the outer peripheral metallized layer 6 formed over the entire surface and the stress cancels out between the upper main surface and the lower main surface. A large stress does not act in one direction over the entire length of each side of the substrate, and the warp of the mother substrate 1 can be prevented. As a result, it is possible to prevent cracks and burrs from occurring when each wiring board region 2 is divided into individual pieces.

また、母基板1を分割しない状態で半導体素子等の電子部品を実装する際に、搭載精度の悪化を防止して実装不良を防止することができる。   In addition, when mounting electronic components such as semiconductor elements without dividing the mother board 1, mounting accuracy can be prevented from being deteriorated and mounting defects can be prevented.

また、形成された外周メタライズ層6がいわゆる補助陰極として作用することから、各配線導体3に流れる電流が均一になり、広面積の母基板1の縦横に複数配列形成した配線基板領域2の主面の配線導体3に被着されるめっき層の厚みを均一で安定したものとすることができる。   Further, since the formed outer peripheral metallization layer 6 functions as a so-called auxiliary cathode, the current flowing through each wiring conductor 3 becomes uniform, and the main part of the wiring board region 2 formed in a plurality of rows and columns on the mother board 1 having a large area. The thickness of the plating layer applied to the wiring conductor 3 on the surface can be made uniform and stable.

なお、貫通導体11は、母基板1の上下主面の外周メタライズ層6同士を電気的に接続し、全体として一つの枠状の導体とするためのものである。外周メタライズ層6を母基板1の上下主面間で一つの枠状の導体とすることにより、配線基板領域2の全体を取り囲む枠状の補助陰極として確実に機能させることができ、配線導体3に被着されるめっき層の厚みを均一で安定したものとすることができる。   The through conductors 11 are for electrically connecting the outer peripheral metallized layers 6 on the upper and lower main surfaces of the mother board 1 to form one frame-like conductor as a whole. By forming the outer peripheral metallized layer 6 as a single frame-shaped conductor between the upper and lower main surfaces of the mother substrate 1, it is possible to reliably function as a frame-shaped auxiliary cathode that surrounds the entire wiring substrate region 2. The thickness of the plating layer deposited on the substrate can be made uniform and stable.

この場合、貫通導体11を形成する方法としては、例えばセラミックグリーンシートを複数枚準備するとともに搭載部、および捨て代領域4に形成する貫通導体11を形成するために所定の位置を金型等により打ち抜き加工を施した後、この打ち抜かれたセラミックグリーンシートの貫通孔の内壁に導電性ペーストをスクリーン印刷法等により塗布するとともに、このメタライズ層が貫通孔の内壁に塗布されたセラミックグリーンシートと、導電性ペーストが所定の位置に印刷されたセラミックグリーンシートとを積層,密着して焼成すること等により作製することができる。   In this case, as a method of forming the through conductor 11, for example, a plurality of ceramic green sheets are prepared, and a predetermined position is formed by a mold or the like in order to form the through conductor 11 formed in the mounting portion and the disposal margin region 4. After performing the punching process, the conductive paste is applied to the inner wall of the through hole of the punched ceramic green sheet by a screen printing method or the like, and the ceramic green sheet in which the metallized layer is applied to the inner wall of the through hole; It can be produced by laminating a ceramic green sheet on which a conductive paste is printed at a predetermined position, and firing it by closely contacting it.

このように、貫通導体11を、貫通孔内に導体が完全に充填されたものとせず、貫通孔の内壁にのみ導体が被着されたものとすることにより、母基板1が大きくなったとしても、貫通導体11の内側の空洞を介して母基板1の表裏面間のめっき液の循環をスムーズに行わせることができることから、広面積の母基板1の縦横に複数配列形成した配線基板領域2の主面の配線導体3に被着されるめっき層の厚みを均一で安定したものとすることができる。   As described above, the through-conductor 11 does not have the conductor completely filled in the through-hole, and the conductor is attached only to the inner wall of the through-hole. In addition, since it is possible to smoothly circulate the plating solution between the front and back surfaces of the mother board 1 through the cavity inside the through conductor 11, a plurality of wiring board regions arranged vertically and horizontally on the large area mother board 1 are provided. The thickness of the plating layer deposited on the wiring conductor 3 on the main surface 2 can be made uniform and stable.

ここで、捨て代領域4の上下主面に交互に全周にわたって形成する外周メタライズ層6は、その幅が2〜5mm程度に形成することが望ましい。外周メタライズ層6の幅が2mm未満となると、補助電極としての機能が低下しやすくなり、配線基板領域2の配線導体3に厚みばらつきが生じやすくなる。また、捨て代領域4の上下主面に交互に全周にわたって外周メタライズ層6を電気的に接続するための貫通導体11の大きさが小さくなり、貫通導体11を介して母基板1の表裏面をめっき液が循環することが妨げられてしまい、配線基板領域2の主面の配線導体3に被着されるめっき層の厚みが安定しなくなる可能性がある。   Here, it is preferable that the outer peripheral metallized layer 6 formed alternately on the upper and lower main surfaces of the disposal margin region 4 over the entire circumference has a width of about 2 to 5 mm. When the width of the outer peripheral metallized layer 6 is less than 2 mm, the function as an auxiliary electrode is likely to be reduced, and the thickness of the wiring conductor 3 in the wiring board region 2 is likely to vary. In addition, the size of the through conductor 11 for electrically connecting the outer peripheral metallized layer 6 alternately to the upper and lower main surfaces of the disposal margin region 4 over the entire circumference is reduced, and the front and back surfaces of the mother board 1 are interposed via the through conductor 11 The plating solution may be prevented from circulating, and the thickness of the plating layer deposited on the wiring conductor 3 on the main surface of the wiring board region 2 may become unstable.

また、外周メタライズ層6の幅が5mmを越えると、母基板1に形成する配線基板領域2の取り個数が減少するため生産性が悪く、また、補助陰極として作用する外周メタライズ層6にめっき成分(ニッケルや金等)が被着されて消費されるため、めっき液の寿命が短くなりやすい。   Further, if the width of the outer peripheral metallization layer 6 exceeds 5 mm, the number of wiring board regions 2 formed on the mother substrate 1 is reduced, resulting in poor productivity, and the outer metallization layer 6 acting as an auxiliary cathode has a plating component. Since (nickel, gold, etc.) is deposited and consumed, the life of the plating solution tends to be shortened.

また、本発明の多数個取り配線基板は、外周メタライズ層6は、配線基板領域2全体の一つの辺部において、その辺部に沿っているものの形状が全て同じであるとともに、平面視で全体として直線状に形成されていることが好ましい。   Further, in the multi-piece wiring board of the present invention, the outer peripheral metallized layer 6 has the same shape in one side part of the whole wiring board region 2 along the side part, and the whole in a plan view. It is preferable that it is formed linearly.

これにより、母基板1の上下各主面のそれぞれの全周にわたって外周メタライズ層6と母基板1との間で焼成時の収縮率の違いに起因して発生する応力がほぼ等しくなり、より一層確実に母基板1の反りを防止することが可能となる。   As a result, the stress generated due to the difference in shrinkage rate during firing between the outer peripheral metallized layer 6 and the mother substrate 1 over the entire circumference of each of the upper and lower main surfaces of the mother substrate 1 becomes substantially equal. It is possible to reliably prevent the mother substrate 1 from warping.

この場合、外周メタライズ層6は、捨て代領域4の上下各主面の全周で、その厚みを5〜20μmの厚みとなるように形成することが望ましい。外周メタライズ層6の厚みが5μm未満となると、各貫通導体11との接続厚みが薄くなってしまい、電気的接続性が悪化する恐れがある。また、外周メタライズ層6の厚みが20μmを超えると、母基板1の厚みが1mm以下と薄い場合において、局所的に基板の反りが発生する可能性があるためである。   In this case, it is desirable that the outer peripheral metallized layer 6 is formed so as to have a thickness of 5 to 20 μm on the entire circumference of the upper and lower main surfaces of the disposal margin region 4. When the thickness of the outer peripheral metallized layer 6 is less than 5 μm, the connection thickness with each through conductor 11 becomes thin, and the electrical connectivity may be deteriorated. Further, if the thickness of the outer peripheral metallized layer 6 exceeds 20 μm, the substrate may be locally warped when the thickness of the mother substrate 1 is as thin as 1 mm or less.

また、外周メタライズ層6は、搭載部が形成されている側の主面(図1の例では上面)の各辺で、配線基板領域2の四角形状の配列の角部に接する部位まで形成するようにしておくことが好ましい。   Further, the outer peripheral metallized layer 6 is formed on each side of the main surface (upper surface in the example of FIG. 1) on the side where the mounting portion is formed up to a portion in contact with the corner of the rectangular array of the wiring board region 2. It is preferable to do so.

これにより、配線導体3に被着されるめっき層の厚さが特に厚くなる傾向のある四角形状の配列の角部において、搭載部に露出する配線導体3にめっき層が厚く形成されることをより有効に防止できるので、配線導体3の露出部分に対する電子部品の電気的な接続の信頼性をより高く確保することができる。電子部品の電極がボンディングワイヤや半田等を介して電気的に接続される配線導体3に被着されるめっき層が厚くなり過ぎると、めっき層の内部応力が大きくなるので、ボンディングや半田付け時の応力と合わさって配線導体3が母基板1から剥がれ易くなるおそれがある。   This ensures that the plating layer is formed thick on the wiring conductor 3 exposed to the mounting portion at the corners of the square array in which the thickness of the plating layer deposited on the wiring conductor 3 tends to be particularly thick. Since it can prevent more effectively, the reliability of the electrical connection of the electronic component with respect to the exposed part of the wiring conductor 3 can be ensured more highly. If the plating layer deposited on the wiring conductor 3 to which the electrodes of the electronic component are electrically connected via bonding wires, solder, or the like becomes too thick, the internal stress of the plating layer increases, so that during bonding and soldering In combination with this stress, the wiring conductor 3 may be easily peeled off from the mother board 1.

以上の結果、電気的な接続信頼性に優れた配線基板を作製可能な多数個取り配線基板を提供することができる。   As a result, it is possible to provide a multi-piece wiring board capable of producing a wiring board excellent in electrical connection reliability.

なお、本発明は以上の実施の形態の例に限定されるものではなく、本発明の要旨を逸脱しない範囲で種々の変更を加えても何ら差し支えない。例えば、この例では7行×5列の35個の配線基板領域2で構成された母基板1としたが、その他の配列個数の母基板で構成してもよいのは言うまでもない。   It should be noted that the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the present invention. For example, in this example, the mother board 1 is composed of 35 wiring board regions 2 of 7 rows × 5 columns, but it is needless to say that the mother board 1 may be composed of other arrangements of mother boards.

また、貫通導体11は、母基板1に形成した貫通孔の内壁面だけではく、貫通孔内を充填するようにして形成してもよい。この場合、母基板1の上下の主面間のめっき液の流通を良好に確保するために、ダミーの貫通孔(図示せず)を捨て代領域4に形成してもよい。   Further, the through conductor 11 may be formed so as to fill not only the inner wall surface of the through hole formed in the mother board 1 but also the inside of the through hole. In this case, a dummy through hole (not shown) may be formed in the discard margin region 4 in order to ensure a good distribution of the plating solution between the upper and lower main surfaces of the mother substrate 1.

また、図1に示した例では、全部の分割溝5’の延長線上に貫通導体11を形成しているが、貫通導体11は、全部の分割溝5’の延長線上に形成する必要はなく、複数の分割溝5’の延長線間に形成するようにしてもよい。ただし、この場合には、分割溝5’は、外周メタライズ層6を分断しないように、外周メタライズ層6よりも内側までの部位で外周メタライズ層6に達しないようにして形成する必要がある。   In the example shown in FIG. 1, the through conductors 11 are formed on the extended lines of all the divided grooves 5 ′. However, the through conductors 11 need not be formed on the extended lines of all the divided grooves 5 ′. Further, it may be formed between the extended lines of the plurality of dividing grooves 5 ′. However, in this case, it is necessary to form the dividing groove 5 ′ so as not to reach the outer peripheral metallized layer 6 in a portion up to the inner side of the outer peripheral metallized layer 6 so as not to divide the outer peripheral metallized layer 6.

(a)は本発明の多数個取り配線基板の実施の形態の一例を示す平面図、(b)は(a)の多数個取り配線基板のA−A’線における断面図である(A) is a top view which shows an example of embodiment of the multi-cavity wiring board of this invention, (b) is sectional drawing in the A-A 'line of the multi-cavity wiring board of (a). (a)は従来の多数個取り配線基板の実施の形態の一例を示す平面図、(b)は(a)の多数個取り配線基板のB−B’線における断面図である(A) is a top view which shows an example of embodiment of the conventional multi-cavity wiring board, (b) is sectional drawing in the B-B 'line of the multi-cavity wiring board of (a).

符号の説明Explanation of symbols

1・・・・・母基板
2・・・・・配線基板領域
3・・・・・配線導体
4・・・・・捨て代領域
5・・・・・境界
5’・・・・分割溝
6・・・・・外周メタライズ層
11・・・・貫通導体
DESCRIPTION OF SYMBOLS 1 ... Mother board 2 ... Wiring board area | region 3 ... Wiring conductor 4 ... Discard allowance area 5 ... Boundary 5 '... Dividing groove 6 ... Outer metallization layer 11 ... Penetration conductor

Claims (2)

主面の中央部に複数の配線基板領域が縦横に全体として四角形状に配列形成されるとともに、外周部に枠状の捨て代領域が形成された四角形状の母基板と、前記各配線基板領域に形成された配線導体と、前記配線基板領域の境界に形成された分割溝と、前記捨て代領域の前記分割溝の延長線上に形成された貫通導体と、隣接する該貫通導体間を連結するとともに前記捨て代領域の上下主面に交互に全周にわたって形成された外周メタライズ層とを具備していることを特徴とする多数個取り配線基板。 A plurality of wiring board regions arranged vertically and horizontally at the center of the main surface as a whole in a square shape, and a rectangular mother board having a frame-shaped discard margin region formed on the outer periphery, and each of the wiring board regions A wiring conductor formed on the wiring board region, a dividing groove formed at a boundary of the wiring board region, a through conductor formed on an extension line of the dividing groove in the discarding region, and the adjacent through conductors are connected to each other. And an outer peripheral metallization layer formed alternately over the entire circumference on the upper and lower main surfaces of the discard margin region. 前記外周メタライズ層は、前記配線基板領域全体の一つの辺部において、その辺部に沿っているものの形状が全て同じであるとともに、平面視で全体として直線状に形成されていることを特徴とする請求項1記載の多数個取り配線基板。 The outer peripheral metallization layer is characterized in that, in one side portion of the entire wiring board region, all of the shapes along the side portion are the same and formed linearly as a whole in plan view. The multi-cavity wiring board according to claim 1.
JP2004093855A 2004-03-26 2004-03-26 Multiple wiring board Pending JP2005285866A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234657A (en) * 2006-02-27 2007-09-13 Kyocera Corp Multiple patterning wiring board
US8024857B2 (en) 2008-11-07 2011-09-27 Hynix Semiconductor Inc. Substrate for semiconductor package having a reinforcing member that prevents distortions and method for fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234657A (en) * 2006-02-27 2007-09-13 Kyocera Corp Multiple patterning wiring board
JP4594253B2 (en) * 2006-02-27 2010-12-08 京セラ株式会社 Multiple wiring board
US8024857B2 (en) 2008-11-07 2011-09-27 Hynix Semiconductor Inc. Substrate for semiconductor package having a reinforcing member that prevents distortions and method for fabricating the same

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